JP2970985B2 - Demodulator for L-MSK signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to a demodulator, in particular L
The present invention relates to a demodulator used for demodulating an MSK signal .

[0002]

2. Description of the Related Art In FM multiplexing, L-MSK (level-controlled minimum shift keyin), which is a kind of MSK, is used.
g) is used (for example, IEICE Autumn Meeting 1991, B-230 “Field experiment of modulation scheme for mobile reception FM multiplex broadcasting”). The demodulation method of L-MSK is M
It is exactly the same as SK, and differential detection is used in mobile communication. MSK is considered to be a kind of FSK, and in FM multiplexing, 72 k is used for data “0” given to a modulator.
A carrier frequency of 80 kHz is assigned to data "1" which is also supplied to the modulator (see FIG. 9). However, the carrier phase maintains continuity even at the data change point. The data transfer rate is 16 kHz. This means that the data “0” contains 4.5 period carriers in one data period (1 / 16K), and the data “1” contains five period carriers in one data period (1 / 16K). Means

[0003] Conventionally, differential detection has been processed in an analog manner. The differential detection multiplies a received signal by a delayed signal obtained by transmitting the received signal for one data period. FIG. 9 shows a detection output of the conventional differential detection. Note that FIG.
Each upper stage of (A) to (D) is a delay signal, and each middle stage is a received signal. As shown in FIG. 9A, the data is “1”.
If it continues with 1 ", the positive DC component and 2
A harmonic having twice the frequency is obtained as an output. FIG.
As shown in (B), when the data is continuous with “00”, a negative DC component and a harmonic having a frequency twice the frequency of the carrier are obtained as an output. As shown in FIG. 9C, when the data continues to be "10", a signal is obtained in which a harmonic component is added to a component that changes from positive to negative. As shown in FIG. 9 (D), when the data continues to be "01", a signal is obtained in which a harmonic component is added to a component that changes from negative to positive. By removing the harmonic components from the delayed detection output, a demodulated signal is obtained.

[0004]

However, in the conventional detection method that performs analog processing , the amplitude of the L-MSK signal is reduced.
Since it changes as needed, it is susceptible to noise, and since harmonic components exist after multiplication, half of the differential detection output must be removed, resulting in poor signal utilization efficiency. Therefore, the error rate characteristics were poor. Therefore, a main object of the present invention is to provide a demodulator having improved error rate characteristics.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a demodulator for demodulating an L-MSK signal whose amplitude level changes, a comparator for binarizing the L-MSK signal, and delaying the output of the comparator. The output of the shift register, the multiplication means for multiplying the output of the comparator and the output of the shift register, the filter means for removing the high frequency component of the output of the multiplication means , and the output of the filter means are the same two data.
A first state indicating continuity and different data follow
The maximum likelihood decision is made using only the second state indicating that
An L-MSK signal demodulator including a maximum likelihood determining means for obtaining a value output .

[0006]

[Action] When L -MSK signal is applied to the comparator, L-MSK signal is binarized. This binarized LM
SK signal is, thus, for example, one data to the shift register
Delayed for a period . Binary L-MSK from comparator
The signal and the binarized L-MSK signal from the shift register are multiplied by multiplication means such as an exclusive OR circuit.
If data continuous with "11" or "00" is sent, for example, a continuous output of "+1" or "-1" is obtained as an output from the multiplication means, so that no harmonic is generated and the signal is not generated. The utilization efficiency is improved, and the S / N is improved. Further, when data continuous with "10" or "01" is sent, a harmonic is generated as an output from the multiplying means, and in this case, the signal use efficiency is the same as the conventional one. Then, the output from the multiplication means is supplied to the filter means, and a high-frequency component is removed to obtain a demodulated signal.

Two such as "11" or "00"
In the first state in which the same data continues, the demodulated signal from the filter means has a double level as compared with the second state in which different data such as "10" or "01" has changed. Therefore, utilizing the demodulation characteristics, the maximum likelihood determination means such as a Viterbi decoder performs maximum likelihood determination on the output from the multiplication means and decodes the result.

[0008]

According to the present invention, the L-MSK signal is
Binarization by comparator, then shift register etc.
By digitally processing the demodulation using , the influence of noise is reduced, and the overall signal utilization efficiency is improved, so that the error rate characteristic is improved as compared with the related art. By performing the maximum likelihood determination, the characteristics can be further improved.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a demodulator 10 of this embodiment includes an input terminal 12. The input terminal 12 is supplied with, for example, an L-MSK signal which is a kind of digital modulation signal. Then, the comparator 14 which is a quantization means outputs L-
The MSK signal is a binarized MSK signal. The MSK signal output from the comparator 14 is applied to a shift register 16 serving as delay means, and is applied as a delayed signal delayed by one data period to one input of an exclusive OR circuit 18 serving as multiplication means. Also, M from the comparator 14
The SK signal is directly applied to the other input of the exclusive OR circuit 18. The exclusive OR circuit 18 multiplies the delay signal from the shift register 16 by the MSK signal from the comparator 14. Then, the obtained signal is provided to a low-pass filter 20 which is an extracting means. The low-pass filter 20 removes high-frequency components and noise of a given signal to obtain a demodulated signal. A digital signal is obtained by binarizing the demodulated signal from the low-pass filter 20 by the comparator 22, and output as a decoded output from the output terminal 24.

FIG. 2 shows the output after multiplication from the exclusive OR circuit 18 in the demodulator 10. Each upper stage in FIGS. 2A to 2D is a delay signal, and each middle stage is an MSK signal. First, as shown in FIG. 2A, data supplied to a modulator (not shown) on the transmission side is “1”.
In the case of continuous "1", a positive DC signal containing no harmonic is output from the exclusive OR circuit 18. In addition, as shown in FIG. If they are continuous, a negative DC signal containing no harmonic is output from the exclusive OR circuit 18. Further, FIG.
As shown in (1), when the data continues to be "10", the exclusive OR circuit 18 outputs a signal including a harmonic. Also, as shown in FIG. 2D, when the data continues to be “01”, a signal including a harmonic is output from the exclusive OR circuit 18.

Therefore, as shown in FIGS. 2 (A) and 2 (B), when the data is continuous with "11" or "00", no harmonic is generated and the signal utilization efficiency is good. Understandably, S / N is improved. On the other hand, as shown in FIGS. 2C and 2D, the data is "10" or "0".
When the signal continues to 1 ", a harmonic is generated. In this case, the signal use efficiency is the same as that of the conventional art.

Here, FIG. 3 shows that the modulator on the transmitting side has “10”.
7 shows a demodulated signal from the low-pass filter 20 and a decoded output (judgment value) from the comparator 22 when data “00100” (a correct value to be demodulated) is given. In this case, until the signal passes through the low-pass filter 20 Contains some noise, so the low-pass filter 2
From 0, a demodulated signal as shown in FIG. 3 is obtained. If the determination by the comparator 22 is performed at the time indicated by the arrow, a decoded output of "1100010" is obtained at the output terminal 24. In this case, the threshold value of the comparator 22 is set to 0. In this embodiment, the C / N can be improved by improving the signal use efficiency, so that the error rate characteristics can be improved as compared with the related art. Note that ideally, when the same data is continuous (“11” or “00”), compared to when the data changes (“10” or “01”),
The demodulated signal from the low-pass filter 20 has a double level. FIG. 4 shows a demodulator 30 utilizing this demodulation characteristic.

A demodulator 30 of another embodiment shown in FIG. 4 is different from the demodulator 10 of FIG.
An A / D converter 32 and a Viterbi decoder 34 as a maximum likelihood determining means are used. Here, assuming that the data input to the modulator on the transmission side is b _k and the ideal output input to the Viterbi decoder 34 is c _k , the relationship shown in Table 1 is established.

[0015]

[Table 1]

Here, k represents time. The threshold value of _ck is ± 0.75. That is, if the absolute value of _ck is 0.
If _k is 75 or more, c _k is regarded as 1.0 or −1.0, and c _k
If the absolute value of _k is less than 0.75, then _ck is 0.5 or-
Assume 0.5. As an input to the Viterbi decoder 34,
Assuming that the state when "0" is input is S0 and the state when "1" is input is S1, the relationship between the data sequence {b _k } and the ideal output sequence {c _k } is shown in FIG. Can be represented by a state transition diagram. Here, the symbols attached to the directed lines represent b _k / c _k . FIG. 6 is a trellis diagram showing the state transition diagram of FIG.

The actual input d to the Viterbi decoder 34
_k is _obtained by adding noise to the output _ck .
Assuming that this noise has a Gaussian distribution with a mean value of 0, the actual output data sequence {d _k } is _obtained by adding an ideal output sequence {c _k } and a Gaussian noise sequence with a mean value of {n _k }. It will be combined. Equation 1 shows.

[0018]

D _k = c _k + n _{k When the} Viterbi algorithm is applied to the systems shown in FIGS. 5 and 6, Equation 2 is derived.

[0019]

[Number 2] _{M k (S 1) = min} {M k-1 (S 1) + L k 11, M k-1 (S 0) + L k 01} M k (S 0) = min {M k-1 ^{_{(S 1) + L k 10}} , M k-1 (S 0) + L k 00} where, M _k (S ₁₎ is in the state S ₁ at time k metric, M _k (S ₀₎ is the state at time k Represents the metric of S ₀ . L _k ^ij (i, j = 0, 1) represents the likelihood of the branch from the state S _{i at} time k−1 to the state S _j at time k. Note that the likelihood of this branch is calculated using a negative log likelihood function as shown in Expression 3.

[0020]

(Equation 3)

In Equation 3, since the only variable is c _k , the actual branch likelihood may be −2d _k c _k + c _k ^{2. In} this embodiment, 0.25 is further subtracted. ,
The normalized metric shown in Equation 4 is obtained as -0.25-2d _k c _k + c _k ² .

[0022]

(4) m _k (S ₁ ) = min _- 1m _{k -1} (S ₁ ) −2d _k +0.75, m _k-1 (S ₀ ) −d _k ｝ m _k (S ₀ ) = min ｛m _{k-1 (S 1) +} d k, m k-1 (S 0) + 2d k +0.75} _{^{Note, L 11 = -2d k + 0.75}} , L 01 = -d k, L 10
= D _k , L ⁰⁰ = 2d _k +0.75.

FIG. 7 shows an example of a simulation in which a path is determined using Equation 4. In FIG. 7, ｛1,
It is assumed that a data sequence {b _k } of 0, 0, 0, 1, 0, 0} is transmitted. Then, the Viterbi decoder 3
4 is an ideal output sequence {c _k } = {1, −
0.5, -1, -1, 0.5, -0.5, -1}. An output sequence {d _k } obtained by adding an appropriate Gaussian noise sequence { _nk } to this value is _represented by Viterbi. Used as the actual input to decoder 34. FIG. 7 shows a calculation example of the metric calculated using Equation 4, and the selected branch is shown on a trellis diagram. In the Viterbi decoding method, a decoded output is obtained by selecting a more probable branch at each time point from two branches that reach state S ₁ (state S ₀ ). That is, the branch selected at each time is divided into a branch that is interrupted at a certain time and a branch that follows. The subsequent one is called a surviving path, and a value corresponding to the surviving path is a decoded output. In FIG. 7, the state ΔS ₁ → S ₁ → S ₀
→ S ₀ → S ₀ → S ₁ → S ₀ } is a surviving path, and the decoded output is {1, 0, 0,.
0, 1, 0}.

Note that the metrics m _k-1 (S ₁ ) and m _k-1 (S ₀ ) in the immediately preceding state in FIG. 7 are M _k-1 (S ₁ ) and Note that, unlike M _k-1 (S ₀ ), only the relative differences are used. That is, from the number 4, m _k (S _{1) is, m k-1 (S 1} ) -2d
_k +0.75 and m _k-1 (S ₀₎ to select the smaller of the _{-d k, m k (S 0} ) _{is, m k-1 (S 1} ) + d k and m
The smaller one of _k-1 (S ₀ ) + 2d _k +0.75 is selected. By this processing, a branch is selected. And m
_The smaller of _k (S ₁ ) and _mk (S ₀ ) is set to 0,
The larger one is the difference between the two. For example, k = 2 shown in FIG.
In the case of ( ₁ ), m ₁ (S ₁ ) and m ₁ (S ₀ ) are obtained as follows. First, m ₁ (S ₁ ) is −1.05 (=
m ₀ (S ₁ ) + L ₁ ¹¹ ) and 1.65 (= m ₀ (S ₀ ) +
L ₁ ⁰¹ ) and the smaller one (−1.05), m ₁
(S ₀₎ is chosen to _{0.90 (= m 0 (S 1} ) + L 1 10) and _{5.10 (= m 0 (S 0} ) + L 1 00) the smaller of the (0.90). And m ₁ (S ₁ ) is m ₁
Since it is smaller than (S ₀ ), m ₁ (S ₁ ) = 0.00, and m ₁ (S ₀ ) = 0.90 − (− 1.05) = 1.9
5 is assumed. The same applies to other cases.

Such processing is performed by the Viterbi Deco shown in FIG.
This is performed by the reader 34. From low pass filter 20
After the A / D converter 32 demodulates the demodulated signal of
The output sequence ｛d is output to the Viterbi decoder 34._k｝ Is given
Likelihood is determined. First, output d_kIs input from the receiving end 36.
The likelihoods L of the branches are calculated by the arithmetic units 38 and 40, respectively._k ¹¹
(= -2d_k+0.75) and L_k ⁰⁰(= + 2d_k+
0.75) is calculated. Branch likelihood L⁰¹And L^TenNitsu
And L_k ⁰¹= -D_kAnd L_k ^Ten= D_kIs
Therefore, no special operation is required. The likelihood of these branches is
Add the likelihood (metric) of the path leading to each state
And the likelihood (metric) of the new path is calculated.
You. That is, from the minimum value determiner 54 to the delay circuit 56 and
And the previous state output through
Metric m_k-1(S₁) And m_k-1(S₀) And each branch
Are added in adders 42, 46 and 48,
The difference is subtracted by the subtractor 44. Thereby, the adder 42
M_k-1(S ₁) -2d_k+0.75 from subtractor 44
m_k-1(S₀) -D_k, From adder 46 to m_k-1(S₁)
+ D_k, From adder 48 to m_k-1(S₀) + 2d_k+0.
75 are each obtained. And an adder 42 and a subtractor
Each output from 44 is processed by a minimum value decision unit 50
And the smaller value is selected. At this time, m_k-1(S
₀) -D_kIs selected, ie, S₀To S₁To
If there is a transition, S₁Shift register corresponding to
60 is S₀The contents of the shift register 62 corresponding to
In order to succeed, shift register 6
The pulse for transferring data to 0 is the minimum value judgment unit
50 to the shift register 60.

Similarly, the outputs of adders 46 and 48 are
Processed by the minimum value determiner 52, the smaller value is selected. At this time, if m _k-1 (S ₁ ) + d _k is selected,
That is, when there is a transition from S ₁ to S ₀ is, S ₀
To shift register 62 that corresponds to the take over the contents of the shift register 60 corresponding to S _1, pulses for transferring data from the shift register 60 to the shift register 62, shift register 62 from the minimum value determiner 52
Given to.

The shift registers 60 and 62 then
A shift operation is performed. At this time, data of 1 and 0 are loaded into the leftmost stages of the shift registers 60 and 62, respectively. It is desirable that each of the shift registers 60 and 62 be configured in approximately 20 stages. By constructing shift registers 60 and 62 in, for example, about 20 stages, for example, k in the trellis diagram of FIG.
= 6 can be dealt with in a case where crosses of branches appear continuously.

Then, the minimum value decision units 50 and 52
Each of the standardized metrics m _k (S ₁ ) and m _k (S ₀ ), that is, the smaller one of the two input metrics, is determined by the minimum value determiner 54.
Output to The minimum value determiner 54 detects a smaller one of the two input standardized metrics. In particular, the minimum value determiner 54 includes the shift registers 60 and 6
This is effective when the outputs from the two differ. _mk
If (S ₁ ) is smaller, the minimum value determiner 54 determines that S ₁
To select the output of the shift register 60 corresponding to S ₁ to select the direction of the path leading to and turns on the switch of the output buffer 64, switch off the output buffer 66, decoded output from the output terminal 24 Is output. On the other hand, if m _k (S ₀ ) is smaller, the operation is reversed.
In this way, optimal paths are sequentially selected.

Note that the minimum value judging unit 54
Metric m_k(S₁) And m _k(S₀) Relative
In order to obtain a good metric, as described above, m_k(S
₁M) if is large_k(S₀) To 0 and m_k(S₁)
M_k(S₁) -M_k(S₀)
Then m_k(S₀If) is large, make the opposite definition,
Prevents the release of ricks.

According to the demodulator 30, the decoded output is {1, 0, 0, 0, 1, 0} as described above. Therefore, the decoded output from the modulator 10 of FIG. 1 in which the comparator 22 detects the decoded output by the threshold determination using 0 as the threshold value is {1, 1, 0, 0, 0, 1, 0}, so that the Viterbi decoding is performed. The decoding error of the demodulator 30 of FIG. 3 using the method is further reduced. Then, the error rate characteristic is further improved by about 3 dB.

[0031] Also, as the maximum likelihood determination means, any means other than the Viterbi decoder may be used. Further, in Equation 3, a positive log likelihood function may be used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart showing inputs and outputs of the exclusive OR circuit of the embodiment in FIG. 1;

3 is an illustrative view showing an MSK signal from a comparator 14, a demodulated signal from a low-pass filter 20, and a decoded output from a comparator 22 in the embodiment of FIG. 1;

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a state transition diagram in the embodiment in FIG. 4;

FIG. 6 is a trellis diagram in the embodiment of FIG. 4;

FIG. 7 is a diagram illustrating an example of calculation of metrics and a trellis diagram in the embodiment of FIG. 4;

FIG. 8 is a block diagram showing a Viterbi decoder used in the embodiment of FIG.

FIG. 9 is a waveform chart according to the related art.

[Explanation of symbols]

 10, 30 demodulators 14, 22 comparators 16, 60, 62 shift register 18 exclusive OR circuit 20 low-pass filter 32 A / D converter 34 Viterbi decoder

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yoshikazu Tomita 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Masayuki Takada 1-110 Kinuta, Setagaya-ku, Tokyo No. Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Toru Kuroda 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Tadashi Isobe 1-10-11 Kinuta, Setagaya-ku, Tokyo No. Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Satoshi Yamada 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (56) References JP-A-1-291536 (JP, A) JP-A-60-146557 (JP, A) JP-A-4-281647 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 27/14

Claims (2)

(57) [Claims] 1. A demodulator for demodulating an L-MSK signal whose amplitude level changes, a comparator for binarizing the L-MSK signal, a shift register for delaying an output of the comparator, multiplying means for multiplying the output and the output of the shift register, the filter means removes a high frequency component of an output of said multiplication means and an output of said filter means, two identical Day
The first state and the different data indicating that
The maximum likelihood judgment is made using only the second state indicating that
A demodulator for an L-MSK signal, comprising: a maximum likelihood determining means for obtaining a binary output . 2. The maximum likelihood determining means includes a Viterbi decoder.
No, demodulator L-MSK signal according to claim 1, wherein.