JP2970085B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2970085B2
JP2970085B2 JP18284991A JP18284991A JP2970085B2 JP 2970085 B2 JP2970085 B2 JP 2970085B2 JP 18284991 A JP18284991 A JP 18284991A JP 18284991 A JP18284991 A JP 18284991A JP 2970085 B2 JP2970085 B2 JP 2970085B2
Authority
JP
Japan
Prior art keywords
semiconductor element
cap
semiconductor device
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18284991A
Other languages
Japanese (ja)
Other versions
JPH0529400A (en
Inventor
周幸 加藤
季夫 森重
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP18284991A priority Critical patent/JP2970085B2/en
Publication of JPH0529400A publication Critical patent/JPH0529400A/en
Application granted granted Critical
Publication of JP2970085B2 publication Critical patent/JP2970085B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

【0002】[0002]

【従来の技術】従来の半導体装置は、半導体素子をステ
ムあるいはリードフレームに搭載しワイヤーボンディン
グ法や、テープオートメイテッドボンディング法やフリ
ップチップ法等により外部接続がなされていた。又、図
4に示すように、半導体素子1の電極パッド7に金錫共
晶合金10等により直接半導体素子にマイクロピン3を
取り付け、半田9により多層配線基板11に実装されて
いた(例えば、特願昭63−279789)。
2. Description of the Related Art In a conventional semiconductor device, a semiconductor element is mounted on a stem or a lead frame, and external connection is made by a wire bonding method, a tape automated bonding method, a flip chip method, or the like. Further, as shown in FIG. 4, the micro pins 3 are directly attached to the semiconductor element 1 with the gold-tin eutectic alloy 10 or the like on the electrode pad 7 of the semiconductor element 1 and mounted on the multilayer wiring board 11 with the solder 9 (for example, Japanese Patent Application No. 63-279789).

【0003】[0003]

【発明が解決しようとする課題】この従来の半導体装置
では、ワイヤーボンディング法では電極パッドピッチが
狭くなると隣りのワイヤーにキャピラリが当ってしま
い、半導体装置の小型化に適してはいないし、フリップ
チップようにチップ上に形成されたバンプと実装基板を
半田によって取り付ける方法では半導体素子と実装基板
との熱膨張率が異なる為、温度変化により半田接続部に
ストレスがかかり、破断等による接続不良が発生してし
まう。
In this conventional semiconductor device, if the electrode pad pitch becomes narrow in the wire bonding method, a capillary hits an adjacent wire, which is not suitable for miniaturization of the semiconductor device. In the method in which the bumps formed on the chip and the mounting board are attached by soldering as described above, the thermal expansion coefficients of the semiconductor element and the mounting board are different, so that a stress is applied to the solder connection portion due to a temperature change, and a connection failure due to breakage or the like occurs. Resulting in.

【0004】又、上記改善案として、図4に示すよう
に、半導体素子の電極パッド上に金錫共晶合金により、
マイクロピンを形成する方法もあるが、この方法では、
半導体素子の電極パッド上にマイクロピンを整列させ、
接合することが非常に困難であり、一ピンづつ接合させ
なければならない為、非常に時間を要すことになる。さ
らに半導体素子そのもので実装することから、外部から
の力に対して弱く、割れやすいという問題があった。
As an improvement, as shown in FIG. 4, a gold-tin eutectic alloy is formed on an electrode pad of a semiconductor element.
There is also a method of forming micro pins, but in this method,
Align the micro pins on the electrode pads of the semiconductor element,
Joining is very difficult, and since it is necessary to join one pin at a time, it takes a very long time. Furthermore, since the semiconductor device is mounted by itself, there is a problem that the semiconductor device is weak against external force and is easily broken.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は、
半導体素子の回路形成面を下向きにして、下側面に半導
体素子の電極パッドと同配列にしたマイクロピンが貫通
している基板を有し、半導体素子上面からは、弾性率の
高い材料で貼付けたキャップを半導体素子に圧力がかか
る様な状態で覆っている。それによって、マイクロピン
と半導体素子の電極パッドとが、電気的接続してマイク
ロピンが外部接続端子となる。
According to the present invention, there is provided a semiconductor device comprising:
With the circuit formation surface of the semiconductor element facing down, the lower surface has a substrate through which micropins arranged in the same arrangement as the electrode pads of the semiconductor element penetrate, and from the upper surface of the semiconductor element, affixed with a material having a high elastic modulus. The cap is covered so that pressure is applied to the semiconductor element. Thereby, the micropin and the electrode pad of the semiconductor element are electrically connected, and the micropin becomes an external connection terminal.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例の半導体装置の断面図であ
る。基板2はAlN等の無機材料であり、そこには半導
体素子1の電極パッド7と同配列で並んでいるマイクロ
ピン3が貫通して立っている。ピッチは120〜180
μmであり、ピン径は60〜110μmであり、材質は
熱伝導率が良く比較的弾性率の低いCu系材料を使用し
た。又電極パッド7とマイクロピン3がずれない様に、
半導体素子1の外径寸法と基板2の凹部寸法の隙間をほ
ぼゼロにした。キャップ5も基板2同様、無機材料であ
り、3の内面には高弾性材4が貼られている。高弾性材
4は、この場合封止時の温度に耐え得るポリイミド系の
フィルムを使用した。そして、半導体素子1に2〜20
0kgf/mm2 の圧力がかかる様にし、低融点ガラス
等のロー材6で封止する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to one embodiment of the present invention. The substrate 2 is made of an inorganic material such as AlN, and the micro pins 3 arranged in the same arrangement as the electrode pads 7 of the semiconductor element 1 penetrate there. Pitch is 120-180
μm, the pin diameter was 60 to 110 μm, and the material used was a Cu-based material having good thermal conductivity and a relatively low elastic modulus. Also, so that the electrode pad 7 and the micro pin 3 do not shift,
The gap between the outer diameter dimension of the semiconductor element 1 and the recess dimension of the substrate 2 was made almost zero. The cap 5 is also made of an inorganic material like the substrate 2, and the high elastic material 4 is attached to the inner surface of the cap 3. In this case, a polyimide film that can withstand the temperature at the time of sealing was used as the high elastic material 4. The semiconductor element 1 has 2 to 20
A pressure of 0 kgf / mm @ 2 is applied, and sealing is performed with a brazing material 6 such as low melting point glass.

【0007】図3は、高弾性材4の上面を示す例であ
る。図の様に中をくり抜き、電極パッド7とマイクロピ
ン3の接触する箇所のみに圧力がかかる様にすることに
より、低い圧力で済み、又、半導体素子中央部に力がか
からないことから、半導体素子の割れ等を防ぐことがで
きる。本実施例の封止構造は密閉型であることから、外
部からの水の侵入等がなく、耐湿性等の信頼性も良い。
FIG. 3 is an example showing the upper surface of the high elastic material 4. As shown in the figure, the inside is hollowed out so that pressure is applied only to the portion where the electrode pad 7 and the micropin 3 are in contact with each other, so that a low pressure is required and no force is applied to the center of the semiconductor element. Cracks and the like can be prevented. Since the sealing structure of the present embodiment is a closed type, there is no invasion of water from the outside and the reliability such as moisture resistance is good.

【0008】図2は本発明の第2の実施例の半導体装置
の縦断面図である。本実施例の基盤2は、ガラス布エポ
キシ積層板等の有機材料であり、座ぐりをすることによ
り凹部を設ける。マイクロピン3は、あらかじめ開けら
れたスルーホールに整列され、半田等により固定する。
キャップ5は、PPS(ポリフェニレンサルファイド)
等のエンジニアリングプラスチックの成形品を使用す
る。内面には、シリコンゴム等の高弾性材4を貼付け
る。キャップ5にはツメ5aを設けて、基盤2と機械的
に取り付ける。半導体素子1には電極パッド部以外を絶
縁保護する為、ポリイミド樹脂膜等のパッシベーション
膜8が設けられている。本実施例は安価で軽量につくる
ことができる。
FIG. 2 is a longitudinal sectional view of a semiconductor device according to a second embodiment of the present invention. The base 2 of this embodiment is made of an organic material such as a glass cloth epoxy laminate, and is provided with a concave portion by counterbore. The micro pins 3 are arranged in through holes that have been opened in advance, and are fixed with solder or the like.
The cap 5 is made of PPS (polyphenylene sulfide)
Use molded products of engineering plastics. A high elastic material 4 such as silicon rubber is attached to the inner surface. The cap 5 is provided with a claw 5a, and is mechanically attached to the base 2. The semiconductor element 1 is provided with a passivation film 8 such as a polyimide resin film for insulating and protecting portions other than the electrode pad portions. This embodiment can be made inexpensively and lightweight.

【0009】[0009]

【発明の効果】以上説明したように、本発明は、半導体
素子の回路形成面を下向きにして、下面側に半導体素子
の電極パッドと、同配列にしたマイクロピンが貫通して
いる基板を有し、半導体素子上面からは弾性率の強い材
料を貼付けたキャップを半導体素子に圧力がかかる様な
状態で覆いマイクロピンと半導体素子の電極パッドとを
電気的接続させたので、超小型パッケージが容易にで
き、外部からの影響に対しても強い半導体装置が可能と
なる。
As described above, the present invention has a substrate on which a circuit forming surface of a semiconductor element is directed downward, and the electrode pads of the semiconductor element and the micro pins arranged in the same arrangement penetrate the lower surface side. Then, the micro pin and the electrode pad of the semiconductor element are electrically connected from the top of the semiconductor element with a cap to which a material with a high elastic modulus is attached in a state where pressure is applied to the semiconductor element. As a result, a semiconductor device which is strong against external influences can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例の縦断面図。FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention.

【図2】本発明の第2の実施例の縦断面図。FIG. 2 is a longitudinal sectional view of a second embodiment of the present invention.

【図3】高弾性材4の平面図。FIG. 3 is a plan view of a high elastic material 4;

【図4】従来の実施例の縦断面図。FIG. 4 is a longitudinal sectional view of a conventional example.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 基板 3 マイクロピン 4 高弾性材 5 キャップ 6 ロー材 7 電極パッド 8 パッシベーション膜 9 半田 10 金錫共晶合金 11 多層配線板 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Substrate 3 Micro pin 4 High elastic material 5 Cap 6 Low material 7 Electrode pad 8 Passivation film 9 Solder 10 Gold-tin eutectic alloy 11 Multilayer wiring board

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体素子の回路形成面を下向きにして
配置し、前記半導体素子の下面に、前記半導体素子の電
極パッドと同配列のマイクロピンが立っている基板を配
置し、前記半導体素子の上面に圧力が加わる様にキャッ
プを前記半導体素子に被せて前記基板に固定し、前記半
導体素子の電極パッドと前記マイクロピンとが接触して
電気的に接続された半導体装置であって、少なくとも前
記キャップの、前記半導体素子の上面に接する面を、弾
性を有する有機材料で構成し、前記半導体素子の電極パ
ッドが配列されている上面のみに前記キャップが接触し
て前記半導体素子に圧力が加わっていることを特徴とす
る半導体装置。
1. A semiconductor device comprising: a semiconductor element having a circuit forming surface facing downward; a substrate on which micro pins having the same arrangement as electrode pads of the semiconductor element are arranged on a lower surface of the semiconductor element; A semiconductor device in which a cap is placed on the semiconductor element so as to apply pressure to the upper surface and fixed to the substrate, and an electrode pad of the semiconductor element and the micropin are in contact with and electrically connected to each other;
The surface of the cap in contact with the upper surface of the semiconductor element is
An electrode material of the semiconductor element.
The cap contacts only the top surface where the pads are
Wherein a pressure is applied to the semiconductor element .
【請求項2】 半導体素子の回路形成面を下向きにして
配置し、前記半導体素子の下面に、前記半導体素子の電
極パッドと同配列のマイクロピンが立っている基板を配
置し、前記半導体素子の上面に圧力が加わる様にキャッ
プを前記半導体素子に被せて前記基板に固定し、前記半
導体素子の電極パッドと前記マイクロピンとが接触して
電気的に接続された半導体装置であって、前記キャップ
と前記半導体素子との間に、前記半導体素子の電極パッ
ドが配列されている上面のみに接触する弾性体を介在さ
せたことを特徴とする半導体装置。
2. The circuit formation surface of a semiconductor device is directed downward.
Placed on the lower surface of the semiconductor element,
Arrange the board on which the micro pins of the same arrangement as the pole pads are standing.
And place the cap so that pressure is applied to the upper surface of the semiconductor element.
The semiconductor chip is fixed to the substrate by covering the semiconductor element.
When the electrode pad of the conductive element comes in contact with the micropin,
An electrically connected semiconductor device, wherein the cap is
Between the semiconductor element and the semiconductor element.
An elastic body that contacts only the upper surface where the
Wherein a that it has.
JP18284991A 1991-07-24 1991-07-24 Semiconductor device Expired - Fee Related JP2970085B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18284991A JP2970085B2 (en) 1991-07-24 1991-07-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18284991A JP2970085B2 (en) 1991-07-24 1991-07-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0529400A JPH0529400A (en) 1993-02-05
JP2970085B2 true JP2970085B2 (en) 1999-11-02

Family

ID=16125537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18284991A Expired - Fee Related JP2970085B2 (en) 1991-07-24 1991-07-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2970085B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2942800A (en) 1999-03-12 2000-10-04 Asahi Breweries, Ltd. Agitation tank for storing yeast solution, method of producing fermented foods such as beer using the agitation tank, and agitating vanes provided in the agitation tank

Also Published As

Publication number Publication date
JPH0529400A (en) 1993-02-05

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Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19990727

LAPS Cancellation because of no payment of annual fees