JP2967570B2 - Test apparatus and test method for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus and a test method for a semiconductor device, and more particularly to a function for evaluating and analyzing a storage semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a storage semiconductor device (hereinafter referred to as a memory IC)
That. Has been tested using a semiconductor tester (hereinafter referred to as a tester).

FIG. 5 is a schematic diagram of a memory IC tester. In the figure, 1 is a tester, 2 is a control unit, 3 is an external controller,
Reference numeral 4 denotes a pattern generating unit, 5 denotes a waveform forming unit, 6 denotes a determining unit, 7 denotes a converting unit, 9 denotes a fail memory unit, and 12 denotes an IC to be measured (hereinafter referred to as a DUT). When testing the electrical characteristics of the memory circuit of a memory IC or a microcomputer IC with a built-in memory,
The control unit 2 in the tester 1 causes the pattern generation unit 4 to generate an address signal and a data signal based on the test conditions. The waveform forming section 5 forms the waveforms of the address signal and the data signal, applies them to the DUT 12, and takes in the data signal from the DUT 12. The determination unit 6 determines the quality of the DUT 12 by comparing the data signal from the DUT 12 with an expected signal generated from the pattern generation unit 4. Memory I
In a memory circuit of C or a microcomputer IC with a built-in memory, tens to millions of cells (corresponding to one bit of storage) are two-dimensionally arranged. The bitmap function is used to evaluate the electrical characteristics of each cell of the memory.

In general, this bit map fetches the judgment result data output from the judging section 6 into the fail memory section 9 inside the tester 1 via the judging section 7 and transfers the fetched data in the fail memory section 9 to the control section. 2 or external controller 3
And displays the pass / fail result of each cell. Usually, the tester 1 performs a test while generating an address in a logical image for the DUT. Since the array of memory cells in the DUT is not arranged in a logical image, it must be converted to the actual array of cells. This conversion unit 7
Converts the logical image address and data array into an actual cell array. Therefore, the fail memory unit 9 stores pass / fail judgment data in an array equivalent to the actual cell array.

FIG. 2 is a circuit diagram of a flash memory which is a non-volatile memory element. For simplicity of explanation, an example of a 1-bit capacity is used. The flash memory stores 1,0 data by controlling the charge amount of the floating gate. For example, in the case of data reading, a cell is selected by a word line and a bit line, a predetermined voltage is applied to these wirings, and 1,0 data is determined by whether or not a transistor of the cell is turned on.

FIG. 3 shows a map display of the electrical characteristics of the transistors of the memory cell, which is called a bit map. This bit map corresponds to the 4-bit capacity flash memory shown in FIG. Cell a
, A predetermined voltage is applied to the word line, a cell that is turned on is temporarily set to “1”, and a cell that is not turned on is set to “0”, and the bit map becomes the map d in the drawing under the conditions of test 3. It is assumed that the cells a, c, and d are "ON", and only the cell b is "OFF". The threshold voltage (hereinafter referred to as Vth) of the transistor of each cell.
An example of bitmapping the threshold voltage is disclosed in Japanese Patent Application Laid-Open No. Hei 7-122611.

[0007]

The first problem is that the above-described conventional bit map function only maps a single test condition, for example, a pass / fail judgment result of each cell at an access time or a power supply voltage. It is. JP-A-7-122
The bitmap of the threshold value for each cell described in Japanese Patent No. 611 cannot be obtained by the conventional bitmap function. Also, Japanese Patent Application Laid-Open No. 7-122611 does not show a specific embodiment. In the flash memory, the transistor Vth is determined by the amount of charge of the floating gate, and data “1” and “0” are determined. Thus, the V of each cell
When evaluating th, the conventional bitmap function uses 1
Only a bitmap under one Vth test condition is obtained, and it merely maps whether or not the transistor Vth of each cell is higher than this Vth. That is, Vt
There is a problem that it is impossible to display a map of an analog amount as in h. The reason is that there is no means for calculating between bitmap data obtained under a plurality of test conditions.

The second problem is that arithmetic processing between a plurality of bitmap data cannot be performed, and, for example, a change in transistor characteristics of each cell before and after temperature stress and a change with time cannot be displayed in a bitmap.

[0009]

The IC tester of the present invention comprises:
A plurality of fail memory units, and pass / fail result data stored in these fail memories, and these data are read out,
A switching unit for sending to the bitmap memory unit;
From bitmap data obtained under multiple test conditions,
It has a function of calculating the transistor characteristics of the memory cells in the DUT for each cell, and a bitmap memory unit for storing the result. Further, the external controller connected to the IC tester has a function of calculating between a plurality of bitmap data and displaying the calculation result.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] An embodiment of the present invention will be described. FIG. 1 shows a first embodiment of an IC tester according to the present invention. In the figure, 8 is a switching unit, 10 is a fail memory unit, 1
1 is a bitmap memory unit. The other blocks are the same as those in FIG.

Next, the test method of the present invention will be described with reference to the bit map configuration diagram of the present invention shown in FIG. 3 by taking as an example a method of obtaining the Vth value of each cell of the 4-bit capacity flash memory of FIG. I do. Here, for simplicity of description, as the conditions of each test, the voltage applied to obtain Vth was set as follows: test 1 = 5 V, test 2 = 5.2
V, test 3 = 5.4V, test 4 = 5.6V, and test 5 = 5.8V.

In FIG. 3, maps b to f are bit maps of the results of test conditions 1 to 5, and maps g to g.
To i indicate exclusive ORs among the maps b and c, maps c and d, maps d and e, and maps e and f, respectively. The maps k to n are map data of each cell pass / fail boundary value under each test condition.

As shown in FIG. 3, first, a test is performed under test 1 conditions. The control unit 1 controls the switching unit 8 and selects the fail memory unit 9. The pass / fail data of each cell data sent from the judgment unit 6 is stored in the fail memory unit 9.

Next, the control unit 2 controls the switching unit 8,
Select the fail memory unit 10. The determination unit 6 stores each cell data under the condition of the test 2 transmitted from the conversion unit 7 in the fail memory unit 10. Now, assume that the cell that has been turned on is “1”, and the cell that is not turned on is “0”.
Assuming that the bit map under the condition (1) is map b, each cell has not been turned ON.

Next, if the bit map under the condition of test 2 is set as map c, only the cell c is turned on. The data of the map b is stored in the fail memory unit 9, and the data of the map c is stored in the fail memory unit 10. The control unit 2 reads data between the fail memory units 9 and 10, compares the data in the two memory units, and calculates a cell whose data is contradictory (different). Next, the control unit 2
The data code "2" corresponding to the immediately preceding test condition is stored in the bitmap memory unit 11 in the memory area corresponding to the cell.
Is stored.

Next, the control unit 2 controls the switching unit 8,
The fail memory unit 9 is selected, and the test is executed under the condition of test 3. The determination unit 6 stores the pass / fail data of each cell data sent from the conversion unit 7 in the fail memory unit 9. The control unit 2 reads data between the fail memory units 9 and 10, compares the data in the two memory units, and calculates a cell whose data is contradictory (different). Next, the control unit 2
The data code "3" corresponding to the immediately preceding test condition is stored in the bitmap memory unit 11 in the memory area corresponding to the cell.

As a result, on the map n, information indicating under what test condition each cell has changed is mapped, that is, a map of the threshold voltage Vth is displayed. Will be.

As described above, the control unit 2 compares the bitmap data in the two fail memory units 9 and 10, ie, the bitmap data under the immediately preceding test condition and the bitmap data under the current test condition, and compares the data. Is calculated (contradictory), and the data code corresponding to the current test condition is stored in the bitmap memory unit 11 in the memory area corresponding to the cell, thereby determining the pass / fail boundary condition of each memory cell. Ask. Eventually, the bit map memory unit 11 stores data corresponding to the map n after the end of the test under the five test conditions.

The control section 2 sends the final data, map n, to the external controller 3. The external controller 3 such as a workstation displays the map n in a bit map, creates a data file, and outputs the map n to a printer.

[Second Embodiment] As a second embodiment,
Although not shown, there is an example in which a fail memory unit has a number corresponding to the number of test conditions or a large-capacity fail memory is divided into a plurality of blocks and a bit map for each test condition is stored. Further, data can be stored in the fail memory unit by using a logical address and a data array, and when sending data to the bitmap memory, it can be replaced with an actual cell array.

Next, a description will be given of a calculation process between a plurality of bitmap data in the external controller 3 connected to the IC tester. FIG. 4 shows the embodiment. The plurality of bitmap data o and p collected by the above-described IC tester of the present invention are transferred to an external controller 3 such as a workstation.
Generates new bitmap data q by performing arithmetic processing, and has processing functions such as display and file creation. Examples of the calculation processing include calculation between the same cells, frequency distribution of the entire map, and the like.

More specifically, for example, Vth data before a temperature cycle is applied is stored in a map o in FIG. 4, and Vth data after a temperature cycle is stored in a map p. By creating, a map display of a cell having a large amount of change in the temperature cycle can be obtained.

[0023]

The IC tester according to the present invention comprises a plurality of fail memory units, a switching unit for storing pass / fail result data in these fail memories, reading these data, and sending the data to the bit map memory unit. By having a function of calculating the transistor characteristics of the memory cells in the DUT for each cell from the bitmap data obtained under a plurality of test conditions, and a bitmap memory unit for storing the result, each cell in the memory is provided. , The analog quantity can be displayed as a map like the Vth of the transistor, and the characteristics can be evaluated by the physical arrangement of each cell.

Further, an external controller such as a workstation connected to the IC tester has a function of operating between one or a plurality of bitmap data, so that a change in transistor characteristics of each cell before and after a temperature stress, a change in time, and the like. There is an effect that the change can be displayed in a bitmap or analyzed for frequency distribution or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an IC tester according to the present invention.

FIG. 2 is a circuit diagram showing an example of a 4-bit capacity in a flash memory which is a nonvolatile memory element.

FIG. 3 is an example of a bit map of electrical characteristics of a transistor of a memory cell.

FIG. 4 is an example in which an external controller such as a workstation according to the present invention performs arithmetic processing between a plurality of bitmap data and generates new bitmap data.

FIG. 5 is a configuration block diagram of a conventional IC tester.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Tester 2 Control part 3 External controller 4 Pattern generation part 5 Waveform formation part 6 Judgment part 7 Conversion part 8 Switching part 9,10 Fail memory part 11 Bit map memory part 12 IC map to be measured b-f Test conditions 1-5 Bit g of map g to i Exclusive OR between maps b and c, maps c and d, maps d and e, maps e and f Map k to map data of each cell pass / fail boundary value under each test condition Map o, p Bitmap data map g Map data after arithmetic processing between maps o and p

Claims (6)

(57) [Claims] 1. A test apparatus for a semiconductor device having a plurality of cells, comprising: means for storing bitmap data according to a plurality of test conditions; and storing bitmap data under a previous test condition and bitmap data under a current test condition. Means for comparing, calculating a cell having different data as a result of the comparison, and storing a data code corresponding to the current test condition in a memory area corresponding to the cell, whereby a boundary of a change for each test condition of each cell is obtained. And a means for mapping a condition. 2. A test apparatus for a semiconductor device having a plurality of cells, comprising: a plurality of fail memory units for storing results for a plurality of different test conditions; and a bit map data of the fail memory unit. (DUT) means for calculating the transistor characteristics of each cell in each cell, a bitmap memory unit for storing the calculation result, storing the pass / fail result data in the fail memory unit, and reading the pass / fail result data A switching unit for performing switching for transmission to a bit map memory unit. 3. The bitmap data in the plurality of fail memory units is compared with the bitmap data under the immediately preceding test condition and the bitmap data under the current test condition to calculate cells having different data, and 3. A control section for storing a data code corresponding to a current test condition in a memory area corresponding to the different cell in the memory section, thereby displaying a boundary condition of pass / fail of each cell on a map. A test apparatus for a semiconductor device according to claim 1. 4. An operation between a plurality of bitmap data,
4. The test apparatus for a semiconductor device according to claim 3, further comprising an external controller for displaying the calculation result. 5. The semiconductor device test apparatus according to claim 1, wherein said cells are memory cells. 6. A method for testing a semiconductor device having a plurality of cells, comprising comparing bitmap data under the immediately preceding test condition with bitmap data under the current test condition, calculating cells having different data, and corresponding to the cells. Storing a data code corresponding to a current test condition in the memory area, thereby mapping a boundary condition of a change for each test condition of each cell.