JP2966184B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit used only on the manufacturer side and a method of manufacturing the same.

[0002]

FIG. 3 shows a conventional EPROM redundant memory cell replacement circuit. The defective address circuit 10 stores and outputs a defective memory cell row of a memory cell array having redundant memory cells.
After a redundant address such as a defective memory cell row address is written in the nMOS transistor T2 with a floating gate on the manufacturer side before shipment on the manufacturer side, the output is theoretically constant. FIG. 3 shows a 1-bit defective address circuit 10 for simplification. Control circuit 18
Is only used on the manufacturer side for this writing.

On the other hand, a semiconductor device is required to operate at high speed regardless of a memory circuit or a logic circuit, and the current driving capability of an output circuit has been increased in order to drive a load at high speed. As a result, the load capacity is charged and discharged at high speed, and the power supply voltage greatly fluctuates due to the inductance component of the power supply line. Further, peripheral devices of the semiconductor device are required to operate at a high speed, and the environment is liable to generate power supply noise.

[0004]

SUMMARY OF THE INVENTION
For example, when writing data to the memory cell array on the user side, noise causes the source voltage of the pMOS transistor T1 to rise or the voltage of the select gate SG to fall, turning on the pMOS transistor T1 and causing nMO
Drain of S transistor T2 and control gate C
When a high voltage is applied between G, the storage content of the nMOS transistor T2 changes, and the EPROM becomes defective and may malfunction. Such a problem also occurs in semiconductor devices other than the circuit shown in FIG.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can prevent a circuit used only on the manufacturer side from malfunctioning by affecting a circuit used on the user side. Is to do.

[0006]

FIG. 1 shows the principle configuration of a semiconductor device according to the present invention.

This semiconductor device comprises a semiconductor integrated circuit 1 which operates in accordance with data at a first input terminal, and nonvolatile storage means to which data is written via a second input terminal. A controlled circuit 2 for supplying storage contents to the first input terminal; a control circuit 3 for supplying write data from the output terminal to the second input terminal to write the data in the nonvolatile storage means; Pad 4 connected to 2 input terminals
The connection between the output terminal and the second input terminal is disconnected in a state where data is written to the nonvolatile storage means, and a constant voltage line is connected to the pad.

According to this semiconductor device, the control circuit 3 used only on the manufacturer side affects the controlled circuit 2 when used on the user side and malfunctions due to noise, which affects the semiconductor integrated circuit 1. The malfunction of the semiconductor integrated circuit 1 can be prevented.

In the first aspect of the first invention, the non-volatile storage means includes, as shown in FIG.
And the control circuit 3 changes the voltage at the output terminal to change the drain voltage of the non-volatile memory cell T2, thereby performing the writing.

In the second aspect of the first invention, the controlled circuit 2
Is, for example, as shown in FIG.
, A gate connected to the second input terminal, a high voltage V _PP for data writing applied to the source, and a drain connected to the non-volatile memory cell T2. A p-channel MIS transistor T1 connected to the drain.

In the third aspect of the first invention, the semiconductor integrated circuit 1 is a semiconductor memory, and a redundant address of the semiconductor memory is written in the nonvolatile storage means of the controlled circuit 2.

In the method for manufacturing a semiconductor device according to the second invention,
A step of writing the data to the controlled circuit 2 by the control circuit 3 and a step of disconnecting the connection between the output terminal and the second input terminal and connecting a constant voltage line to the pad. Have.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a redundant memory cell replacement circuit of an EPROM to which the present invention is applied. The same components as those in FIG. 3 are denoted by the same reference numerals.

The defective address circuit 10 includes a write circuit 12
And a defective address storage circuit 14. Write circuit 1
2, the source of the pMOS transistor T1 is connected to the write voltage supply line V _PP . Bad address storage circuit 1
4, the source of the nMOS transistor T2 is connected to the ground line, and the drain of the nMOS transistor T2 and n
The drain of the MOS transistor T3 is connected, and nM
The gate of the OS transistor T3 is connected to the power supply line V _CC . Write circuit 12 and defective address storage circuit 1
4, the drain of the pMOS transistor T1 is n
It is connected to the drain of the MOS transistor T2.

The pMOS transistor T1 is for switching the nMOS transistor T2. nMO
The S-transistor T2 is a memory cell having a floating gate FG between the control gate CG and the channel. The S-transistor T2 applies a high voltage between the drain and the control gate CG to charge the floating gate FG, thereby causing a threshold. The stored voltage is determined by changing the value voltage. The nMOS transistor T2 is a memory cell of an UPROM (Unerasable Programmable ROM) which is itself the same as the memory cell of the EPROM, but does not have an ultraviolet transmission window corresponding to this part of the package. nMOS transistor T3 with its source voltage below the gate voltage V _CC, is intended to prevent the high voltage is applied to the circuit of the memory cell row switching circuit 16 connected to the source of the nMOS transistor T3 .

The memory cell row switching circuit 16 switches the memory cell row selected by the address decoder according to the storage contents of the nMOS transistor T2, thereby replacing the row containing the defective memory cell with the redundant memory cell row. Although a plurality of defective address circuits 10 are connected to the memory cell row switching circuit 16, FIG. 2 shows one bit of defective address circuits 10 for simplification.

The output terminal of the select gate control circuit 18 is connected to the select gate SG of the pMOS transistor T1 via the fuse 22 and the pad 24, and the output terminal of the control gate control circuit 20 is connected to the control gate CG of the nMOS transistor T2. Connected, select gate control circuit 18 and control gate control circuit 2
The address input terminal A1 is connected to the input terminal of 0, and the data input terminal D1 is connected to the other input terminal of the select gate control circuit 18.

The voltage V _PP is normally equal to the voltage V _CC . However, when writing data to the nMOS transistor T2 or the memory cell array, a high voltage, for example, 12 V
To be.

The feature of the redundant memory cell replacement circuit having the above configuration is that the output terminal of the select gate control circuit 18 and p
The difference lies in that the fuse 22 and the pad 24 are connected in series between the select gate SG of the MOS transistor T1.

Next, the operation of this embodiment will be described.

In a normal use state, that is, when the address input terminal A1 is at a voltage other than the high voltage, the select gate control circuit 18 outputs the voltage V _CC to output the pMOS transistor T1.
Is turned off, and the control gate control circuit 20 outputs the voltage V _CC to bring the pMOS transistor T1 into the read state.

The nMOS transistor T2 on the manufacturer side
When writing data to the address input terminals A1 and A1,
Voltage V_PPTo a high voltage. This allows control game
The port control circuit 20 outputs 0V. In this state, write
0V or V at the data input terminal D1_CCV
Apply. The select gate control circuit 18, for example,
When the input terminal D1 is at 0 V, the select gate SG
Is the high voltage V_PPV to turn off pMOS transistor T1
State, and the pMOS transistor T1 _CCWhen
The select gate SG is set to 0V and the pMOS transistor
By turning on the transistor T1, the nMOS transistor is turned on.
High voltage between transistor T2 and control gate CG
To make the floating gate FG negatively charged.
You.

When the address input terminal A1 is set to a high voltage and nM
After writing data to the OS transistor T2, the fuse 22 is blown by, for example, a laser beam, and the pad 24 is connected to the write voltage supply line V _PP by a wire bonder. Pad 24 is for this connection.

Accordingly, when data is written to the memory cell array on the user side, even if the output voltage or the write voltage V _PP of the select gate control circuit 18 fluctuates due to noise, the voltage of the select gate SG is equal to the voltage V _PP . As a result, the pMOS transistor T1 is always turned off, so that the stored contents of the nMOS transistor T2 are not suddenly rewritten and do not malfunction.

[0026]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the control circuit used only on the maker side affects the controlled circuit due to noise when used on the user side. An erroneous operation, which exerts an excellent effect that the semiconductor integrated circuit can be prevented from being erroneously operated by affecting the semiconductor integrated circuit, greatly contributes to improvement in reliability of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a principle configuration of a semiconductor device according to the present invention.

FIG. 2 is a redundant memory cell replacement circuit of an EPROM to which the present invention is applied.

FIG. 3 is a circuit diagram of a redundant memory cell replacement circuit of a conventional EPROM.

[Explanation of symbols]

 Reference Signs List 10 defective address circuit 12 write circuit 14 defective address storage circuit 16 memory cell row switching circuit 18 select gate control circuit 20 control gate control circuit A1 address input terminal D1 data input terminal FG floating gate

Claims (5)

(57) [Claims] 1. A semiconductor integrated circuit (1) that operates in accordance with data at a first input terminal, and a non-volatile storage device to which data is written via a second input terminal, wherein the storage of the non-volatile storage device is performed. A controlled circuit (2) for supplying contents to the first input terminal, and a control circuit (3) for supplying write data from the output terminal to the second input terminal and writing the data in the nonvolatile storage means. And a pad (4) connected to the second input terminal, wherein the connection between the output terminal and the second input terminal is cut off in a state where data is written to the nonvolatile storage means. And a constant voltage line is connected to the pad. 2. The non-volatile storage means includes a non-volatile memory cell (T2) having a gate connected to the output terminal of the control circuit (3), and the control circuit stores a voltage at the output terminal. 2. The semiconductor device according to claim 1, wherein the writing is performed by changing the drain voltage of the nonvolatile memory cell. 3. The controlled circuit (2) includes an n-channel M having a floating gate (FG).
A gate connected to the second input terminal, a high voltage for data writing (V _PP ) applied to a source, and a drain connected to the non-volatile memory cell (T2) formed of an IS transistor; The semiconductor device according to claim 2, further comprising: a p-channel MIS transistor (T1) connected to the drain. 4. The semiconductor integrated circuit (1) is a semiconductor memory, and a redundant address of the semiconductor memory is written in the nonvolatile storage means of the controlled circuit (2). Item 4. The semiconductor device according to any one of Items 1 to 3. 5. A step of writing the data to the controlled circuit (2) by the control circuit (3), and then disconnecting a connection between the output terminal and the second input terminal. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: connecting a constant voltage line to the pad.