JP2966071B2 - Unit delay multiplexing logic element and logic simulator using the logic element - Google Patents

Description

The present invention relates to a logic element for performing a logic simulation of a digital circuit and a logic simulator using the logic element, and particularly relates to an area occupied by a wiring network. A logic simulator with greatly reduced unit delay multiplexing logic elements.

(Prior Art) Conventionally, in order to shorten the development period of a large-scale logic device, logic is debugged using a logic simulator before actually manufacturing the device.

The logic simulator includes a plurality of logic modules LM ′
Are connected to each other by a wiring network, and the logic module LM 'further includes a large number of three-input one-output or two-input one-output logic elements LE' therein, and the logic element LE '
Are configured by arranging a wiring network that interconnects them.

As the logic element LE ′, a memory cell array system in which a unit memory cell group that functions as a logic gate is regularly repeated and arranged in an array structure, or a programmable logic including an AND array and an OR array of diodes -In addition to general-purpose logic circuits consisting of an array (PLA) system, a universal logic gate (ULG) system is generally used.

FIG. 15 shows a logic module LM ′ configured by connecting a plurality of logic elements LE ′ by a wiring network. FIG. 16 shows a logic simulator constituted by connecting a plurality of logic modules LM ′ in the same manner using an arrangement network.

In Fig. 15, the logic module is composed of 16 logic elements LE '
In FIG. 16, an example in which a logic simulator is constituted by 16 logic modules LM 'is shown for convenience, but in actuality, a logic module LM' has about several thousand logic elements LE '.
, And the logic simulator implements about several hundred logic modules LM ′. That is, the logic simulator is generally a logic circuit having a scale of one million gates (one gate corresponds to one logic element LE ').

Hereinafter, 4096 (64 × 64) logic elements LE ′ are mounted on the logic module LM ′, and the logic module LM ′
A logic simulator in which 256 (16 × 16) are mounted will be described with reference to FIG.

FIG. 17 shows details of the connection of the logic element LE 'by the wiring network. The logic element LE' has two inputs and one output only for the sake of simplifying the explanation.

In the figure, A and B are input terminals of the logic element LE ', and H is an output terminal. Also, the logical element LE of 64 rows and 64 columns
In order to connect ′, 16 of v1 to v16 in the vertical direction in the figure
Similarly, 16 wirings h1 to h16 are provided in the horizontal direction. Here, the above number of wires are semi-custom
It is well known to those skilled in the art from experience of designing a gate array used as an LSI.

In the case of a two-input, one-output logical element LE ', the seventeenth
As shown in the figure, 48 switches (3 terminals × 16 wires) are required and provided for connection between the input / output terminals of the logic element LE ′ and the wires. Similarly, there are 64 switches (4
256 switches (16 wires × 16 wires) are required and provided for branching the wires. That is, a total of 368 for one logical element LE '
Switches are provided as necessary.

Here, the switches a, b, and c correspond to FIGS.
As shown in FIG. 18 (c), opening and closing are controlled by a 1-bit memory as is well known.

So, in the logic module LM´, 4096 logic elements
Since LE 'exists, about 1.5 million switches (368 × 4096 logic elements) with memory are required.

(Problems to be Solved by the Invention) However, in the above-described conventional logic simulator, since the logic element LE 'itself can be constituted by a circuit equivalent to about 20 memories, the logic element LE' is wasted on the group of logic elements LE '. The area within one logical module LM 'is 80,000 (20 × 4096)
(The number of logical elements). That is, when the logic module LM 'is configured on the LSI, a large part of the area of the LSI is occupied by the switch with the memory, and there is a problem that the logic simulator becomes large.

Further, as shown in FIG. 19, a logic simulator composed of a large number of logic modules LM ′ and a wiring network connecting the logic modules LM ′, as shown in FIG.
Each side of LM´ has 64 terminals (256 in total),
In addition, for connection between the logic modules LM ′, as is well known, 128 wirings v1 are provided in the vertical and horizontal directions in the figure, respectively.
To v128 and h1 to h128.

In this case, 32K switches (the number of 256 terminals × 12) are indicated by reference symbol d for connection between one logic module LM ′ and the wiring.
8 switches required), 512 switches (4 directions x 128 wires) indicated by reference symbol e for disconnection or connection of wiring,
16K switches (1
(28 wirings x 128 wirings). That is, a total of about 48K switches are required for one logic module LM '. A logic simulator using 256 logic modules LM ′ requires about 12M switches (48K × 256 logic modules).

Therefore, almost all the area occupied by the logic simulator is occupied by the wiring and the switch with the memory which are not directly involved in the logic calculation, and there is a problem that the size becomes large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances and has an object to provide a logic simulator capable of greatly reducing an area occupied by wiring and a switch with a memory.

This makes it possible to implement a larger logic simulator with 1M gates or more.

[Means for Solving the Problems] To solve the above problems, the unit delay multiplexing logic element of the present invention instructs to sample only a specific pulse signal from one multiplexed input signal. A sampling signal generating means for generating a signal to be generated, a sampling means for sampling the specific pulse signal specified by the sampling signal generating means within one simulation cycle, and holding the pulse signal sampled by the sampling means. At the start of a new simulation cycle, holding means for converting and outputting a restored signal having a constant level during the cycle are provided for each multiplexed input signal, and output from each sampling and holding means. A predetermined logical operation is performed on the restored signal A general-purpose logic circuit that outputs a force signal, characterized in that said logic output signal and a pulsing means for outputting a sampled multiplexable operations already pulse signal at a predetermined timing.

Further, in the logic simulator of the present invention, the unit delay multiplexing logic elements are arranged in a large number in two dimensions of rows and columns, and the calculated pulse signals output from the unit delay multiplexing logic elements of one row or column are different from each other. Are input to the unit delay multiplexing logic element of the row or column, and the multiplexed input signals are sequentially output in each unit delay multiplexing logic element connected in series for each row or column and for each simulation cycle. It is characterized by being subjected to logical operation processing independently.

More preferably, a wiring network for interconnecting the respective unit delay multiplexing logic elements is provided, wherein the wiring network includes a plurality of switches for connecting and disconnecting the respective unit delay multiplexing logic elements, and connecting the switches. The disconnection operation may be performed by time division control using a register programmed in advance.

(Operation) In the unit delay multiplexing logic element of the present invention, the multiplexed input signal has a plurality of pulse signals that are time-divided during one simulation cycle. The sampling signal generating means generates a signal instructing to sample any one of the pulse signals according to a program in advance, and in accordance with the instruction signal, the sampling means samples only a specific pulse signal from the input signal. The pulse signal sampled in this manner is sent to and held by the holding means, and then, at the start of a new simulation cycle, converted into a restored signal having a constant level during the new cycle, and sent to a general-purpose logic circuit.

The restoration signal is subjected to a predetermined logic operation by a general-purpose logic circuit, and then sent to a pulse generator as a logic output signal. In the pulsing means, the logical output signal is synchronized with a predetermined timing pulse and converted into a pulse signal again. That is, the logical output signal is converted into a multiplexable signal.

Accordingly, since each unit delay multiplexing logic element samples and processes only a specific pulse signal to be logically operated from the multiplexed input signal, a large number of signals can be put on one signal wiring.

Further, in the logic simulator of the present invention, the calculated pulse signal is output from the unit delay multiplexing logic element of one row or column at a timing specific to the row or column. The unit delay multiplexing logic element of another row or column to which the calculated pulse signal is input samples the calculated pulse signal in synchronization with the timing of the calculated pulse signal according to a program in advance. That is, in the group of unit delay multiplexing logic elements constituting a predetermined logic circuit, an input signal is subjected to logical operation processing sequentially and independently for each unit delay multiplexing logic element of each stage and for each simulation cycle.

Therefore, in the logic simulator of the present invention, a desired logic circuit can be constructed by combining a plurality of unit delay multiplexing logic elements according to a predetermined program.

Also, since a large number of signals can be carried on one signal wiring of a wiring network interconnecting the respective unit delay multiplexing logic elements, the number of wirings in each direction decreases in inverse proportion to the number of multiplexing. As a result, the number of switches with memory is greatly reduced.

For example, when the degree of multiplexing is 4, the number of switches with memories for branching wirings arranged two-dimensionally is reduced to 1/16 (1/4 × 1/4) as compared with the conventional case.

As a result, the wiring area in the logic simulator is significantly reduced, so that the chip of the logic module LM 'and the chip of the wiring network can be reduced, and a compact logic simulator can be manufactured.
This leads to the realization of a larger logic simulation system.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a unit delay multiplexing logic element according to an embodiment of the present invention.

The unit delay multiplexing logic element LE is, for example, when handling a logic element having two inputs and one output, from a multiplexed signal A or B having a plurality of time-divided pulse signals in the same simulation cycle, and This is a logic element that samples only the pulse signal and then performs a predetermined logical operation process.

In other words, as shown in FIG. 1, a specific pulse signal is sampled from each of the multiplexed signals A and B, and restored signals a and b having a certain level during the new simulation cycle at the start of the new simulation cycle. A general purpose logic circuit 2 for performing a predetermined logic operation on the restored signals a and b, and a logic output signal h logically operated by the general purpose logic circuit 2 A pulsing circuit 3 which samples at a timing, converts the multiplexed pulse signal H into an output signal, and outputs the multiplexed pulse signal H.

As shown in the block diagram of FIG. 2A, the sampling and holding circuit 1 includes a timing pulse Ti (this embodiment) synchronized with each of a plurality of multiplexed input signals, for example, a plurality of pulse signals of the signal A. Then i = 1 to 4)
A sampling signal generator 4 for outputting a predetermined timing pulse Ti from the sampling circuit 5, a sampling circuit 5 for sampling only a specific pulse signal synchronized with the predetermined timing pulse Ti, and the pulse sampled by the sampling circuit 5. And a hold circuit 6 for holding a signal, converting the signal to a restored signal a having a constant level during a new simulation cycle at the start of the cycle, and outputting the restored signal a.

The sampling signal generating unit 4 includes a sampling instruction register 7 for instructing a timing for sampling only the specific pulse signal, and a sampling instruction register 7.
And a selection circuit 8 that outputs a timing pulse Ti synchronized with the specific pulse signal in accordance with the instruction of (1). Further, the sampling signal generating section 4 will be described in detail with reference to FIG. 2 (b). The sampling instruction register 7 is a 2-bit register. In this case, it is programmed in advance to output a timing pulse of Ti = T1 01 Ti = T2 10 Ti = T3 11 Ti = T4.

Here, as shown in FIG. 3, the timing pulse Ti is divided into four types of timing pulses T1 and T4 obtained by dividing the basic period T of the simulation into four non-overlapping portions.
It is a periodic pulse signal train composed of 2, T3, and T4.

Accordingly, only the pulse signal synchronized with the timing pulse Ti sent from the sampling signal generator 4 is sampled from the multiplexed signal, for example, the signal A input to the sampling circuit 5 of the sampling and holding circuit 1. Next, the data is held by the hold circuit 6 until the start of a new simulation cycle, and is restored at the start of the simulation cycle and output to the general-purpose logic circuit 2. This restored signal a has a constant level during the simulation cycle.

In the above description, only the input signal A is targeted, but the sampling and holding circuit 1 is provided with a similar sampling signal generator 4 'for processing the input signal B, a sampling circuit 5', and a hold circuit 6 '. Not shown).

The general-purpose logic circuit 2 is composed of logic elements of the ULG system used in, for example, a conventional logic simulator as shown in FIG. 4, and the circuit 2 uses the function f to calculate the logic of h = f (a, b). An operation is performed.

That is, in FIG. 4, the restoration signals a and b are subjected to predetermined switching in the input switching circuit M1 based on a command from the control circuit 21, and are then calculated in the ULG 22 by one of the six logic functions. Further, the restoration signals a and b undergo predetermined switching again in the input switching circuit M2 based on a command from the control circuit 21, and the ULG 23 selects the presence or absence of inversion and outputs it as a logical output signal h.

Therefore, the general-purpose logic circuit 2 can perform all kinds of basic logical operations, and has the same configuration and functions as the conventional general-purpose logic circuit.

As shown in FIG. 5 (a), the pulsing circuit 3 includes a timing pulse Ti determined by the arrangement of a unit delay multiplexing logic element at one input terminal of an AND circuit, that is, a sampling pulse input terminal, for example, a unit. When the delay multiplexing logic elements LE are arranged in the second row, the timing pulse T2 is applied. Further, a logical output signal h obtained by performing a logical operation in the general-purpose logic circuit 2 is applied to the other input terminal.

Then, as shown in the signal waveform diagram of FIG. 5 (b), the logical output signal h is logically ANDed with the timing pulse T2 in the pulsing circuit 3 which is an AND circuit, and
Is output as a pulse signal H that can be multiplexed in synchronism with.

Therefore, the above-mentioned unit delay multiplexing logic element LE can sample only one pulse signal synchronized with the timing set in advance from the multiplexed input signals A and B on a program.

Further, the sampled pulse signal is subjected to a predetermined logical operation to be logically converted into a logical output signal h, and then the logical output signal h is converted into a multiplexable pulse signal and output. The signal can be subjected to another logical operation in another unit delay multiplexing logic element LE.

Further, in the above-described unit delay multiplexing logic element LE, when the multiplexed input signals A and B are restored by the hold circuit 6 shown in FIG. 2 (a), as shown in FIG. 7 (a). In addition, since a unit delay is generated by being held until a new simulation cycle, it is a great feature that it is not necessary to provide a unit delay circuit required for delaying the logic output h by a unit in the conventional logic element.

Next, using the unit delay multiplexing logic element LE having the above-described configuration and function, a unit delay multiplexing logic element LE group arranged in a two-dimensional matrix as in the related art, and the unit delay multiplexing logic element A multiplexing logic module composed of a wiring network interconnecting each of the element LEs
The LM is shown in FIG.

In the figure, a predetermined timing pulse is pre-programmed and assigned to the unit delay multiplexing logic element LE for each row of the array. That is, in this embodiment, for example, for the first row, the timing pulse T1 for the second row, the timing pulse T2 for the third row, the timing pulse T3 for the fourth row, the timing pulse T4 or less, and again the 4n + ith row (N = 1, 2,...), The timing pulse Ti is repeatedly assigned every four rows.

Further, FIG. 7A shows a specific example in which the unit delay multiplexing logic elements LE are connected via a wiring network in the multiplexing logic module LM to form a predetermined combination of logic circuits.

That is, in the unit delay multiplexing logic element LEu in the first row, the multiplexed input signal is
The logical operation of h1 = f1 (a1, b1) is performed on A1 and B1, and the signal H1 is output within the second simulation cycle. Here, a1 and b1 are multiplexed input signals A
1, a restored signal for B1, and H1 is a signal obtained by converting the logical output signal h1 into a multiplexable signal.

Similarly, in the unit delay multiplexing logic element LEv in the third row, a logic operation of h3 = f3 (a3, b3) is performed on the multiplexed input signals A3 and B3 in the same first simulation cycle, and H3 is also output within the second simulation cycle.

Next, the output signal H1 and the output signal H3 are sent to the input terminals of the unit delay multiplexing logic element LEx in the second row via the wiring network. Then, in the unit delay multiplexing logic element LEx in the second row, a logical operation of h2 = f2 (a2, b2) is performed on the input signals H1 and H3 that can be multiplexed in the second simulation cycle, and the signal H2 is output within the third simulation cycle. Here, a2 and b2 are restoration signals for the multiplexable input signals H1 and H3.

Further, the operation of the logic circuit shown in FIG. 7A will be specifically described below with reference to FIG. 7B.

If the result of the predetermined logical operation f1 in the unit delay multiplexing logic element LEu in the first row is that h1 is always at the H level after the second simulation cycle, the multiplexing synchronized with the timing pulse T1 in the pulsing circuit 3 The enable signal H1 is similarly output to the unit delay multiplexing logic element LEx in the second row after the second simulation cycle. In the unit delay multiplexing logic element LEx, the multiplexable signal H1 is converted into a restored signal a2 in each simulation cycle in the hold circuit 6, and goes to the H level after the third simulation cycle.

Further, as a result of the predetermined logical operation f3 in the unit delay multiplexing logic element LEv on the third row, h3 is at H level until the second simulation cycle (L is low after the third simulation cycle).
If the signal is a level, the multiplexing enable signal H3 synchronized with the timing pulse T3 is output to the unit delay multiplexing logic element LEx in the second row until the second simulation cycle. In other words, the multiplexable signal H3 is at the L level after the third simulation cycle. Next, in the unit delay multiplexing logic element LEx, the multiplexable signal H3 is converted into a restoration signal b2 in each simulation cycle up to the third simulation cycle in the hold circuit 6 and sent to the general-purpose logic circuit 2.

Therefore, in the general-purpose logic circuit 2 of the unit delay multiplexing logic element LEx in the second row, for example, an AND operation is performed on the restored signals a2 and b2, and the restored signals a2 and b2 are output only in the third simulation cycle. The signal is converted into a logic output signal h2 which becomes H level, and the multiplexing enable signal H2 is output in the pulsing circuit 3 in synchronization with the timing pulse T2.

Therefore, by combining a plurality of unit delay multiplexing logic elements LE, an arbitrary combined logic circuit can be constructed.

Here, when such a logic circuit is constructed on a multiplexing logic module, since it is determined in advance which row the logic circuit is to be assigned to the unit delay multiplexing logic element LE of which unit, each unit delay multiplexing is performed. It is possible to know in advance which row the unit delay multiplexing logic element LE from which the signal input to the multiplexing logic element LE comes. That is, for example, it is possible to know in advance which of the timing signals Ti the input signals H1 and H3 are to be cycled. Therefore, it is possible to set in advance at the time of programming so as to instruct the sampling instruction register of the unit delay multiplexing logic element LEx with the timing pulse Ti synchronized with the input signals H1 and H3.

Since the signals output from the unit delay multiplexing logic element LE on the i-th row are synchronized with the timing pulse Ti, for example, each output signal from the first row to the fourth row is connected to the same wiring. , Each output signal becomes one multiplexed signal, and the output signals do not overlap with each other. However, for example, when the output signal of the first row and the output signal of the fifth row are placed on the same wiring, overlapping occurs. The countermeasure against this problem is dealt with by a switching operation described later.

Next, a wiring network in the multiplexing logic module LM will be described with reference to FIGS.

In order to interconnect the logic elements in the multiplexed logic module LM, about 16 wirings are required in the vertical and horizontal directions, respectively, as described in the conventional example. On the other hand, in the present embodiment, since the signals propagating in the wiring are multiplexed into four multiplexes, it is apparent that only four (16/44 multiplexes) are required.

As shown in FIG. 8 in an enlarged view of FIG. 6, the wiring network according to the present embodiment includes a connection for connecting the input / output terminals A and B of the unit delay multiplexing logic element LE to the wiring as in the conventional example. The switch includes a switch s1, a connection switch s2 for disconnecting or connecting wiring, and a connection switch s3 for branching wiring.

The connection switch s1 is composed of a transistor controlled by a 1-bit memory M as shown in FIG. 9 (a), and when M = 1, the input / output terminals A and B of the unit delay multiplexing logic element LE are Connected to wiring.

The connection switch s2 is composed of a transistor controlled by the timing instruction circuit 9, as shown in FIG. 9 (b). That is, as shown in detail in the timing instruction circuit 9 in FIG. 10, in the timing register 10, when p1 = 1, when the timing pulse T1 p2 = 1, when the timing pulse T2 p3 = 1, and when the timing pulse T3 p4 In the case of = 1, the timing pulse T4 passes through each of the AND circuits A1 to A4, and is then applied at different timings to the gates of the transistors via the OR circuit A5.

That is, by programming the values of p1 to p4 in advance, the timing instruction circuit 9
Whether to connect or disconnect the wiring can be independently specified for each type of signal. For example, when the values of p1 to p4 are all set to 1 in a predetermined simulation cycle, all four types of four-multiplexed signals are connected.

The above setting is made in advance when the wiring network is programmed, similarly to the programming of the sampling signal generator 4 of the unit delay multiplexing logic element shown in FIG. 2 (b).

As shown in FIG. 9 (c), the connection switch s3 is composed of a transistor controlled by a 1-bit memory M, as in the case of the connection switch s1, and branches when M = 1. That is, the signal travels straight and propagates through the intersecting wiring. When M = 0, the signal only goes straight.

Therefore, when input signals are multiplexed, the same function as in the related art can be realized using fewer wirings.

That is, as in the conventional case, 40
When 96 (64 × 64) logic elements are mounted, 49K connection switches s1 (3 terminals × 4 wirings × 4096 logical elements) are required. 66K connection switches (4 directions x
(4 wirings × 4096 logic elements)). Connection switch
s3 requires 66K (4 wirings × 4 wirings × 4096 logical elements). Therefore, the total is only 180,000, which is a significant decrease from the 1.5 million required in the conventional example.

Also, for example, signals output from the unit delay multiplexing logic element groups from the first row to the fourth row are output from the unit delay multiplexing logic element groups from the fifth row to the eighth row. If the signal and signal overlap on the same wiring,
What is necessary is just to set in advance so that the wiring is cut using the connection switch s2 located between the fourth row and the fifth row. Thus, the above-mentioned problem is solved.

The group of unit delay multiplexing logic elements LE shown in FIG. 8 has all input / output terminals only on one side (right end in the figure), and the wiring network is arranged to be connected to the input / output terminals. However, it is not necessary to limit to such an arrangement relationship. As shown in FIG. 11, input / output terminals are distributed on each side of each unit delay multiplexing logic element LE, and the distributed input / output terminals A wiring network may be constructed so as to be connected.

Next, a description will be given of a multiplexing logic module LM in which a large number of unit delay multiplexing logic elements LE are arranged in a matrix in two dimensions of rows and columns, and the respective unit delay multiplexing logic elements LE are interconnected by a wiring network. .

As described in the conventional example, the conventional logic module generally has 64 terminals (256 in total) on each side of the logic module for exchanging information with the outside. However, when signals are multiplexed using the unit delay multiplexing logic element LE of this embodiment, the number of terminals on each side of the multiplexing logic module LM is reduced to 16 (64 in total). In order to operate the multiplexing logic module LM, a terminal for supplying a clock signal, a terminal for supplying program data, and a power supply terminal are required, but these terminals occupy a small area.

FIG. 12 shows the relationship between the signal terminals of the multiplexed logic module LM and the internal signal wiring connected to the terminals when 16 signal terminals are provided for each side of the multiplexed logic module LM. In FIG. 12, a part of the signal terminals U1 to U16 is provided on the upper side of the multiplexed logic module LM, and the signal terminal R1 is provided on the right side.
R16 are partially enlarged.

As shown, the terminals U1 to U16 and R1 to R16 of the multiplexed logic module LM are selectively connected to signal wiring in the multiplexed logic module LM by the connection switch s4. The connection switch s4 is composed of one connection switch transistor as shown in FIG. 13 (a), and the switch transistor receives a signal from the terminal selection signal circuit 11 at its gate. That is, the terminal selection signal circuit 11 is configured as shown in FIG.
As shown in FIG. 10, the timing instruction circuit 9 shown in FIG.
Similarly, the timing pulse Ti determined by the timing register 12 is supplied to the switch transistor. Therefore, the switch transistor can independently branch the wiring for the four types of signals on the wiring.

When a signal in the multiplexing logic module LM is given or received outside the multiplexing logic module LM, the signal usually passes through a buffer circuit, but this buffer circuit is omitted in FIG.

Therefore, in the multiplexing logic module LM of the present embodiment, by setting in advance the opening and closing of the connection switch s4 in the timing register 12 of the terminal selection signal circuit 11,
The multiplexed signal in the multiplexing logic module LM can be freely transmitted to the outside, and conversely, the multiplexed signal can be input.

Next, a description will be given of a logic simulator in which a large number of the multiplexed logic modules LM are arranged two-dimensionally in rows and columns in a matrix and the multiplexed logic modules LM are interconnected by a wiring network with reference to FIG. I do.

As shown in the figure, since there are 16 terminals on each side of each multiplexing logic module LM as described above, 16
Two leader lines are required. Further, in the present embodiment, sixteen wirings are provided as intersecting these lead lines. The 19th
In the conventional example shown in the figure, 128 intersecting wires are provided for the logic module, but in the logic simulator of this embodiment, the lead lines of the two multiplexed logic modules LM facing each other are 16 lines. 4
In this multiplexed embodiment, 16 (128 lines / 4 multiplex / 2) cross wirings are sufficient.

In the logic simulator having the above configuration, 1K connection switches s5 are provided for each multiplexed logic module LM to connect the input / output terminals of the multiplexed logic module LM and the wiring (16K).
Number of terminals x 16 wires x 4 sides) 256 connection switches s6 for cutting or connecting wires (4 directions x 16 wires x 4 sides),
1K connection switches s7 (16 wires × 16
(Number of wirings × 4 sides). So, in a logic simulator consisting of 256 multiplexed logic modules LM,
Only a total of 0.6M connection switches are required. This is a significant reduction from the 12M required in the conventional example.

The connection switches s5, s6, and s7 operate by the same mechanism as the connection switches s1, s2, and s3 described with reference to FIGS. 9 (a) to 9 (c).

Therefore, in the present embodiment, a predetermined delay pulse signal is sampled from the four-multiplexed signal, the arithmetic processing is performed in the same manner as in the related art, and a unit delay multiplexing logic element LE that can be converted into a multiplexable signal and output is used. As a result, a desired logic circuit can be assembled in the same manner as before, and the number of wires and connection switches of the two-dimensional wiring network can be reduced to about 1/16 (1/4 × 1/4). Can be reduced to That is, the area occupied by the wiring network in the logic simulator can be significantly reduced.

In the above, the signal for performing the logic simulation is 4
Although the case of multiplexing has been described, it is not necessary to limit to multiplexing. For example, according to the conventional technology, up to 16 multiplexing is possible without any particular difficulty, and the number of wirings and the number of connection switches of the wiring network can be further reduced.

Further, in the present embodiment, multiplexing is performed using time-division pulse signals. However, the multiplexing method is not limited to this, and a PAM method or a PWM method in which the amplitude, time width, or the like of a signal is changed may be used. Further, a carrier may be used as a signal, and its amplitude, frequency, phase, or the like may be changed.

The present invention is not limited to the above embodiment, but can be implemented in an appropriate mode by an appropriate design change.

[Effects of the Invention] As described above, according to the present invention, sampling signal generating means for generating a signal instructing to sample only a specific pulse signal from one multiplexed input signal, and the sampling signal generating means Sampling means for sampling the specific pulse signal designated by the means within one simulation cycle, and holding the pulse signal sampled by the sampling means and having a constant level during the new simulation cycle at the start of the new simulation cycle Sampling and holding means having a holding means for converting and outputting the restored signal are provided for each multiplexed input signal, and a predetermined logical operation is performed on the restored signal output from each sampling and holding means to generate a logical output signal. A general-purpose logic circuit for outputting the logic output signal, Pulsed means for sampling at a fixed timing and outputting a multiplexed pulse signal that can be multiplexed,
A predetermined logical operation process is performed only on a desired pulse signal in a multiplexed pulse signal group on the same signal wiring, so that the required number of signal wirings can be greatly reduced.

Also, a large number of the unit delay multiplexing logic elements are arranged two-dimensionally in rows and columns, and the calculated pulse signal output from the unit delay multiplexing logic element in one row or column is changed to a unit delay in another row or column. The input signals input to the multiplexing logic element and multiplexed are sequentially and independently subjected to logical operation processing in each unit delay multiplexing logic element connected in series for each row or column and for each simulation cycle. Therefore, it is possible to construct a desired logic circuit, and it is possible to greatly reduce the area occupied by the wiring of the wiring network for interconnecting the respective unit delay multiplexing logic elements and the connection switch with memory.

[Brief description of the drawings]

FIG. 1 is a block diagram of a unit delay multiplexing logic element according to an embodiment of the present invention, and FIG. 2 (a) is a block diagram of a sampling and holding circuit of the unit delay multiplexing logic element shown in FIG. 2 (b) shows the sampling data shown in FIG. 2 (a).
FIG. 3 is a circuit diagram of a sample signal generator of the hold circuit, FIG. 3 is a waveform diagram of a timing pulse used in the unit delay multiplexing logic element shown in FIG. 1, and FIG. 4 is a unit delay shown in FIG. FIG. 5 (a) is a circuit diagram of a pulse generating circuit of the unit delay multiplexing logic element shown in FIG. 1, and FIG. 5 (b) is a diagram of FIG. FIG. 6A is an operation signal waveform diagram of the pulsating circuit shown in FIG. 6A; FIG. 6 is a schematic diagram of a multiplexing logic module constructed using the unit delay multiplexing logic element shown in FIG. 1; 7A is a schematic configuration diagram of a logic circuit combined in the multiplexed logic module shown in FIG. 6, and FIG. 7B is an operation signal waveform of the logic circuit shown in FIG. 7A. FIG. 8 is a partially enlarged view of the multiplexing logic module shown in FIG. 6, 9 (a) to 9 (c) are explanatory diagrams of the function of the connection switch used in the multiplexing logic module shown in FIG. 8, and FIG. 10 is a timing instruction circuit of the connection switch shown in FIG. FIG. 11 is a partially enlarged view of a multiplexing logic module according to another embodiment similar to the multiplexing logic module shown in FIG. 8, and FIG. 12 is a multiplexing logic module shown in FIG. FIG. 13 (a) is an explanatory diagram of signal terminals and connection switches in a logic module, FIG. 13 (a) is a functional explanatory diagram of the connection switches shown in FIG. 12, and FIG. 13 (b) is shown in FIG. 13 (a). FIG. 14 is a partial enlarged view of a logic simulator constructed using the multiplexed logic module shown in FIG. 11, and FIG. 15 is an overall view of a conventional logic module. FIG. 16 uses the logic module shown in FIG. FIG. 17 is an explanatory diagram of the connection relationship of the logic elements used in the logic module shown in FIG. 15, and FIGS. 18 (a) to 18 (c) are diagrams of the logic simulator constructed. FIG. 17 is an explanatory diagram of the function of the connection switch shown in FIG. 17, and FIG. 19 is an explanatory diagram of the connection relationship between the logic modules shown in FIG. 1 Sampling and holding circuit 2 General-purpose logic circuit 2 3 Pulsing circuit 4 Sampling signal generator 5 Sampling circuit 6 Hold circuit 7 Sampling instruction register 8 Selection circuit LE … Unit delay multiplexing logic element LM …… Multiplexing logic module T1, T2, T3, T4 …… Timing pulse

────────────────────────────────────────────────── ─── Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50 H03K 19/173-19/177 JICST file (JOIS)

Claims (4)

(57) [Claims] 1. A sampling signal generating means for generating a signal for instructing to sample only a specific pulse signal from one multiplexed input signal; Sampling means for sampling within the simulation cycle of the above, and hold means for holding the pulse signal sampled by the sampling means, and converting and outputting a restored signal having a constant level during the new simulation cycle at the start of a new simulation cycle. A general-purpose logic circuit for providing a sampling and holding means for each multiplexed input signal, performing a predetermined logical operation on the restoration signal output from each sampling and holding means, and outputting a logical output signal; The signal is sampled at a predetermined And a pulse generating means for outputting a calculated pulse signal which can be duplicated. 2. The signal generated by the sampling signal generating means is one timing pulse selected from a plurality of timing pulses synchronized with each of the pulse signals of the multiplexed input signal. 3. The logic element according to claim 1, wherein one pulse signal synchronized with the selected timing pulse is sampled. 3. A calculated pulse signal output from the unit delay multiplexing logic element of one row or column, wherein a large number of the unit delay multiplexing logic elements according to claim 1 are arranged two-dimensionally in rows and columns. Is input to the unit delay multiplexing logic element of another row or column, and the multiplexed input signal is output for each row or column in each unit delay multiplexing logic element connected in series and for each simulation cycle. A logic simulator characterized by sequentially and independently performing logical operation processing. 4. A wiring network for interconnecting each unit delay multiplexing logic element, wherein said wiring network includes a plurality of switches for connecting and disconnecting each unit delay multiplexing logic element. 4. The logic simulator according to claim 3, wherein the connection and disconnection operations are performed by time division control using a register programmed in advance.