JP2965004B2 - Cell assembly processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell assembling apparatus for assembling an STM multi-line signal, that is, frame data, into ATM cells.

[0002]

2. Description of the Related Art Conventionally, an S which accommodates a plurality of lines of arbitrary speed has been proposed.
A TM (Synchronous Transfer Mode) multiplexed signal, that is, frame data is transmitted to an ATM (Asynchronous Transfer Mod
e) As a cell assembling processing apparatus for assembling and disassembling into cells, an apparatus configured as shown in FIG. 4 is known.

The cell assembling processing apparatus includes an STM multiplex input line 11 for storing frame data, an input buffer device 12 for storing frame data, and a channel (hereinafter referred to as "CH") for an externally set STM multiplex signal. .)
And ATM cell VPI / VCI (Virtual Path Identif
ier Virtual Channel Identifier) and corresponding information 13
A cell buffer device 14 for storing information, a data processing device 15 executed by a processor or the like, an ATM,
An output buffer device 16 for transmitting cells.

[0004] The input buffer device 12 includes a frame data receiving unit 121.
Is the STM input via the STM multiplex input line 11.
Stores multiplexed signals. In the stored frame data, the CH is identified from the time position of the line time slot (referred to as “TS”).

[0005] The celling buffer device 14 has a VPI / VC
A VPI / VCI data storage unit 141 for storing the frame data for each I is provided.

The data processing device 15 includes a VPI / VCI-specific data storage control unit 151 and a cell storage determination unit 152.
, An AAL layer processing unit 153, and an ATM layer processing unit 154.

[0007] VPI / VCI-specific data storage control section 151
Is conversion information 13 between the input CH and VPI / VCI.
By this, the frame data stored in the frame data receiving unit 121 is sorted by VPI / VCI,
The corresponding VPI / PI in the data storage unit 141 for each PI / VCI
It is stored in the VCI storage area.

[0008] The cellized accumulation judging section 152 has a VPI / VC
For each VPI / VCI storage area of the I-by-I data storage unit 141, it is determined whether 47 bytes or 46 bytes of user information that requires celling are stored.

[0009] The ALL layer processing section 153 includes the AAL
One processing or other type of AAL processing is performed to generate and add an ALL header.

[0010] The ATM layer processing unit 154 has a VPI / V
Generates and adds an ATM header with CI as main information,
Generate a 53-byte ATM cell.

The output buffer device 16 has an ATM cell transmitting section 161.
The ATM cell is output to the multiplex output line.

Next, the operation of the conventional cell assembling apparatus shown in FIG. 4 when receiving the frame data shown in FIG. 5 will be described.

The frame data shown in FIG. 5 includes CHs of different line speeds on TSs (time slots) 1 to A.
(Channels) can be multiplexed. As a specific example, it is assumed that different channels having the following different line speeds are multiplexed. That is, of the multiplexed first channel to M-th channel CH1 to CHM, CH1, CH1
2 are channels of the same line speed (Xb / s) occupying x TSs on the frame. CH3,
CH4, CH5, CH6, CH7, CH8, CH9,.
.., CHM are channels of the same line speed (Yb / s) occupying y TSs on the frame.

The frame data (STM multiplexed input signal) of FIG. 5 is stored in the input buffer device 12 via the STM multiplexed input line 11. The VPI / VCI-specific data storage control unit 151 converts the frame data of 1 TS (for 1 byte) from the conversion information 3 between CH and VPI / VCI.
The corresponding VPI / PI in the data storage unit 141 for each PI / VCI
It is stored in the VCI storage area.

Here, CH1 is the data of the corresponding TS (TS data) from the first frame corresponding to the corresponding VPI / V
The storage in the CI storage area is started. CH2 starts storing the corresponding TS data in the corresponding VPI / VCI storage area from the first frame. CH3 starts storing the corresponding TS data in the corresponding VPI / VCI storage area from the first frame. In addition, CH4 starts storing the corresponding TS data in the corresponding VPI / VCI storage area from the first frame. In the same manner, all the channels multiplexed in the frame start to distribute the first received frame data to the VPI / VCI storage area after the start-up of the device.

FIG. 6 shows the distribution of the channel data for each frame of the frame data shown in FIG. 5 to the storage area for each VPI / VCI or the storage situation in the storage area for each VPI / VCI.

The cell storage determination section 152 determines whether the payload data amount (user information) necessary for cell conversion has been stored in each VPI / VCI by writing the TS data. If data to be cellized is stored in the celling buffer device 14, a celling request is issued,
AAL layer processing unit 153, ATM layer processing unit 154
Then, the cell assembling process is executed by the ATM cell transmitting unit 161. The AAL layer processing unit 153 uses
A process according to the AL is executed to generate and add AAL header information. The ATM layer processing section 54 generates and adds ATM header information to generate a 53-byte ATM cell, and outputs the ATM cell to the ATM cell transmitting section 161.

As described above, the frame data shown in FIG. 5 is received by the conventional method, and the frame data is distributed according to VPI / VCI and stored in the corresponding VPI / VCI storage areas. The graph shown is obtained. As a result, as shown in FIG.
Data for 1 cell for 1 and CH2 is accumulated, and a celling request is issued. CH3, C after time T5
Data for one cell for H4, CH5, CH6, CH7, CH8 and CH9 is accumulated, and a celling request is issued.

Therefore, it is required to assemble two cells for CH1 and CH2 in one frame time from time T4 to T5, and to set CH3, CH4, CH5, CH6, and CH7 in one frame time from time T5 to T6. ,
It is required to assemble seven cells for CH8 and CH9.

Here, the celling request is defined as an event in which the celling accumulation judging section 152 judges that the amount of payload data necessary for celling has been accumulated. Note that the request is A
It can be considered as a trigger for starting the cell assembling process executed by the AL layer processing unit 153, the ATM layer processing unit 154, and the ATM cell transmission unit 161. The number of cellization requests is the number of CHs that issued a cellization request during a certain period of time.
(VPI / VCI) number.

[0021]

According to the conventional cell assembling processing apparatus, the timing to start storing frame data in the corresponding VPI / VCI storage area based on the conversion information between the CH and the VPI / VCI is common to all the CHs. Therefore, there has been a problem that cellization requests are concentrated in a certain period of time. As a result, there are cells in which the load is concentrated on the processor that executes the cell assembly and the cells must wait for processing, and the cells that are waiting to be transmitted when the ATM cell transmitting unit transmits the transmission path after the cell is assembled. Occurs. As a result, there is a problem that the delay time in the cell assembling apparatus increases.

(Purpose) The present invention disperses the load on the processor executing the cell assembling process by dispersing the timing of a cell request in the cell assembling process, and further reduces the delay time in the cell assembling apparatus. The purpose is to let them.

[0023]

According to the cell assembling process of the present invention, data of a channel is distributed to a storage area for each VPI / VCI based on correspondence information between a channel and a VPI / VCI, stored, and then converted into a cell. In the cell assembling process for assembling the STM multiplexed signal accommodating a plurality of lines of an arbitrary speed into ATM cells as described above, the distribution of the data of the channel of the same line speed of the STM multiplexed signal to the storage area for each VPI / VCI is performed in channel units And is shifted at least by one frame time interval. And
When the amount of data stored in the storage area for each VPI / VCI in the cell assembling process reaches the amount of data required to be converted into an ATM cell, one cell of data is read from the storage area to generate an ATM cell. It is characterized by.

Further, the cell assembling processing apparatus of the present invention has a
A frame data receiving unit for receiving an M-multiplexed signal;
VPI / VCI data storage unit having a storage area for each VPI / VCI, and VPI / VCI data for storing the data of each channel received by the frame data receiving unit in the VPI / VCI storage area corresponding to each data An accumulation control unit, and an ATM for reading out one cell of data from the accumulation area and generating an ATM cell when the data accumulated in the accumulation area for each VPI / VCI reaches a data amount necessary for ATM cell conversion. It is characterized by having a processing unit and an accumulation start control unit for dispersing the accumulation start time of the data of each channel in the accumulation area for each VPI / VCI in frame units.

Further, the cell assembling apparatus includes the V
It is determined whether the amount of data stored in the storage area for each PI / VCI is the data amount required for ATM cell conversion, and when the data amount required for ATM cell storage is stored, the data of the storage area is requested to be cellized. A cell-storage / accumulation determining unit for outputting a cell-forming request; and the ATM processing unit includes a VPI / VCI
An AAL layer processing unit for adding an AAL header to storage data in another storage area to form a cell, and a VPI / VCI AT
And an ATM layer processing unit for adding an M header.

Further, the frame data receiving section includes a frame counter that periodically increments for each frame data, and the accumulation start control section controls an ID previously assigned to each channel for each line speed of the STM multiplex signal.
And accumulating the channel data in the VPI / VCI-specific data accumulating unit when the count value of the frame counter matches the count value of the frame counter. The frame counter is constituted by a counter having a count value corresponding to the maximum number of channels having the same line speed, and an ID assigned to each channel in advance is a different value for each channel having the same line speed within the range of the count value. Is set.

The ATM cell payload includes:
Only information of the same CH can be accommodated.
8-byte user data and a 5-byte header can be added. The header includes VPI / VCI and CH
Can be provided. Also, AAL
The processing in the layer is a processing performed for each CH for assembling and disassembling the 48-byte user data, and a header in the processing can be included in the 48 bytes of the user data. The cell assembling process including the ALL process can be executed by a processor and performed by software.

More specifically, in the cell assembling processing apparatus of the present invention, the frame data receiving unit (21 in FIG. 1)
A frame counter that counts each time one frame data is received is provided. The frame counter is 1, 2,
, N, 1, 2,... (However, the value of n is determined by the maximum number of multiplexed channels having the same line speed among the channel CHs multiplexed in the frame. ).

After the cell assembling apparatus start-up processing, the data of the corresponding CH (CH data) is output from each of the frame data received by the frame data receiving unit to each CH.
Information (ID) as to whether the data is to be stored in the PI / VCI storage area is given in advance.

Then, the accumulation start control section (55 in FIG. 1) refers to the frame counter value obtained from the frame data receiving section, and compares the frame counter value with a predetermined value (I
If D) matches, the corresponding VPI / VC for that CH
The distribution to the I accumulation area is started.

(Operation) For CHs having the same line speed,
The distribution to the corresponding VPI / VCI storage area is started with a shift at one frame time interval. As a result, the number of cellization requests within one frame time generated by CHs of the same line speed can be minimized, and even if CHs of different line speeds are multiplexed in a frame in any combination, the maximum , The number of cellization requests can be minimized. That is, the timing of cell formation can be dispersed.

[0032]

Embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, in the first embodiment of the present invention, an STM multiplex input line 1 for storing frame data, an input buffer device 2 for storing frame data, and an externally set input buffer device 2 are provided. A correspondence information 3 between the CH and the VPI / VCI, a cell buffer unit 4 for storing the information,
It comprises a data processing device 5 which can be executed by a processor or can be operated under software control, and an output buffer device 6 for sending out ATM cells.

The input buffer device 2 includes a frame data receiving unit 21. The frame data receiving unit 21
The frame data input via the M multiplex input line (S
TM multiplexed signal). The CH (channel) of the frame data is identified from the time position of the line TS (time slot). Also, the frame data receiving unit 2
1 has a frame counter that counts each time one frame data is received. The frame counter is 1,
, N, 1, 2, 3,.... Here, the value of n is determined by the maximum multiplexing number of the same line speed among the CHs multiplexed in the frame.

The cell buffer 4 is composed of VPI / VCI
A VPI / VCI-specific data storage unit 41 having a data storage area capable of separately managing a data storage amount is provided.

The data processing device 5 includes a data storage control unit 51 for each VPI / VCI, a cell storage determination unit 52, an AA
An L layer processing unit 53, an ATM layer processing unit 54, and an accumulation start control unit 55 are provided. The VPI / VCI-specific data storage control unit 51 converts the frame data stored in the frame data receiving unit 21 into the VPI / VCI based on the conversion information from the CH to the VPI / VCI input from the correspondence information 3 between the CH and the VPI / VCI. / VCI, and assigns the corresponding VPI in the VPI / VCI-specific data storage unit 41.
/ VCI storage area.

Here, the start of distribution of each CH to the corresponding VPI / VCI storage area is independently controlled for each CH by the storage start control unit 55 as follows.

Each CH is set after the cell assembling apparatus start-up processing.
From the number of frame data received by the frame data receiving unit 21, each corresponding CH data is converted to VPI / VC
Information (ID) related to whether or not to accumulate in the I accumulation area is set in advance. Then, referring to the frame counter value obtained from the frame data receiving unit 21, from the time when the frame counter value matches the value of the information (ID) given in advance, the CH is allocated to the corresponding VPI / VCI storage area. To start.

The cell-based accumulation judging section 52 calculates the VPI / V
For each VPI / VCI storage area of the CI-specific data storage unit 41, it is determined whether or not a desired amount of user data requiring cellization has been stored. Here, the desired amount of user data is, for example, 46 bytes, 47 bytes, 48 bytes, or the like, and is determined by the AAL type used.

The AAL layer processing unit 53 uses the AA
A process necessary for the L type is performed, and AAL header information is generated and added.

The ATM layer processing section 54 has a VPI / VC
Generate and add an ATM header with I as the main information, 53
Generate a byte ATM cell.

The output buffer unit 6 is an ATM cell transmitting unit 6
1 and the ATM cell transmitting section 61 outputs the ATM cell to the ATM multiplex output line.

Referring to FIGS. 5, 1 and 2, as a specific operation example of the embodiment of the present invention, the operation when cell assembly processing apparatus shown in FIG. 1 receives frame data shown in FIG. Will be described.

In the frame data of FIG. 5, it is possible to multiplex CHs of different line speeds on TSs (time slots) 1 to A.
Are multiplexed. That is, CH1, CH2
Are channels of the same line speed (Xb / s) occupying x TSs on a frame. CH3, CH4, CH
5, CH6, CH7, CH8, CH9,..., CHM
Are channels of the same line speed (Yb / s) occupying y TSs on the frame (where M−
2 represents the multiplexing number of the line speed Yb / s, and it is assumed that M-2> 2). The IDs given to the CH1 to CHM in advance are CH1 “1”, CH2 “2”, CH3
"1", CH4 "2", CH5 "3", CH6 "4",
CH7 "5", CH8 "6", CH9 "7", ...,
CHM "M-2" (the value in "" is the ID).

Here, the frame counter in the frame data receiving section 21 (FIG. 1) is 1, 2, 3,.
., M-2, 1, 2,... That is, the frame counter has the maximum value among the multiplex numbers of the same line speed (in this case, the multiplex number of the line speed Xb / s is 2, and the multiplex number of the line speed Yb / s is M-2, so the maximum value is M− Count up to 2).

As a more specific configuration for multiplexing CHs of different line speeds, for example, when M−2 = 8, the ID given to CH1 to CH8 in advance is CH
1 “0”, CH2 “1”, CH3 “0”, CH4
"1", CH5 "2", CH6 "3", CH7 "4",
CH8 “5”, CH9 “6”, and the frame counter is 0, 1, 2, 3,..., 7, 0, 1, 2,.
And a modulo (modulus) 8 counter (a counter having a function of dividing the count value by 8 and outputting the remainder thereof) that outputs a periodic value as described above.

The STM multiplexed input signal (frame data) of FIG. 5 is stored in the input buffer device 2 via the STM multiplexed input line 1 (FIG. 1), and the frame counter is incremented every time one frame data is received. .

VPI / VCI-specific data storage controller 51
Indicates that the frame data is CH in units of 1 TS (1 byte).
And VPI / VCI based on conversion information from CH to VPI / VCI obtained from correspondence information 3 between VPI / VCI.
The data is stored in the corresponding VPI / VCI storage area of the I-specific data storage unit 41.

Here, the control at the start of the accumulation of each CH is performed by the accumulation start control unit 55. Storage start control unit 5
Reference numeral 5 compares an ID value preset for each CH with a frame counter value, and controls so as to start accumulation at a timing when the two coincide with each other. That is, CH1 stores the corresponding TS data from the first frame in the corresponding VPl / VCI.
Start accumulation in the accumulation area. CH2 starts storing the corresponding TS data in the corresponding VPI / VCI storage area from the second frame (the corresponding T2 of CH1 in the first frame).
S data is discarded). CH3 starts storing the corresponding Ts data in the corresponding VPI / VCI storage area from the first frame. CH4 is the corresponding TS from the second frame
Data storage is started in the corresponding VPI / VCI storage area (the corresponding TS data of CH4 in the first frame is discarded). CH5 starts storing the corresponding TS data in the corresponding VPl / VCI storage area from the third frame (the corresponding T1 of CH2 in the first and second frames).
S data is discarded). The same applies hereinafter.

FIG. 2 shows the distribution of the channel data for each frame of the frame data shown in FIG. 5 to the storage areas for each VPI / VCI and the storage status of the storage areas for each VPI / VCI.

The celling accumulation judging section 52 judges whether or not the payload data amount (user information) necessary for celling has been accumulated in the corresponding VPI / VCI by writing the TS data. If the amount of data to be converted into cells is stored in the cell buffer 4, the AAL layer processing unit 53, the ATM layer processing unit 54, and the ATM cell transmitting unit 61 execute a cell assembling process. The AAL layer processing unit 53 executes processing according to the AAL to be used, generates and adds AAL header information. The ATM layer processing unit 54 generates and adds ATM header information,
A 3-byte ATM cell is generated and output to the ATM cell transmitting unit 61.

As described above, in the embodiment of the present invention, FIG.
Of frame data of the VPI /
When the data is sorted by VCI and stored in the corresponding VPI / VCI storage area, the data is stored as shown in FIG. As a result, as shown in FIG. 3, after time T2, data for one cell for CH1 is accumulated, and a celling request is issued. After time T3, data for one cell for CH2 is accumulated, and a celling request is issued. Time T4
Thereafter, data for one cell for CH1 is accumulated, and a celling request is issued. CH2 and C after time T5
Data for one cell for H3 is accumulated, and a celling request is issued. After time T6, data for one cell for CH4 is accumulated, and a celling request is issued.
Since the same applies hereinafter, the number of cellization requests during one frame time is at most one for the same line speed. Therefore, from time T2 to time T5, CH1 and CH2
It is sufficient to assemble one cell alternately for. In one frame time from time T5 to T6, CH2 and C
Assembling two cells for H3 is sufficient. 1 frame for CH4 in one frame time from time T6 to T7
Assembling one cell is enough. Similarly, after time T7, it is sufficient to assemble 1-2 cells in any one of the channels. Thus, it can be seen that the assembly of cells in the same frame is dispersed and the concentration can be avoided as in the related art.

There are several types of AAL processing depending on the transmission service class.
AALtype1 that handles (Constant Bit Rate) signals
(Hereinafter referred to as “AAL1”), the AAL header 1
-P composed of bytes and 47 bytes of user data
There is a cell called a format and a cell called a P format composed of 2 bytes of an AAL header and 46 bytes of user data.

The basic information of the first byte of the AAL header in both formats is SC (Sequence Count). SC is a number indicating the order for each cell, and is periodically assigned to each cell as a number on the transmitting side by modulo 8, such as 0, 1, 2,... 7, 0, 1, 2,. The P format cell is used when a structured data transfer protocol is used. Structured data transfer
This is used when the receiving side needs to know this frame structure when the user signal has a frame structure. In this structured data transfer, a pointer indicating the position of the first byte of the frame of the user signal is inserted into the second byte of the AAL header. However, even when the protocol for structured data transfer is used, all cells are in the P format. Instead, a pointer is inserted according to a certain rule, and, for example, a P-format cell is output once every eight-cell output (seven out of eight cells are non-P-format cells). At this time, since the frame head byte position is different for each cell, it is necessary to calculate a pointer for each cell. AAL layer processing unit 5
In No. 3, the AAL1 and other ALLtype ALL processes including the above process and the pointer process are realized.

As described above, in the present invention, it is necessary to discard a small amount of frame data for each CH after the apparatus start-up processing.
Is slightly shorter than the device start-up processing time, and in actual operation, it can be said that the connection time from calling to connection establishment is slightly extended.

In the above embodiment, the operation of starting data storage in the cell buffering device after the start-up process of the cell assembling device has been described. However, the device can change the channel CH required during its operation. Can respond flexibly. That is, in the cell assembling apparatus, it may be required to stop the service of an arbitrary CH and add the service of an arbitrary CH during the operation of another CH. For example, the service of the CH4 and CH5 in the above example is stopped. Then, new CH1
When 0 is added, such a change can be appropriately realized by appropriately selecting an ID given to CH10. That is, since “2” and “3” of the IDs of CH4 and CH5 are released, it is sufficient to change any of the IDs “2” and “3” to be given to CH10. C
When “2” is given as the ID of H10, the corresponding TS data of CH10 is started to be stored in the cell buffer at the timing when the frame counter value during operation of the cell assembling apparatus becomes 2.

In the above embodiment, the cell buffering device (VPI) for each CH data of the STM multiplexed input signal
/ VCI-based data storage unit), an example has been described in which a method is employed in which the distribution is uniformly performed in units of one frame for each CH having the same line speed. It is possible to configure such that the CHs smaller than the value are dispersed at intervals of a plurality of frames by setting the ID value. Also, it is possible that the CH data having the maximum value of the multiplexing number can be configured to be distributed at a plurality of frame intervals by setting the frame counter to a count value larger than the maximum value of the multiplexing number. It is clear. Further, it goes without saying that, depending on the processing capacity of the data processing device, the storage start time may be started in the same frame without dispersing the accumulation start time for some of the plurality of CHs.

[0058]

According to the present invention, the timing for starting the accumulation in the VPI / VCI accumulation area is shifted by one frame time interval for the CH data of the same line speed. The number can be reduced. In particular, it is possible to minimize the number of cellization requests issued on CHs having the same line speed. This means that the maximum number of cellization requests can be minimized regardless of the combination of different line speeds in a frame in any combination.

Further, according to the present invention, the number of celling requests during one frame time can be reduced, so that the number of cells to be assembled per frame time can be reduced, and the AAL
It is possible to reduce the load on the processor that executes the cell assembling process in the ATM layer and the ATM layer.

Further, since the number of cells to be assembled during one frame time is averaged, the number of cells waiting to be assembled by the AAL layer processing unit and the ATM layer processing unit is reduced, and the transmission path is reduced by the ATM cell transmission unit. Since the number of cells waiting for cell output when the cell is transmitted is reduced, the cell delay time in the cell assembling apparatus can be reduced.

Since the number of cells waiting for cell assembly processing and cell output is reduced, the amount of data remaining in the cell buffer and the output buffer is reduced, so that the buffer capacity provided in the cell buffer is reduced. can do.

Since the trigger (request) for starting cell assembly is dispersed, the output of the ATM cell (user cell) to the transmission path is also dispersed, and this plays a role of simple shaping. Stress can be reduced.

[0063]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing distribution of channel data to storage areas for each VPI / VCI.

FIG. 3 is a diagram illustrating an operation of assembling a cell according to the embodiment;

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a diagram showing frame data in an STM multiplex input line.

FIG. 6 is a diagram showing distribution of channel data to storage areas by VPI / VCI.

FIG. 7 is a diagram showing a cell assembling operation of a conventional example.

[Explanation of symbols]

 1,11 STM multiplex input line 2,12 input buffer device 3,13 correspondence information between CH and VPI / VCI 4,14 cell buffer device 5,15 data processing device 6,16 output buffer device 10,12 ATM multiplex output Line 21, 121 Frame data receiving unit 41, 141 VPI / VCI-specific data storage unit 51, 151 VPI / VCI-specific data storage control unit 52, 152 Cellular storage determination unit 53, 153 AAL layer processing unit 54, 154 ATM layer processing Unit 55 accumulation start control unit 61, 161 ATM cell transmission unit

Continuation of front page (56) References JP-A-6-261064 (JP, A) IEICE Technical Report SSE93-17 IEICE, Vol. 79-B-I I No. 2 p31-40 1997 IEICE Communications Conference B-7-17 1994 IEICE Spring Conference B-550 1993 IEICE Autumn Meeting B-416 NTT R & D Vol. 44 No. 10 pp961-968 (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/56 H04L 12/28

Claims (1)

(57) [Claims] 1. A frame data receiving unit for receiving an STM multiplexed signal, and a VP having a storage area for each VPI / VCI.
An I / VCI-specific data storage unit, and a VPI / VCI storing the data of each channel received by the frame data receiving unit in the VPI / VCI-specific storage area corresponding to each data.
A separate data storage control unit and, when the data stored in the storage area for each VPI / VCI reaches a data amount necessary for conversion to an ATM cell, reads out one cell of data from the storage area and generates an ATM cell A cell assembling processing apparatus having an ATM processing unit, wherein the frame data receiving unit periodically increments for each frame data;
The frame counter of the maximum count value corresponding to the maximum multiplex number of the same line speed among the channels multiplexed in the frame and the range of the count value previously allocated to each channel for each of the same line speeds of the STM multiplexed signal are different from each other. A cell start-up unit for controlling to start storing data of each channel in a VPI / VCI-based data storage unit when an ID matches the count value of the frame counter. Processing equipment.