JP2960744B2 - Pulse width modulation signal generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating two types of pulse width modulation signals having pulse waveforms opposite to each other and having a fixed time difference between a rising point and a falling point. Things.

2. Description of the Related Art A pulse width modulated signal (hereinafter referred to as PWM
Signal)) to control the operation of an electric motor such as a DC motor or an AC motor, or a power transformer. In this case, two types of PWM signals having opposite pulse waveforms are generated. In some cases, a pair of controlled elements, which are switched between an on state and an off state in accordance with a change in the level of the PWM signal, are controlled so as to be in opposite states. For example, Figure 5 shows a three-phase brushless DC
An example of a control circuit that controls the rotation speed of the motor 10 (hereinafter simply referred to as DC motor 10)
The energization state for the U phase, V phase, and W phase is switched by 12; however, a pair of transistors for switching the energization state of each phase are PWM-controlled so that the on state and the off state are opposite to each other. The pulse waveform supplied from the signal generation circuit 14 is switched and controlled by PWM signals opposite to each other.

The U-phase will be described in detail. As shown in FIG. 6, when the PWM signal X is at the H level, the transistor T
While r1 is in a conductive state (ON state), the PWM signal X 'whose HL level is inverted with respect to the PWM signal X is at L level at this time, so that the transistor Tr2 is in a non-conductive state (OFF state). The power supply 16 is connected to the U phase of the DC motor 10.
Is supplied. When the PWM signal X is at L level and the PWM signal X 'is at H level, the transistor Tr1
Is turned off, the transistor Tr2 is turned on, and the U-phase is grounded via the transistor Tr2, so that the conduction to the V-phase or W-phase is allowed. In this example, the transistors Tr1 and Tr2 correspond to a pair of controlled elements that are controlled to be switched on and off by two types of PWM signals X and X 'so as to be in opposite states.

By the way, since the turn-off time when the transistor changes from the conductive state to the non-conductive state is generally longer than the turn-on time when the transistor changes from the non-conductive state to the conductive state, the PWM signals X and X ′ are used.
FIG. 7 shows the response of the transistors Tr1 and Tr2 to the level change of the transistor. When the transistors Tr1 and Tr2 are turned on and off, the transistors Tr1 and Tr2 are instantaneously turned on to generate a spike current. was there. Therefore, when switching control of a pair of controlled elements having different turn-on times and turn-off times,
A certain time difference (dead time) τD is provided between the rising point and the falling point of the two types of PWM signals to prevent the occurrence of the spike current or the like.
The turn-on time and the turn-off time are determined by the responsiveness of three transistors from the photocoupler to Tr1 or Tr2 in FIG.

The PWM signal generation circuit 14 generates two types of PWM signals having opposite pulse waveforms and a fixed time difference τD between a rising point and a falling point as described above. An example is shown in FIG. The ninth
FIG. 10 and FIG. 10 are time charts showing an example of signals of respective parts of the circuit of FIG. Hereinafter, the PWM signal generation circuit 14 will be specifically described.

In FIG. 8, a signal r1 corresponding to a deviation between a preset command speed and the current speed is output from the speed control unit 20, while the DC motor 10, the transistors Tr1, Tr2, etc. are output from the triangular wave generation circuit 22. A signal T1 for generating a triangular wave at a predetermined constant cycle according to the characteristics of
In, a pulse signal A1 that continues at the H level only while the signal r1 is higher than T1 is output. This pulse signal A1 is
A pulse is generated with the same period as the signal T1 and the signal r1
Pulse width modulated PWM signal based on DC motor 10
Is the basis of speed control.

The signal A1 is directly input to the logic circuit 26 having an exclusive OR function, and is input to the same logic circuit 26 as a signal B1 delayed by a time constant determined by the resistor RI and the capacitor C1, and the logic circuit 26 From 26, a trigger signal C1 that generates a pulse with a delay at the rise and fall of the signal B1 is output. The trigger signal C1 is input to the monostable multivibrator 28, and a signal D1 that keeps the L level for a time constant determined by the resistor RII and the capacitor CII is output in synchronization with the trigger signal C1. The L-level pulse width of the signal D1 corresponds to the constant time difference τD, and the resistance and capacitance of the resistor RII and the capacitor CII that define the time difference τD are as follows:
It is determined in consideration of the difference between the turn-on time and the turn-off time of the controlled element including the transistors Tr1 and Tr2.

The signal A1 is obtained by inverting the HL level of the signal A1.
The signal E1 is obtained by inputting 1 'and the signal D1 to the AND circuit 30, and the signal F1 is obtained by inputting the signal A1 and the signal D1 to the AND circuit 32. These signals
E1 and F1 have their HL levels inverted with respect to each other, and the rising point is delayed by a time difference τD from the falling point of the other signal.
Used as M signal X, X '. Since the H level pulse width of the signal E1 which becomes the PWM signal X and defines the energization time to the U phase is shorter than the L level pulse width of the signal A1 by the time difference τD, the pulse width of the signal A1 is defined. The signal
r1 is corrected as necessary so that the H level pulse width of the signal E1 becomes a predetermined pulse width.

However, the PWM signal generation circuit 14 includes a triangular wave generation circuit 22, a comparator 24, resistors RI and RII, and capacitors CI and CII.
The characteristic values fluctuate due to temperature changes and the like, and the period of the signal T1 and the pulse widths of the signals A1 and D1 change accordingly, and the PWM signals E1 and F1
Variations occur in the pulse width and the pulse generation timing of 1, which causes a decrease in the accuracy of the rotation speed control of the DC motor 10.

On the other hand, in order to avoid such a problem, a PWM signal generation circuit that performs pulse width modulation under computer control has recently been proposed. This is configured, for example, as shown in FIG. 11, and the signals of the respective parts are as shown in FIG. This PWM signal generation circuit 14 '
Has three clock generators 36, 38, and 40, and outputs clock signals T2, CLK, and DLE that generate rectangular pulses at a predetermined constant cycle. The clock signal T2 defines the pulse generation cycle of the final PWM signals X and X ', and the pulse generation cycle PT1 is the same as the triangular wave generation cycle of the signal T1 such as the DC motor 10 and the transistors Tr1 and Tr2. For example, it is set to about 512 μsec according to the characteristics. The clock signal CLK determines the pulse width of the pulse width modulation based on the number of pulses, and determines the accuracy of the pulse width modulation. The pulse generation period PT2 is sufficiently longer than the pulse generation period PT1 of the clock signal T2. Short, for example 500
It is set to about n seconds. The clock signal DLE defines the time difference τD, and its pulse generation period PT3
Considering the difference between the turn-on time and the turn-off time of the controlled element including the transistors Tr1 and Tr2,
For example, it is set to about 16 μsec.

The clock signals T2 and CLK are supplied to the computer system 42 and the timer IC 46, respectively. The computer system 42 is also supplied with a signal representing the actual rotation speed from the DC motor 10, and performs signal processing in accordance with a program stored in advance, so that a difference between the command speed and the actual speed is obtained. By calculating the duty ratio from the deviation and multiplying the duty ratio by the pulse generation period PT1 of the clock signal T2, the pulse width or the pulse duration of the PWM signals X and X 'corresponding to the duty ratio is calculated. By dividing the pulse duration by the pulse generation period PT2 of the clock signal CLK, the number of pulses P of the clock signal CLK corresponding to the pulse duration is calculated.

Then, a control signal indicating the pulse number P is supplied to the timer IC 46 via the system bus 44. Timer IC46
The number of pulses P is stored in a down counter, the output signal A2 is set to the L level simultaneously with the rise of the clock signal T2, and the content of the down counter is reduced by one for each pulse of the clock signal CLK. The signal A2 is maintained at the L level until the content becomes 0. Therefore, this signal A2 is the pulse generation period PT of the clock signal T2.
A pulse is generated at 1 and the L level pulse width is controlled based on the number of pulses of the clock signal CLK in accordance with the duty ratio obtained in the computer system 42. This signal A2 is based on the PW
This corresponds to the signal A1 in the M signal generation circuit 14.

The signal A2 is input to the delay generating IC 48, and is latched and output at each rising of the clock signal DLE, thereby obtaining the signal AL2. The signal AL2 is again input to the delay generating IC 48, and is latched and output at each rising edge of the clock signal DLE, thereby obtaining the signal AM2. This signal A
M2 is delayed from the signal AL2 by one cycle of the clock signal DLE, for example, about 16 μsec.
The signal E2 is obtained by inputting both signals AL2 and AM2 to the NOR circuit 50, and the signal F2 is obtained by inputting both signals AL2 and AM2 to the AND circuit 52. These signals E2 and F2 correspond to the signals E1 and F1, respectively, and
Used as X, X '.

Since there is no analog element in the PWM signal generation circuit 14 ', a decrease in accuracy due to a temperature change or the like as in the PWM signal generation circuit 14 is avoided.

Problems to be Solved by the Invention However, PWM by the above computer system
In the signal generation circuit, there is a problem that the pulse width of the PWM signal and the generation timing of the pulse are varied, and the accuracy of the switching control of the controlled element and the control of the rotation speed of the motor are impaired.

The conventional example shown in FIGS. 11 and 12 will be specifically described. The AL whose phase is shifted by a certain time difference τD
The delay generating IC for generating two signals and AM2 signal
48 is based on the clock signal DLE having the same cycle as the time difference τD, and the signal A is generated at every rising edge of the clock signal DLE.
2 to output the signal AL2, the pulse width and the pulse generation timing of the signal AL2 are different from the pulse generation period PT3 of the clock signal DLE, that is, the time difference τD, with respect to the signal A2 which is the basis of the PWM signal to be generated. It varies within the range. Thereby, even if the pulse width modulation of the signal A2 is performed at a resolution of, for example, 500 ns based on the number of pulses of the clock signal CLK, the clock signal DLE is added to the final pulse width and pulse generation timing of the signals E2 and F2. In this case, an error of about 16 μsec occurs in the pulse generation period PT3, that is, the above example, and the accuracy thereof is reduced to 1/32.

The present invention has been made in view of the above circumstances, and has as its object the pulse width of a PWM signal finally obtained in a PWM signal generation circuit by the computer system which is less affected by temperature changes and the like. It is to improve the accuracy of the pulse generation timing.

Means for Solving the Problems In order to achieve the above object, the present invention provides a method for generating a pulse at a constant period and using two types of PWM signals having pulse width modulated pulse waveforms opposite to each other. When a pair of controlled elements that are switched between an on state and an off state in response to a change in the level are controlled so as to be in opposite states, the rising and falling points of the two types of PWM signals are determined. A PWM signal generating circuit for providing a fixed time difference between the first clock generator and a first clock generator for outputting a first clock signal for generating a pulse in the same cycle as the pulse generation cycle of the PWM signal; A second clock generator that outputs a second clock signal that generates a pulse at a predetermined constant period sufficiently shorter than a pulse generation period of the first clock signal;
Pulse width control means for controlling the pulse width of the PWM signal, obtaining the number of pulses of the second clock signal corresponding to the time corresponding to the pulse width to be controlled, and outputting a control signal representing the number of pulses; And (d) generating pulses in synchronization with the first clock signal, and counting the number of pulses of the second clock signal by the number of pulses represented by the control signal, thereby obtaining the number of pulses of the second clock signal. (E) fetching the reference pulse signal in synchronization with a shift signal that generates a pulse at a constant period sufficiently shorter than the predetermined time difference. And a shift register for storing and outputting after a predetermined number of pulses of the predetermined shift signal corresponding to the predetermined time difference. And (f) performing a logical operation using the reference pulse signal and an output signal from the shift register delayed by the predetermined time difference from the reference pulse signal, so that the pulse waveforms are opposite and rise from the rising point. Logic operation means for generating and outputting two types of PWM signals having a certain time difference from the falling point.

Here, the shift signal defining the operation of the shift register may be supplied from a single shift signal generator, but the second clock signal output from the second clock generator may be used. Is also possible.

The generation of two types of PWM signals by the logical operation means includes, for example, the case where an output signal from the shift register is used as it is as one PWM signal and the other PWM signal is generated by logical operation. This is because, from a signal delayed by a fixed time difference from the reference pulse signal, a signal further delayed by the fixed time difference is extracted from the shift register, and two types of PWs are obtained from these three signals.
It can be adopted when generating an M signal.

In addition, such a PWM signal generation circuit uses the output signal from the shift register and the reference pulse signal to make a final PWM signal.
A signal is generated. As a shift register, (g) the reference pulse signal is fetched and stored in synchronization with the shift signal, and the shift register stores the predetermined shift signal corresponding to the predetermined time difference. (H) outputting a plurality of signals which are delayed from each other by a predetermined number of pulses at a fixed timing determined by the number of pulses of the shift signal with respect to the reference pulse signal; By performing a logical operation using a plurality of output signals output from the shift register, two types of PWM signals having opposite pulse waveforms and having a certain time difference between a rising point and a falling point are generated. It is also possible to adopt what is output.
In this case, the logical operation means does not necessarily need to use the reference pulse signal, and may generate two types of PWM signals by performing a logical operation on only the signal output from the shift register.

Operation and Effect of the Invention In such a PWM signal generation circuit, first, the first
A first clock signal output from the clock generator, a second clock signal output from the second clock generator,
A reference pulse signal having a pulse width corresponding to the number of pulses represented by the control signal and generating a pulse in synchronization with the first clock signal based on the control signal output from the pulse width control means; Output from Up to this point, it is substantially the same as the conventional example shown in FIG.

Thereafter, the reference pulse signal is supplied to a shift register, and a signal delayed by a certain time difference determined based on the number of pulses of the shift signal is generated. Then, using the output signal from the shift register and the reference pulse signal, two types of PWM signals having opposite pulse waveforms and a fixed time difference between the rising point and the falling point are generated by the logical operation means. Generated.

In this case, the delay time and pulse width variation of the output signal from the shift register with respect to the reference pulse signal are determined by the pulse generation cycle of the shift signal, and the pulse generation cycle of the shift signal has a fixed time difference to be delayed. Since the cycle is sufficiently shorter than the above, the variation in the delay time and the pulse width is small. As a result, compared to the conventional case in which a delay signal is generated using a clock signal that generates a pulse with the same cycle as the constant time difference,
Variations in the pulse width and pulse generation timing of the finally obtained PWM signal are also reduced, and the switching of the pair of controlled elements is controlled with high accuracy.

Note that the delay time and pulse width of the output signal from the shift register vary strictly within the range of the pulse generation cycle of the shift signal, and the pulse width and pulse generation timing of the PWM signal also vary within the same range. If the pulse generation period of the shift signal is the same as the pulse generation period of the second clock signal that determines the pulse width modulation accuracy of the reference pulse signal, the accuracy with respect to the delay time and the pulse width becomes the accuracy of the pulse width modulation. And the accuracy of the pulse width modulation is maintained as it is until the final PWM signal. As can be seen from this, it is desirable that the pulse generation period of the shift signal be substantially the same as the pulse generation period of the second clock signal.

On the other hand, a plurality of shift registers, which fetch and store the reference pulse signal in synchronization with the shift signal, and delay each other by a predetermined number of pulses of the predetermined shift signal corresponding to the predetermined time difference And a signal which is output at a fixed timing determined by the number of pulses of the shift signal with respect to the reference pulse signal, and uses a plurality of output signals output from the shift register as logic operation means. In the second invention, the two pulse signals having opposite pulse waveforms and having a certain time difference between the rising point and the falling point are generated and output by the arithmetic operation. The final PWM signal is generated by using a plurality of output signals, and the plurality of output signals correspond to the reference pulse signal. Variations in the pulse width and the pulse generation timing because determined by the pulse generation period of the shift signal, as in the first invention, the pulse width and the pulse generation timing accuracy of the PWM signal is improved.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following embodiments, portions common to the above-described conventional example are denoted by the same reference numerals, and detailed description is omitted.

FIG. 1 shows a PWM signal generating circuit 60 according to an embodiment of the present invention.
FIG. 2 is a time chart showing an example of a signal of each section of the PWM signal generation circuit 60 of FIG.
In these figures, the clock generators 36 and 38, the computer system 42, and the timer IC 46 are configured exactly the same as the conventional example shown in FIG. 11, but the signal A2 and the clock output from the timer IC 46 are output. The clock signal CLK output from the generator 38 is input to the shift register 62. The shift register 62 is formed by serially connecting a plurality of registers such as flip-flops. The shift register 62 takes in the signal A2 in synchronization with the clock signal CLK, stores the content in the register, and stores the content of the register in the register. The stored contents are output from a preset n-th register. Therefore, the output signal AL3 of the shift register 62 becomes n in the pulse generation period PT2 of the clock signal CLK.
Is multiplied by the signal A2. The delay time of the signal AL3 defines a constant time difference τD between the rising point and the falling point of the final PWM signal X, X ′. For example, the time difference τD is 16 μsec and the pulse generation period PT2 is In the case of 500n seconds, the above “n” is set to 32.

Signals A2 'and AL3' obtained by inverting the HL levels of the signals A2 and AL3 are obtained by NOT circuits 64 and 66, respectively, and an AND circuit is formed from these signals A2 'and AL3'.
The signal E3 is generated by 68 while the signals A2 and AL3
, A signal F3 is generated by the AND circuit 70. These signals E3 and F3 have their HL levels inverted with respect to each other, and their rising points are delayed by a time difference τD from the falling points of the other signals. Used as signals X, X '.

It should be noted that instead of the above NOT circuits 64 and 66 and the AND circuit 68, N
The signal E3 can also be generated using an OR circuit. Also,
A signal E3 that becomes the PWM signal X and regulates the energization time to the U phase
Is shorter than the L level pulse width of the signal A2 by the time difference τD, the program of the computer system 42 for defining the pulse width of the signal A2 is:
The H level pulse width of this signal E3 is set to a predetermined pulse width.

Here, the variation in the delay time and the pulse width of the signal AL3 with respect to the signal A2 depends on the pulse generation period P of the clock signal CLK.
Although determined by T2, the pulse generation period PT2 is a period (1/32 in the above example) that is sufficiently shorter than the fixed time difference τD to be delayed, and thus the variation in the delay time and the pulse width is small. Thus, the constant time difference τ
Compared with the conventional case where a delay signal is generated using a clock signal DLE that generates pulses with the same cycle as D, the variation in the pulse width and pulse generation timing of the finally obtained PWM signals E3 and F3 is also smaller. As a result, the transistors Tr1 and Tr2, which are a pair of controlled elements, are switched and controlled with high accuracy.

In addition, the delay time and pulse width of the signal AL3 vary strictly within the range of the pulse generation period PT2 of the clock signal CLK, and accordingly, the pulse width and pulse generation timing of the PWM signals E3 and F3 also vary within the same range. However, the clock signal CLK is a signal that is supplied to the timer IC 46 and serves as a reference for performing pulse width modulation of the signal A2, and the signal A2 that is the basis of the signal AL3 originally has an error within the range of the pulse generation period PT2. Since they are included, the delay control by the shift register 62 does not impair the accuracy of the pulse width, the pulse generation timing, and the like. Therefore, the accuracy of the pulse width modulation by the timer IC 46 is maintained as it is until the final PWM signals E3 and F3.

As described above, the clock signal CLK output from the clock generator 38 is supplied to the timer IC 46 and the shift register 62.
Therefore, the circuit is simpler and less expensive than when a clock generator for generating a shift signal for defining the shift timing of the shift register 62 is separately provided.

In this embodiment, the clock generators 36 and 38 correspond to a first clock generator and a second clock generator, respectively.
These clock signals T2, CLK are the first clock signal, the second
It corresponds to a clock signal. The clock signal CLK also serves as a shift signal that defines the operation of the shift register 62. The computer system 42 and the timer IC 46 correspond to a pulse width control unit and a reference pulse signal output unit, respectively.
The signal A2 corresponds to a reference pulse signal. Further, the NO
The T circuits 64 and 66 and the AND circuits 68 and 70 correspond to logical operation means.

 Next, another embodiment of the present invention will be described.

In the PWM signal generation circuit 80 of FIG. 3, the shift register 72 outputs the contents stored in the n-th and 2n-th registers, and outputs the signal A2 from the n-th register in the same manner as in the previous embodiment. A signal AL3 delayed by a time difference τD, in other words, n × PT2, is output based on the clock signal CLK, while a signal delayed by 2n × PT2 from the signal A2 from the 2nth register, ie, a signal AL3 The signal AL4 which is further delayed by the time difference τD is the clock signal CLK.
Is output based on HL of the signal AL3
The signal E4 is obtained by inverting the level by the NOT circuit 74, and the signal E4 is obtained by the AND circuit 70 from the signals A2 and AL4. These signals E4 and F4 are H-
The L levels are inverted with each other, and the rising point is delayed by a time difference τD from the falling point of the other signal, and is used as the PWM signals X and X ', respectively. FIG. 4 is an example of the signals of each section in FIG.

Here, since the signals AL3 and AL4 are both output with a certain timing determined by the number of pulses of the clock signal CLK with respect to the signal A2, variations in pulse width and pulse generation timing are small. ,
The same operation and effect as in the above embodiment can be obtained. In this embodiment, the NOT circuit 74 and the AND circuit 76 correspond to logic operation means.

The H level pulse width of the signal E4 is the L level of the signal A2.
The pulse width of the signal A2 is longer than that of the first embodiment by the time difference τD, but is shorter than that of the first embodiment by the time difference τD.
The computer system for defining the pulse width of the signal A2
What is necessary is just to set 42 programs in advance.

As mentioned above, although one Example of this invention was described in detail based on drawing, this invention can be implemented in another aspect.

For example, in the above embodiment, the three-phase brushless DC motor 10
When controlling the rotation speed of the transistor bridge circuit 12
The circuit for generating the PWM signals X and X 'for controlling the switching is described above, but the control circuit for other DC motors or AC motors, or a device other than a motor such as a power transformer, or a control circuit having a controlled element other than a transistor Also, the present invention can be similarly applied.

In the above embodiment, the transistors Tr1 and Tr2 are turned on when the PWM signals X and X 'rise. However, the transistors Tr1 and Tr2 may be turned on when the PWM signals X and X' fall. In that case, the falling point of one PWM signal may be delayed from the rising point of the other PWM signal by a certain time difference τD. For a controlled element whose turn-on time is longer than the turn-off time, it goes without saying that the difference between the rising point and the falling point of the pair of PWM signals must be reversed.

In the above embodiment, the clock signal CLK supplied to the timer IC 46 also serves as the shift signal for the shift registers 62 and 72. However, a clock generator for outputting the shift signal may be provided separately.

In the second embodiment, three signals A2, AL3, and A3
Although PWM signals E4 and F4 are generated from L4, two signals AL3 output from the shift register 72 are output.
And AL4 only, based on only
Different types of PWM signals can be generated. In that case, the delay time from the input of the signal A2 to the shift register 72 to the output of the signal AL3 can be arbitrarily set according to the number of pulses of the clock signal CLK.

Further, the clock signal T2, the pulse generation period PT1,
PT2 can be changed as appropriate within the clock response range of the timer IC 46, and they can be made variable. Note that the set values “n” and “2n” of the shift registers 62 and 72 need to be changed according to the change of the pulse generation period PT2.

Although the clock signals T2 and CLK are supplied to the computer system 42 of the above embodiment, the pulse generation periods PT1 and PT2 and the frequencies thereof may be set.

Although not specifically exemplified, the present invention can be implemented in various modified and improved modes based on the knowledge of those skilled in the art.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a pulse width modulation signal generation circuit according to one embodiment of the present invention. FIG. 2 is a time chart showing an example of a signal of each section in the generation circuit of FIG.
FIG. 3 is a circuit diagram showing another embodiment of the present invention. 4th
FIG. 6 is a time chart showing an example of signals of each section in the embodiment of FIG. FIG. 5 is a diagram schematically illustrating a rotation speed control circuit of a three-phase brushless DC motor in which the pulse width modulation signal generation circuit of FIG. 1 is suitably used. FIG. 6 is a circuit diagram showing an energization switching portion in the control circuit of FIG. FIG. 7 is a diagram showing the relationship between the pulse width modulation signal and the on / off switching of the transistor in the circuit of FIG. FIG. 8 is a circuit diagram showing an example of a conventional pulse width modulation signal generation circuit having an analog element. FIG. 9 and FIG. 10 are time charts showing an example of a signal of each section in the generation circuit of FIG. FIG. 11 is a circuit diagram showing an example of a conventional pulse width modulation signal generation circuit by a computer system. FIG. 12 is a time chart showing an example of a signal of each section in the generation circuit of FIG. 36 clock generator (first clock generator) 38 clock generator (second clock generator) 42 computer system (pulse width control means) 46 timer IC (reference pulse signal output means) 60 , 80… Pulse width modulation signal generation circuit 62,72… Shift register 64,66… NOT circuit 68,70… AND circuit 74… NOT circuit, 76… AND circuit Tr1, Tr2… Transistor Control element) T2 First clock signal CLK Second clock signal (shift signal) A2 Reference pulse signal AL3, AL4 Output signal of shift register E3, F3 Two types of pulse width modulation signal E4 , F4 ... two types of pulse width modulation signals τD ... fixed time difference

Claims (2)

(57) [Claims] 1. A method for generating a pulse at a constant period and using two types of pulse width modulated signals having pulse width modulated pulse waveforms opposite to each other, and turning on and off in accordance with a level change of the pulse width modulated signal. In controlling the switching of a pair of controlled elements to be switched to the opposite state, the pulses giving a fixed time difference between the rising and falling points of the two types of pulse width modulation signals. A width modulation signal generation circuit, comprising: a first clock generator that outputs a first clock signal that generates pulses at the same period as a pulse generation period of the pulse width modulation signal; and a pulse generation period of the first clock signal. A second clock generator for outputting a second clock signal for generating a pulse at a predetermined constant period, which is sufficiently short; Pulse width control means for obtaining the number of pulses of the second clock signal corresponding to the time corresponding to the pulse width to be controlled, and outputting a control signal representing the number of pulses; By generating a pulse in synchronization with the first clock signal and counting the number of pulses of the second clock signal by the number of pulses represented by the control signal,
A reference pulse signal output unit that outputs a reference pulse signal having a pulse width corresponding to the number of pulses of the clock signal; and the reference pulse signal in synchronization with a shift signal that generates pulses at a fixed period sufficiently shorter than the fixed time difference. And a shift register that outputs after elapse of a predetermined number of pulses of the predetermined shift signal corresponding to the predetermined time difference, and the reference pulse signal and the reference pulse signal, Logical operation using the output signal from the shift register delayed by the time difference between the two types of pulse width modulated signals having opposite pulse waveforms and having a fixed time difference between a rising point and a falling point. And a logical operation means for generating and outputting the pulse width modulation signal. 2. The pulse width modulation signal generating circuit according to claim 1, wherein said shift register fetches and stores said reference pulse signal in synchronization with said shift signal and corresponds to said predetermined time difference. A plurality of signals that delay each other by a predetermined number of pulses of the predetermined shift signal to be output at a constant timing determined by the number of pulses of the shift signal with respect to the reference pulse signal, and By performing a logical operation on the logical operation unit using a plurality of output signals output from the shift register, two types of pulse waveforms having opposite pulse waveforms and having a fixed time difference between a rising point and a falling point are provided. A pulse width modulation signal generation circuit for generating and outputting a pulse width modulation signal.