JP2958967B2 - Digital clock - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital clock provided with a power failure detection device.

2. Description of the Related Art In general, a digital clock operating using a commercial frequency as a reference source has a built-in power failure detection device,
In the event of a power outage or interruption of the commercial frequency, the detection circuit is activated, the circuit is switched to operate on an external battery, the internal oscillation circuit is activated, and the clock circuit operates based on the oscillation frequency. It is configured to be able to satisfy the function as a clock even during a power failure.

A clock circuit used for such a general digital clock also has a built-in device for displaying time, and connects an LED as a display device. This satisfies the function as a watch.

Since the display device is built-in, depending on the display circuit, there are a clock circuit that operates using plus as a reference power supply and a clock circuit that operates using minus as a reference power supply.

The detection means of the power failure detection circuit of the clock circuit that operates with the plus as the reference power
Voltage is held. At the time of a power failure or when the commercial frequency is cut off, the input of the power failure detection device must detect a negative voltage.

However, in an LSI that uses a positive power supply as the reference power supply, the power supply unit rectifies the negative side to obtain a DC voltage and supplies it to the clock circuit. In addition, this power supply becomes a plus of the reference power supply, and has a complicated circuit configuration as a power failure detection means.

FIG. 2 shows a conventional digital clock. FIG. 3 shows a main part of the power failure detection device, and FIG. 4 is an explanatory diagram of its operation. In FIG. 3, reference numeral 2 denotes a clock circuit, and 2c denotes an input terminal of the power failure detection device. This terminal 2c is connected to resistors R ₇ and R ₈
Is always set to the voltage of V _SS / 2. That is, the resistance R
₇ is connected to 2a, terminal 2a has V _SS (plus),
R ₈ is connected to 2b, V _DD (minus) is applied to the terminal 2b. Therefore, the 2c terminal is at the voltage of V _SS / 2. Further, the resistors R ₇ and R ₈ use the same value of high resistance of 100 KΩ or more. Terminal 2c is connected to the gate of the transistor Q _2, the terminal
The input mode is determined by the voltage externally applied to 2c. The input mode changes according to the values shown in FIG. When V _SS, that is, H level is applied to the terminal 2c, the test mode is set, and when V _SS / 2 is applied, a normal clock operation is performed. When the V _DD “L” level is further applied, the mode is switched to the power failure detection mode. That is, the input circuit of the terminal 2c makes the determination based on the ternary data.

Referring to FIG. 4, the horizontal axis represents time, and the vertical axis represents voltage. Each input is present detection voltage range, H level is in the range of V _SS -1v from V _SS. 1/2 level is V _SS / ₂ + 1v
To V _SS / 2−1v, the L level is in the range of V _DD to V _DD + 1v. That is, when an external voltage is applied in each voltage range, the mode is switched.

In FIG. 2, the clock circuit 2 of the digital clock operates using (V _SS ) as the reference voltage 6. 1 is an indicator, L
ED is used. Since the driving method of this LED is duplex, half-wave rectified voltages of the diodes D ₁ and D ₂ are applied to 1a and 1b, and the time counted by switching with the output of the clock circuit 2 can be displayed. it can. Further, since the LED of the display 1 is a cathode common, the half-wave rectified voltage in the negative direction is applied to 1a and 1b with reference to ( _VSS ). Therefore, the clock circuit 2, it is necessary to operate on the basis of the V _SS. Furthermore, the resistors R ₁ and R ₂ are connected to the diodes D ₁ and
Which is the load resistance of the D _2.

The diode D ₃ and the capacitor C ₂ are rectifier circuits for driving the clock circuit 2 and the radio receiver 4. diode
D ₅ and capacitor C ₃ are LPFs for preventing clock malfunction due to commercial frequency noise. Diode D ₅ as the commercial frequency of the reference signal source for the clock circuit with a diode D ₃ does not exceed the rated input voltage of the 2d input V _SS, V _DD
It is for restricting each side.

Reference numeral 5 denotes a battery for driving the clock circuit 2 during a power failure. When operating in commercial power is the manner it does not flow a current from the battery by a diode D _7. However, the voltage between V _{SS and} V _DD must be higher than the voltage of the battery. Diode D ₆ is for the way the radio receiver 4 is not operated by a battery.

That time the battery 5 is a power failure, and After voltage drop of the secondary side 10 of the shut when the power transformer 3, is not applied to the radio receiver 4 simultaneously by the diode D ₆ is supplied a voltage via the diode D _7, watches Only the circuit 2 is operated. V _SS is applied to the terminal 2a of the clock circuit 2, and V _DD is applied to the terminal 2b.
Is applied. The secondary side 10 of the power transformer 3 is a clock circuit 2,
The display 1 and the radio receiver 4 are operated. That is, it is composed of one power supply device.

Next, the operation of the power failure detection circuit will be described. Reference numeral 8 denotes a power failure detection circuit, and a diode D ₄ and a capacitor C ₁ are half-wave rectifier circuits for operating the transistor Q ₁ . This DC voltage is turned on current flows to the base of the transistor Q ₁ via the resistor R _3. This means that the collector of the transistor Q ₁ is substantially the same voltage as V _SS. The collector is connected to load resistors R ₄ and R ₅ , and the connection point is connected to the input terminal 2 c of the clock circuit 2 for detecting a power failure. In other words, when the commercial power supply is energized, the resistor 2
The voltage divided by R ₄ and R ₅ is applied, and the clock circuit 2 maintains the normal operation state.

However, the resistance R ₄ and R ₅ must be the same value. As a result, this voltage becomes V _SS / 2.

Next, the operation when no commercial power is applied to the primary side 9 of the power transformer 3, that is, at the time of a power failure or forcible shutoff (when the outlet is unplugged) will be described.

Voltage which has been rectified through the diode D ₄ is,
( _VSS ) reference voltage. This means that the base potential of the transistor Q ₁ is turned to the emitter and the same potential, the transistor Q ₁ is turned off. That thing by now collector open state of the transistor Q _1, a power failure detection input terminal 2c is resistance
It becomes V _DD through R _5. Therefore, the terminal 2c detects the “L” level and enters the power failure mode. On the other hand, the DC voltage rectified by the diode D ₃ also becomes the reference voltage of (V _SS ), the voltage drops below the battery 5, and current flows into the diode D ₇ , and the battery 5 flows into the terminals 2 a and 2 b of the clock circuit 2. Is applied. As a result, the power failure detection device operates, the clock circuit 2 is operated by the external battery 5, and the power failure is compensated.

Problems to be Solved by the Invention However, it is necessary to configure a very complicated circuit as a detection means of a power failure detection circuit of a clock circuit of a digital clock using plus as a reference power supply. For this reason, the number of parts has increased, the material cost has been high in terms of cost, and this has been an obstacle for an apparatus for providing it at low cost.

SUMMARY OF THE INVENTION The present invention provides an inexpensive digital clock in which a complicated power failure detection circuit can be simplified, reliable operation can be guaranteed, and the number of components can be significantly reduced.

Means for Solving the Problems A digital clock according to the present invention comprises: a first power supply device for obtaining a power supply voltage by stepping down and rectifying a commercial power supply with a transformer;
A clock circuit having a power failure detection device that operates at the voltage of the power supply device and has a voltage that is approximately one half of the power supply voltage constantly applied to the input; A battery power supply for supplying a voltage, a second power supply for stepping down and rectifying a commercial power supply with a transformer to obtain a power supply voltage higher than a constantly applied voltage at the input of the power failure detection device, and an anode connected to the input of the power failure detection device And a diode having a cathode connected to the voltage of the second power supply device.

The present invention includes two power supply units, and uses the power supply voltage of the second power supply unit as a power failure detection unit of a clock circuit using plus as a reference power supply, and the first power supply unit rectifies the negative direction. The plus side creates a reference DC voltage. Thereby, the clock circuit is driven based on the plus voltage. This is because a circuit for displaying is built in.

On the other hand, the second power supply device is for operating other circuit loads, and can rectify the plus direction to extract the minus DC voltage. This second power supply is for driving a radio receiver, and is in the form of a digital clock radio as a composite product.

The input of the power failure detection device built in the clock circuit using the commercial frequency as a reference source has three values, and the normal operation mode is set to の of the power supply voltage. This means that two high resistances of the same value are connected in series between the plus and minus of the power supply. Therefore, the connection point of the two equivalent resistance values becomes 1/2 voltage. Only when this input detects minus, it is concluded that a power failure or interruption has occurred.

DC is output as the voltage of the second power supply device in the normal operation state, and the voltage of the second power supply device is higher than the half voltage of the input terminal 2c of the power failure detection device. Focusing on this, by connecting from the input terminal 2c of the power failure detection device to the output terminal of the second power supply device via the diode D9 which is the power failure detection circuit 14, normally, the 1/2 voltage is divided by resistance division. Detected. During a power outage or interruption, the DC voltage of the second power supply becomes negative, a forward current flows through the diode, and the input of the detector drops from 1/2 voltage to the _Vf voltage of the diode. The built-in power failure detection device determines that the voltage is a negative voltage, oscillates the internal oscillation circuit, and operates as a normal clock.

FIG. 1 shows an embodiment according to the present invention. In FIG. 1, the same reference numerals in FIG. 2 indicate the same components. Here, the difference from FIG. 2 is that there are two output windings 10 and 11 on the secondary side of the power transformer 3 to constitute two power supplies, and to detect the power supply voltage of the second power supply, Power failure detection input
This is to add to 2c.

A DC voltage is extracted from the second output winding 11 through a rectifier circuit including a diode D ₈ and a capacitor C ₄ . Furthermore diode D ₈ is in the negative 13 is rectified in the positive direction to the reference. That is, minus 13 of the second output winding 11
Is the same potential as (V _DD ) of the first output winding 10. The DC voltage rectified by the diode D ₈ and the capacitor C ₄ is applied to the radio receiver.

 Next, the operation of the power failure detection circuit of the present invention will be described.

When commercial power is applied to the primary side 9 of the power transformer 3, that is, during normal operation, the power failure detection input terminal 2 c of the clock circuit 2 holds the voltage V _SS / 2. At that time, the voltage of the second output winding 11 is always set to a voltage higher than the V _SS / 2 voltage. The diode D ₉ is connected in the forward direction from the power failure detection input terminal 2 c of the clock circuit 2, and is connected to the positive potential 12 of the second output winding 11. Therefore, during normal operation,
Is the V _SS / 2 voltage, and since the plus voltage of 12 has a higher potential than V _SS / 2, no current flows through the diode D ₉ and the terminal 2 c
_{The SS} / 2 voltage is maintained and the level is determined, and the clock circuit 2 maintains the normal operation state.

Next, the operation at the time of a power failure and at the time of interruption will be described.
When the commercial power is not applied to the primary side 9 of the power transformer 3, the positive voltage 12 of the second output winding 11 becomes the negative potential of the reference 12 of the rectifier circuit. That is, a diode
Cathode side at the same time the potential at the time of power failure and shut drop of D _9, and further lowered from V _SS / 2 voltage becomes the same potential as the (V _DD). Therefore, the cathode of the diode D ₉ becomes current flows out ON state from the time when the lower potential than V _SS / 2, finally becomes almost the same potential as the (V _DD) potentials, the terminal 2c is "L" It is determined to be the level, and the power failure detection mode is set. On the other hand, the potential of the first output winding 10 becomes the reference potential (V _SS ) at the same time as the power failure, and the diode D
Current flows through the terminal ₇ and the voltage of the external battery 5 is applied to the terminals 2a and 2b of the clock circuit 2, and the power supply operates in a normal state even at the time of power failure or interruption, and the power failure is compensated.

The clock circuit 2 has a built-in CR oscillation circuit, and the terminal 2c
Simultaneously detects the “L” level, the CR oscillation circuit operates, and the signal source switches from the commercial frequency to the internal oscillation frequency.

When the power failure detection circuit 14 is configured using the power supply voltage of the second power supply device in this manner, the number of components can be significantly reduced,
Mode switching at power failure is possible.

As described above, the present invention provides a first power supply device that obtains a power supply voltage by stepping down and rectifying a commercial power supply with a transformer, and a power supply that operates at the voltage of the first power supply device and that is approximately half of the power supply voltage. A clock circuit having a power failure detection device in which a voltage of 1 is constantly applied to the input; a battery power supply that supplies a power supply voltage to the clock circuit instead of a power failure of the first power supply device; A second power supply device for obtaining a power supply voltage higher than the constantly applied voltage of the input of the power failure detection device, and a diode having an anode connected to the input of the power failure detection device and a cathode connected to the voltage of the second power supply device. As a result, a power outage can be compensated for when the commercial power supply is interrupted or cut off, the number of components can be greatly reduced, and the power outage detection circuit can be configured with the least number of components.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a digital clock of the present invention, FIG. 2 is a circuit diagram of a conventional digital clock, and FIG.
FIG. 4 is an equivalent circuit diagram of a power failure detection input circuit of the clock circuit used for the digital clock, and FIG. 4 is a diagram showing an input detection range in the power failure detection input circuit on a time axis and a voltage axis. 2. Clock circuit, 3. Power transformer, 4. Radio receiver, 5. External battery, 14. Power failure detection circuit.

Claims (1)

(57) [Claims] A first power supply unit for obtaining a power supply voltage by stepping down and rectifying a commercial power supply with a transformer; and operating at a voltage of the first power supply unit and substantially equal to about 2 of the power supply voltage.
A clock circuit having a power failure detection device in which a one-half voltage is constantly applied to an input; a battery power supply that supplies a power supply voltage to the clock circuit in place of a power failure of the first power supply device; A second power supply device that obtains a power supply voltage higher than the constantly applied voltage at the input of the power failure detection device by stepping down and rectifying the voltage; and an anode connected to the input of the power failure detection device to reduce the power supply voltage of the second power supply device. A digital clock, comprising: a diode connected to a cathode.