JP2958609B2 - Calculator test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing hardware and firmware of a firmware-controlled computer.

[0002]

2. Description of the Related Art FIG. 15 shows a conventional example. When performing a test on an I / O device of a computer, the firmware is first IMPLed, and then the system monitor is IPLed.
Then, each test program is executed under the control of the system monitor. The setting of the address conversion table, the setting of the storage protection mechanism, and other settings (such as interrupt processing) are performed by the system monitor. When testing the CPU (Central Processing Unit), the firmware must be IMP
L, then IPL the simple monitor, and then execute the CPU TP (test program) under the simple monitor control. C
The PU test program prepares a plurality of logical addresses (to be tested), and confirms that the addresses are normally converted and that an expected address conversion exception occurs.
The CPU test program has an address conversion table created in advance as data.

FIG. 16 illustrates a conventional seek address in an IPL loader. X'000 of main memory
The area from address 0 'to 256 bytes is a BOOT storage area, the area from address X'0A00' to 512 bytes is an IPL loader area, and the area from address X'1000 'is a MIPL program area. .

After the IMPL is completed, the firmware is
T (a program for loading the IPL loader into the memory) is loaded at address 0 of the memory and executed (loading the IPL loader onto the memory and passing control). The IPL loader (a program for loading the IPL program into the memory) reads the IPL program from the magnetic disk device in accordance with the size / address described at the relative address 506 in the IPL loader, and reads X 'on the memory.
It loads to address 1000 'and passes control to the IPL program.

[0005] The CPU system TP is an architecture realized by hardware and firmware.
Dynamic address translation mechanism (realizes virtual memory system), memory protection mechanism (prevents the destruction of other programs and data areas when a running program accesses other programs and data areas by mistake), interrupt mechanism (machine , Supervisor, program, input / output), and instructions in the instruction set, etc., to confirm that they operate as specified.

FIG. 17 is a diagram for explaining address conversion. The case where the page size in the dynamic address translation mechanism by referring to the segment table and the page table is 2K page and 16K page will be described.
FIG. 17A is a diagram showing the case of the firmware in the 2K page mode. In the 2K page mode, bits 0 to 15 of the logical address are used as the segment number, bits 16 to 20 are used as the page number, and bits 21 to 31 are used.
Is the displacement in the page. In each entry of the segment table, a page table start address and the like are written. A page address is written in each entry of the page table.

According to the segment number of the logical address,
The contents of the corresponding entry in the segment table are read, and the start address of the page table is obtained. Based on the obtained start address of the page table and the page number of the logical address, the contents of the corresponding entry in the corresponding page table are read to obtain the page address. The sum of the obtained page address and the displacement of the logical address within the page is the real address.

FIG. 17B is a diagram showing the case of firmware in the 16K page mode. In the 16K page mode, bits 0 to 11 of the logical address are used as the segment number, bits 12 to 17 are used as the page number,
Bits 18 to 31 are set as in-page displacement. In each entry of the segment table, a page table head address and the like are written, and in each page table entry, a page address is written. The process of converting a logical address to a real address is the same as in the case of 2K pages.

As described above, in the firmware of the supported page sizes of 2K and 16K, the bit ranges for expressing the segment number and the page number are different (the maximum number of entries in the table is also different). The table is also different. Therefore, C for each
PU-based TP is required.

The system monitor controls a test program for diagnosing each device (such as an I / O device) by using the above functions guaranteed by the CPU system TP (assuming that it operates normally). An environment is created (the purpose is to indirectly diagnose the above functions by operating the system normally).

The simple monitor executes the CPU system TP (diagnoses the above functions) without using the above functions in order to diagnose the above functions (loading). / Start, etc.) (the TP cannot diagnose that part if the monitor is using it).

Therefore, in the system monitor, the CPU T
P cannot be executed (partially possible), and a simple monitor cannot create an environment for controlling a test program for diagnosing each device.

The conventional CPU system TP includes one that operates under control of a system monitor (mainly loading from a magnetic disk device) and one that operates under control of a simple monitor (loading from a floppy disk device). Each monitor is independent. Further, there is no method for diagnosing a plurality of firmwares having different operating environments of the program.

[0014]

In the prior art, the CPU system TP operating on the system monitor cannot make a diagnosis that destroys the operating environment and resources of the monitor program. Diagnosis CPU TP
Must be operated on a simple monitor.

However, since the simple monitor has only a minimum function for operating the CPU system TP, an operator's operation is necessary, and since the capacity of the floppy disk is small, a plurality of CPU systems TP are required. Could not run continuously. Further, when diagnosing a plurality of firmware, it is necessary to switch the firmware and perform the IMPL again. SUMMARY OF THE INVENTION It is an object of the present invention to perform diagnostics by switching a plurality of firmwares without lowering the diagnostic level of the CPU TP, thereby enabling an automatic test.

[0016]

According to a first aspect of the present invention, there is provided a computer test method comprising: a firmware specification information area for storing firmware specification information for specifying firmware to be IMPLed; and a content of the firmware specification information area. I to load firmware
MPL execution means, an IPL information area for storing information indicating a position and a size on an external storage device in which a simple monitor or a system monitor is stored, and an IPL information area which is started after the IMPL is completed, and is executed according to the contents of the IPL information area. An IPL executing means for transferring a control by loading a simple monitor or a system monitor, a main memory, a central processing unit,
A firmware-controlled computer test method comprising: an execution table in which a CPU-based test program name is written; an execution information flag indicating whether to execute the CPU-based test program; and an execution information flag turned on. An execution table creation program for writing the CPU test program name designated by the operator in the execution table; a plurality of firmware; a plurality of CPU test programs corresponding to each firmware; A system monitor for monitoring and control, and an I / O so that the system monitor is IPLed when the execution information flag is off.
Update the contents of the PL information area, start the IPL execution means,
If the execution information flag is on, the CP corresponding to the CPU-based test program name written in the execution table
Load U system test program and pass control,
After the CPU-based test program ends, it is checked whether or not the next-executed CPU-based test program exists.
If the PU test program exists, the contents of the firmware specification information area are updated so as to specify the firmware corresponding to the CPU test program of the next execution, the IMPL execution means is started, and the CPU test of the next execution is executed. When there is no program, the execution information flag is turned off and the IP is set so that the system monitor is loaded.
The contents of the L information area are updated, a simple monitor for activating the IMPL execution means is stored in an external storage device in advance, the firmware is IMPLed, and the IMON of the simple monitor is executed.
PL, performs IPL of the system monitor, executes the execution table creation program under the control of the system monitor, performs IMPL of the firmware, performs IPL of the simple monitor, and controls the simple monitor A series of processes for executing the CPU test program under
(N = 1, 2,...), After the processing of, the IMPL of the firmware is performed, the IPL of the simple monitor is performed, the IPL of the system monitor is performed, and other than the central processing unit under the control of the system monitor. And executing a test program for testing the device.

A computer test method according to a second aspect of the present invention is the computer test method according to the first aspect, wherein the simple monitor comprises a CP.
When an error is detected during the execution of a U-system test program, the system has a function of turning on the error information flag and writing the error information to the error information area. The system monitor checks whether the error information flag is on and turns it on. In the case of (1), it has a function of outputting error information.

[0018]

FIG. 1 is a diagram for explaining the outline of the present invention. In the figure, 1 is a central processing unit, 2 is a main memory,
Reference numeral 3 denotes an I / O device, 4 denotes an operation panel, and 5 denotes a magnetic disk device.

In the disk volume of the magnetic disk device 5, BOOT, SSW (System Status Word),
IPL loader, simple monitor, IPL program, system monitor, CPU TP execution program, multiple firmware, multiple test programs, firmware information storage member, TP execution information flag, CPU TP execution table, error information storage area, etc. Exists.

The BOOT is for loading an IPL loader. The SSW contains information for specifying firmware to be IMPLed. The IPL loader has an IPL information area for storing a seek address and a size of a program to be loaded.
The simple monitor or the IPL program is loaded according to the value of the PL information area.

The simple monitor is loaded when the CPU system TP is executed. The IPL program is for loading a system monitor. CP
Tests other than the U-system test are performed under the control of the system monitor. The system monitor is loaded during normal operation. The CPU-based TP execution program is CP
This is for creating a U-system TP execution table.

For example, firmware 1 is for a 2K page dynamic address translation mechanism, and firmware 2 is for a 16K page dynamic address translation mechanism. The test program 1 is a CPU TP for testing the firmware 1 and the hardware, and the test program 2 is a CPU TP for testing the firmware 2 and the hardware.

The firmware information storage member has a head seek address of a plurality of firmware, a support page size of each firmware, a size of each firmware, and the like.

The TP execution information flag has a bit indicating whether or not to execute the CPU TP. CPU system TP
The names of the CPU TPs to be executed are written in the execution table in order. In the error information storage area,
Error information indicating details of an error detected during execution of the CPU TP is stored.

The operation of the system shown in FIG. 1 will be briefly described.
First, an IMPL loader (not shown) operates to read the SSW on the disk volume. The IMPL loader IMPLs the firmware specified by the SSW. BOOT by firmware control after IMPL
Is loaded, and control is passed to the BOOT. BO
The OT loads the IPL loader.

The IPL loader loads the simple monitor when the value of the IPL information area indicates the simple monitor, and passes the control. When the value of the IPL information area indicates the IPL program, the IPL loader transfers the control. Load the program and pass control. At the initial stage, the size and seek address of the simple monitor are written in the IPL information area.

In the simple monitor, the TP execution information flag is set to CP
If the execution of the U system TP is instructed, the CPU system TP
The CPU system TP registered in the execution table is loaded and control is passed, and the TP execution information flag is
When the execution of P is not instructed, the IPL loader I
The contents of the PL information area are rewritten to the seek address / size of the IPL program, and control is passed to the IPL loader. In addition, when the execution of the CPU TP is completed, the simple monitor
Next, the firmware corresponding to the CPU TP to be executed is obtained by referring to the contents of the firmware information storage member, and the firmware designation information in the SSW is rewritten.
Start the IMPL loader.

The CPU TP execution program operates under the control of the system monitor. When the operator instructs the execution of the CPU TP execution program from the operation panel 4, the CPU TP execution program is loaded,
Is activated. The CPU TP execution program changes the TP execution information flag to a value for executing the CPU TP,
A display screen for creating a U-system TP execution table is displayed on the screen of the operation panel 4. When the operator inputs the name of the CPU TP to be executed and presses the execution key, the name of the CPU TP is registered in the CPU TP execution table.

FIG. 2 is a diagram for explaining the change of the seek address in the IPL loader according to the present invention. After the completion of the IMPL, the firmware loads the BOOT (a program for loading the IPL loader on the memory) to address 0 on the memory and executes it (loads the IPL loader on the memory and passes control).

An area of 6 bytes from the relative address 506 in the IPL loader is an IPL information area. The IPL loader (a program for loading the MIPL or MCPUMON program into the memory) executes an MCPUMON program (synonymous with a simple monitor) according to the size / address described in the relative address 506 in the IPL loader in X'1000 'on the memory. Load at address and pass control.

Simple monitor (MCPUMON program)
Means that the TP execution flag of the information member in the disk is CPU
Check whether or not the execution of the system TP is instructed.
If the execution of P is instructed, the process is continued,
If the execution of the CPU TP is not instructed, the size / address of the MIPL program (IPL program for IPL for the system monitor) on the memory (6 bytes from address 500 in the IPL loader relative address) is set to IPL.
Copy from the address 506 of the relative address in the loader to 6 bytes, and transfer control to the IPL loader again. The IPL loader is
In accordance with the size / address described at the relative address 506 in the IPL loader, the MIPL program is loaded to the address X'1000 'on the memory, and the control is passed.

FIG. 3 is a view for explaining the address / size of the firmware in the SSW. The zero sector of the disk volume has a structure as shown in FIG.
In the area from the beginning of sector 0 to the 63-byte position, BO
The OT is stored, and the SSW is stored in the area from the 102 (70 in hexadecimal) byte position to the 159 byte position.

FIG. 3B is a diagram showing the configuration of the SSW.
23 from 16 (10 in hexadecimal) byte position of SSW
The area up to the byte position is a firm area. The firmware area stores the physical machine number of the external storage device in which the firmware is stored, the size of the firmware, and the starting physical address of the area in which the firmware is stored. Regions other than the firmware region in the SSW are not relevant to the present invention, and thus description thereof is omitted. The firmware area is rewritten by the simple monitor.

The IMPL is executed according to the information of the fixed area (0 sector) of the disk volume. Firmware information (firmware address / size, support page) can be known from a firmware information storage member (MSYSEVL member) described later. If the contents of the firmware area of the SSW are changed and re-IMPL is performed, the support page can be started with different firmware.

FIG. 4 shows a firmware information storage member (MSY).
FIG. 3 is a diagram showing a configuration example of a SEVL member). In the example shown,
Start seek address of firmware entity 0, start seek address of firmware entity 1, start seek address of firmware entity 2, start seek address of firmware entity 3, support page size 0, support page・ Size 1, support page size 2,
Support page size 3, firmware 0 size, firmware 1 size, firmware 2 size, and firmware 3 size are stored. The other data is not relevant to the present invention, and thus the description is omitted.

FIG. 5 is a diagram showing a configuration example of an information member in a disk. The information members in the disk are
Called NF member. FIG. 6 shows the configuration of the TP execution information flag. The TP execution information flag has a size of one byte. Bit 0 indicates whether or not to execute the TP specified in the CPU-based TP execution table. 0 indicates no execution and 1 indicates execution. Bit 1 indicates whether or not there is error information. 0 indicates no error information and 1 indicates error information. Bit 6 indicates whether the 16K page test has been completed (whether to execute or not)
0 indicates no end (execute) and 1 indicates end (no execution). Bit 7 indicates whether or not the 2K page test has been completed (whether to execute or not). 0 indicates that the test has not been completed (executed), and 1 indicates that it has been completed (not executed).

The execution progress message display flag is a flag indicating whether or not a message indicating the execution progress is displayed on the operation panel. When the execution progress message display flag is on, a message indicating which CPU TP is currently being executed is displayed on the operation panel.

The CPU TP execution table (member) name designates a CPU TP execution table. CPU system T
The P execution table is created as one member and SY
It exists in a file called SCPU.

The structure of the CPU TP execution table is shown in FIG.
Is shown in The CPU TP execution table includes an execution table determination flag (TBLFLG), a 2K page test entry number (ETNUM2K), and a 16K page test entry number.
(ETNUM16K) and a plurality of test program names (TPNAME).

The execution table determination flag (TBLFLG) has a size of 8 bytes, and indicates whether or not the member stored in the SYSCPU file is a CPU system TP execution table. In the case of the CPU system TP execution table, a character string “CPUTABLE” is written in the area of the execution table determination flag (TBLFLG).

The number of 2K page test entries (ETNUM2
K) indicates how many names of the CPU TP for testing the dynamic address translation mechanism of the 2K page are registered in the CPU TP execution table. 16K page test
The number of entries (ETNUM16K) indicates that the name of the CPU TP for testing the dynamic address translation mechanism of 16K pages is the CPU T
Indicates how many are registered in the P execution table.

In the area of the test program name (TPNAME),
The member name of the CPU test program to be executed is stored. Always starts with a 2K page test entry (row). The case of starting from the 16K page test entry is when there is no 2K page test entry (the number of 2K page entries is 0).

The CPU system TP execution table (FIG. 7) is resident until the simple monitor reads the data into the memory and performs the IMPL again. The simple monitor loads the members of the test program name (8 bytes) stored after the address 12 in the CPU TP execution table one by one in order.
Execute. When the execution of one test program is completed, the count is counted in the data area (2 bytes) held by the simple monitor itself (the initial state is 0, and is incremented by 1 every time the TP ends).

The processing of the CPU TP execution program will be described. The CPU TP execution program stores the CPU TP execution table member name input from the operator in the 8-byte area from the 4-byte memory in FIG.
From the 0th byte, the 0 bit of the TP execution information flag (details in FIG. 6) is turned ON. Next, a system reset instruction is executed. When the system reset instruction is executed, the IMPL is executed, and then control is passed to the simple monitor.

The error information storage area in the information member in the disk shown in FIG. 5 stores error information passed between the simple monitor and the MIPL program (IPL program for IPL of the system monitor).

When a program operating under the control of the system monitor detects an error, an error can be output to a display, a disk, a printer or the like as an automatic test measure. Since the simple monitor has only a minimum function of operating the CPU TP, the error output is only the display, and the output contents are different.

According to the present invention, when the CPU TP operating under the simple monitor control detects an error, the error is temporarily stored in the error information storage area in the information member (MCPUINF) in the disk, and the simple monitor is used by the system monitor. Before performing the IPL, the format is changed to error information to be displayed under the control of the system monitor, and the information is transferred to the system monitor. The system monitor outputs an error after the end of the IPL.

FIGS. 8 to 11 are diagrams showing details of the initial processing. These processes are performed by a simple monitor. In step S1, the BOOT (256 bytes from address 0 on the memory) is saved. In step S2, TE
The head address of the AMS entity (IPL loader) and the IPL device address are saved.

In step S3, an ISF (Integrated Se
Stop CPU monitoring from rvic Facility). The ISF has a non-volatile memory, in which information necessary for the computer is stored. In step S4, system information is obtained. This process is MCD
Performed by instruction. The system information means the current support page size of the firmware and the like.

In step S5, the IPL device sets the DISK
Or FPD. Step S for DISK
Proceed to 6. In step S6, BOOT and SSW are read, and MSYSEVL is read.

In step S7, it is determined from the extended system information in the ISF whether or not to execute the CPU TP. If not executed (MIPL activation), step S
Then, the process proceeds to step S13. In step S8, R0 is cleared to zero.

In step S9, the data (X'A0
The seek address of the simple monitor in the IPL loader (address 0 ') is rewritten to the seek address of MIPL. In step S10, the saved BOOT is restored. In step S11, the process branches to an IPL loader (address X'A00 '). In step S12, MIPL is executed.

In step S13, it is determined whether or not to execute a test using a flag in MCPUINF. If not, the process proceeds to step S14. If the process is to be executed, the process proceeds to step S16. In step S14, MCPUINF
It is determined whether or not there is error information based on the flag in. If no, go to step S8; if yes, go to step S8.
Proceed to 15. In step S15, the error information in MCPUINF is loaded into the memory, and the total size is set in R0. Next, the process proceeds to step S9.

In the step S16, (X'1
0 'to X'2F') are set. In step S17, the memory (X'68 'to X
The save area address in the conversion exception information save data of '6F') is set by the real address. The processing in steps S16 and S17 is processing for creating an operation environment of the simple monitor. In step S18, the support page size of the current firmware is determined by the MCD instruction. In the case of 2K, the process proceeds to step S19, and in the case of 16K, the process proceeds to step S24.

In step S19, it is determined whether or not the 2K page test end flag in MCPUINF is ON.
If it is ON, the process proceeds to step S22, and if it is OFF, the process proceeds to step S20. In step S20, the MCPI
The member of the table name stored in the NF is loaded, and a 2K page test is executed according to the contents.
If there is no error, the process proceeds to step S21, and if there is an error, the process proceeds to step S29.

In step S21, the 2K page test end flag in MCPUINF is turned on. Step S2
In step 2, it is determined whether the 16K page test end flag in MCPUINF is ON. Step S if ON
The process advances to step S30, and if it is OFF, the process advances to step S23. In step S23, the address / size of the 16K firmware is set in the SSW. Next, the IMPL is performed again.

In step S24, it is determined whether the 16K page test end flag in MCPUINF is ON. If it is ON, the process proceeds to step S27, and if it is OFF, the process proceeds to step S25. In step S25, the MCP
The table name members stored in UINF are loaded, and a test of 16K pages is executed according to the contents. If there is no error, the process proceeds to step S26, and if there is an error, the process proceeds to step S29.

In step S26, the 16K page test end flag in MCPUINF is turned on. Step S
At 27, it is determined whether the 2K page test end flag in MCPUINF is ON. Step S if ON
The process proceeds to step S30, and if it is OFF, the process proceeds to step S28. In step S28, the address of the 2K firmware /
Set the size. Next, the IMPL is performed again.

In step S29, error information is stored in MCPUINF, the error information flag is turned on, and 2K
Turn on the / 16K test end flag. Step S30
Then, the TP execution flag in MCPUINF is turned off. Then, the firmware (M
The address / size of the firmware (SYSEVENTL) is set, and then the IMPL is performed again.

FIG. 12 is a diagram for explaining an operation example of the present invention. This operation example is based on the condition that only one CPU TP name is registered in the CPU TP execution table. In the present invention, the size / address in the IPL loader stored in the disk volume in advance is changed to that of the simple monitor, and the IPL of the simple monitor is performed after the completion of the IMPL of the firmware. The simple monitor is an information member (MCPUINF) stored on the disk.
Of the TP execution information flag (this value is initially set to 0), and executes the IPL of the system monitor without executing the CPU TP.

After the end of the IPL of the system monitor, the test program for each device becomes operable. At this time, the operator starts the CPU-based TP execution program, and stores the contents of the information member (MCPUINF) in the disk into the CPU.
Change to execute system TP. After changing the information member (MCPUINF) in the disk,
Perform MPL.

After the completion of the firmware IMPL, the simple monitor displays the CPU member T of the information member (MCPUINF) in the disk.
The CPU TP is executed in accordance with the contents of the CPU TP execution table specified by the P execution table name. After the test is completed, the value of the TP execution information flag of the information member (MCPUINF) in the disk is IPLed by the system monitor. And perform IMPL of the firmware again.

After completion of the firmware IMPL, the simple monitor refers to the value of the TP execution information flag of the information member (MCPUINF) in the disk, executes the IPL of the system monitor without executing the CPU TP, and executes the system monitor IPL. A test program for each device is executed under the control of the monitor.

FIGS. 13 and 14 are diagrams for explaining another operation example of the present invention. This operation example is based on the condition that a plurality of CPU TP names are registered in the CPU TP execution table. When diagnosing a plurality of firmwares having different operating environments of the program, the firmware 1
The CPU system TP for diagnosing the firmware 1 must be operated when L is activated (the CPU system TP for diagnosing the firmware 2 cannot operate), and the CPU system TP for diagnosing the firmware 2 is operated when the firmware 2 is IMPLed. (The CPU TP for diagnosing the firmware 1 cannot operate). For example, firmware 1 is firmware for performing dynamic address translation in 2K page mode, and firmware 2 is firmware for performing dynamic address translation in 16K page mode.

For this reason, the simple monitor refers to the value of the TP execution information flag of the information member (MCPUINF) in the disk and executes the CPU TP or the IP of the system monitor.
Perform L. After executing the CPU TP for diagnosing the firmware 1, the simple monitor rewrites the address / size of the firmware 1 written at a fixed address (sector 0) in the disk to that of the firmware 2 and performs the IMPL again. After the execution of the CPU TP for diagnosing the firmware 2, the address / size of the firmware 2 written at a fixed address in the disk is rewritten to that of the firmware 1, and the IMPL is performed again.

[0066]

As is clear from the above description, according to the present invention, a plurality of firmware can be diagnosed without lowering the diagnostic level of a test program for diagnosing a CPU, and a plurality of CPU TPs can be diagnosed. Can be continuously executed, and the manual operation of the operator is not required, so that there is an effect that the number of test steps can be reduced by the automatic test.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an outline of the present invention.

FIG. 2 is a diagram for explaining a change of a seek address in an IPL loader according to the present invention.

FIG. 3 is a diagram for explaining addresses / sizes of firmware in an SSW.

FIG. 4 is a diagram illustrating a configuration example of a firmware information storage member.

FIG. 5 is a diagram showing a configuration example of an information member in a disc.

FIG. 6 is a diagram illustrating a configuration example of a TP execution information flag.

FIG. 7 is a diagram illustrating a configuration example of a CPU TP execution table.

FIG. 8 is a diagram illustrating details of an initial process (1).

FIG. 9 is a diagram illustrating details of an initial process (part 2);

FIG. 10 is a diagram illustrating details of an initial process (part 3).

FIG. 11 is a diagram illustrating details of an initial process (part 4).

FIG. 12 is a diagram for explaining an operation example of the present invention.

FIG. 13 is a diagram for explaining another operation example of the present invention.

FIG. 14 is a diagram illustrating another operation example (continued) of the present invention.

FIG. 15 is a diagram illustrating a conventional example.

FIG. 16 is a diagram showing a seek address in a conventional IPL loader.

FIG. 17 is a diagram illustrating address conversion.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Central processing unit 2 Main memory 3 I / O device 4 Operation panel 5 Magnetic disk device

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 11/22 G06F 9/06

Claims (2)

(57) [Claims] 1. A firmware specification information area for storing firmware specification information for specifying firmware to be IMPL, IMPL execution means for loading firmware specified by the content of the firmware specification information area, and a simple monitor or a system monitor. An IPL information area for storing the information indicating the stored position and size on the external storage device; and a control which is started after the IMPL is completed and is loaded by loading a simple monitor or a system monitor according to the contents of the IPL information area. A test method for a firmware-controlled computer comprising: an IPL executing means to be passed; a main memory; and a central processing unit, wherein: an execution table in which a CPU test program name is written; and whether or not to execute the CPU test program Execution information flag An execution table creation program for turning on the execution information flag and writing the CPU test program name specified by the operator in the execution table; a plurality of firmware; and a plurality of CPU test programs corresponding to each firmware A system monitor for monitoring and controlling the system during normal operation; and, when the execution information flag is off, update the contents of the IPL information area so that the system monitor is IPLed.
If the execution information flag is on, the CPU execution program is loaded with the CPU test program corresponding to the name of the CPU test program entered in the execution table, and control is passed to the L execution means. Thereafter, it is checked whether or not the next execution CPU test program exists. If the next execution CPU test program exists, the firmware designation information is specified so as to designate the firmware corresponding to the next execution CPU test program. Update the contents of the area, activate the IMPL execution means,
When there is no CPU test program to be executed next, the execution information flag is turned off, the contents of the IPL information area are updated so that the system monitor is loaded, and the IMPL is updated.
A simple monitor for starting the execution means is stored in an external storage device in advance, and the firmware is IMPLed.
PL, perform IPL of the system monitor, execute the execution table creation program under the control of the system monitor, perform IMPL of the firmware, perform IPL of the simple monitor, and control the simple monitor A series of processes for executing the CPU test program under
(N = 1, 2,...), After the processing of, the IMPL of the firmware is performed, the IPL of the simple monitor is performed, the IPL of the system monitor is performed, and other than the central processing unit under the control of the system monitor. A method for testing a firmware-controlled computer system, which executes a test program for testing a device. 2. The simple monitor has a function of turning on an error information flag when an error is detected during execution of a CPU-based test program, and writing error information to an error information area. 2. The computer test method according to claim 1, further comprising a function of checking whether or not the computer is on and outputting error information when the computer is on.