JP2953707B2 - Descramble pulse detector - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a descrambling pulse detector for descrambling a scrambled video signal using a synchronization signal compression method used in a pay cable TV. It is.

2. Description of the Related Art In a pay cable TV, as shown in FIG. 4 (a), a synchronizing signal of a video signal is compressed (this is called scrambling), and the compressed synchronizing signal is reproduced correctly (this is descrambled). Therefore, the voice carrier is modulated by the descrambling pulse in the period of the synchronization signal.
The modulated signal is transmitted as shown in FIG. Therefore, in order to descramble in a CATV receiver, this voice carrier is demodulated by AM and a descrambling pulse is detected as shown in FIG. 4 (c), and a rectangular pulse is formed at about 50% of the peak value of the descrambling pulse. A pulse generated as shown in FIG. 4 (d), from which the rising point of the pulse is delayed to the position of the synchronization signal and the pulse width is adjusted to the width of the synchronization signal as shown in FIG. 4 (e). Is generated, and the gain of the portion of the synchronizing signal is increased by this pulse.
The synchronization signal is reproduced as shown in FIG.

Conventionally, this type of descramble pulse detector has a configuration as shown in FIG. In FIG. 3, 2 is a video intermediate frequency amplification circuit, 8 is a video detection circuit, and 10 is 4.5 MHz.
Bandpass filter, 16 is a 4.5MHz audio intermediate frequency amplifier circuit, 11 is an AM detection circuit that detects a descramble pulse from the 4.5MHz audio intermediate frequency signal, 12 is a comparator, 13 is the position of the synchronization signal and the width of the synchronization signal. This is a pulse width adjuster that generates a combined pulse. Reference numeral 17 denotes an amplitude limiting circuit which amplifies the video intermediate frequency signal by limiting its amplitude, and inputs the amplified signal to the video detection circuit 8. An average value AGC circuit 18 controls the gain of the video intermediate frequency amplification circuit 2 based on the video signal voltage.

The video intermediate frequency signal input from the tuner 1 is amplified by the video intermediate frequency amplification circuit 2 and divided into two, one of which is input to the video detection circuit 8, and the other is amplified by the amplitude limiting circuit 17 to be amplified by the video detection circuit 8. Is input to These two signals are multiplied by a video detection circuit 8 to detect a video signal and a 4.5 MHz audio intermediate frequency signal. Then, only the 4.5 MHz audio intermediate frequency signal is extracted by the 4.5 MHz hand pass filter 10, amplified by the 4.5 MHz audio intermediate frequency amplification circuit 16, the descramble pulse is detected by the AM detection circuit 11, and the comparator 12
Then, a rectangular pulse is generated at a point 50% of the peak value of the descramble pulse. The pulse width adjusting unit 13 adjusts the delay of the pulse for a certain period of time and the pulse width to generate a pulse in accordance with the position of the synchronization signal, and increases the gain of only the synchronization signal portion by the synchronization signal reproducing circuit 14, Synchronous signal is being reproduced.

The video signal 19 output from the video detection circuit 8 is input to the average value AGC circuit 18, and the voltage output based on the average value of the video signal voltage causes the video intermediate frequency amplification circuit 2
Is controlling the gain.

In such a conventional configuration, as shown in FIG. 5 (a), when the image modulation degree becomes over-modulated by about 95% or more, the output of the amplitude limiting amplifier circuit 17 is changed to that shown in FIG. As shown in (b), the amplitude limit voltage is not reached in the overmodulation part, and an amplitude distortion occurs. This signal is multiplied by the intermediate frequency signal of the audio carrier of FIG. Then, the output 4.5 MHz audio intermediate frequency signal is also distorted as shown in FIG. Therefore, the descramble pulse is compressed as shown in FIG. 5 (e) due to distortion and is buried in the signal, so that the output of the comparator 12 becomes as shown in FIG. However, there is a problem that the gain of other parts increases, and it becomes impossible to descramble correctly.

Further, since the synchronizing signal of the video signal 19 output from the video detection circuit 8 is compressed, the average value AGC circuit 18 is used. As a result, the output voltage of the average value AGC circuit 18 fluctuates, the gain of the video intermediate frequency amplifying circuit 2 fluctuates, and the video detection circuit 8 simultaneously detects the video signal and the audio intermediate frequency signal. ), A signal in which the two signals are superimposed is output, so that the output dynamic range of the video detection circuit 8 exceeds the output dynamic range due to the fluctuation of the gain of the video intermediate frequency amplification circuit 2, and the descramble pulse is generated. There was also a problem that it became distorted and could not be correctly descrambled.

The present invention solves such a problem. Even if the image modulation degree becomes overmodulation of 95% or more, or if the image modulation degree changes due to a change in the content of the image, the descrambling pulse is generated. It is an object of the present invention to provide a descrambling pulse detection device capable of detecting correctly.

Means for Solving the Problems In order to solve the above-mentioned conventional problems, a descrambling pulse detection device of the present invention has a video intermediate frequency amplification circuit connected to a television signal input terminal and a video intermediate frequency amplification circuit connected to the video intermediate frequency amplification circuit. A video detection circuit including a 4.5 MHz audio intermediate frequency detection circuit, a phase comparison circuit, and a gain control terminal; and a voltage-controlled oscillation circuit connected to the phase comparator. One is connected to the video intermediate frequency carrier input terminal of the 4.5 MHz audio intermediate frequency detection circuit and the video intermediate frequency carrier input terminal of the phase comparison circuit via the first and second phase shift circuits having Connected to the video intermediate frequency carrier input terminal of the video detection circuit, the output of the video detection circuit
This is input to the gain control terminal of the video intermediate frequency amplification circuit via the AGC circuit.

Operation With the above configuration, even if the image modulation degree is over-modulated, the 4.5 MHz audio intermediate frequency detection circuit does not distort the 4.5 MHz audio intermediate frequency signal by the undistorted video intermediate frequency carrier generated by the voltage controlled oscillation circuit. It can be detected. Also, 4.5MHz
It is possible to operate the head value AGC circuit by reproducing the synchronization signal by applying the synchronization signal period pulse to the gain control terminal of the video detection circuit and separating the audio intermediate frequency detection circuit from the video detection circuit independently of the video detection circuit. Therefore, the gain of the video intermediate frequency amplifier can be stabilized even when the video modulation degree changes, and a 4.5 MHz audio intermediate frequency signal without fluctuation can be obtained. Also, when detecting the 4.5 MHz audio intermediate frequency signal, the phase of the video intermediate frequency signal and the video intermediate frequency carrier is set to 90 °, so that only the 4.5 MHz audio intermediate frequency signal is detected without detecting the video signal. Therefore, the influence of the video signal on the 4.5 MHz audio intermediate frequency signal can be eliminated. By these things, distortion-free 4.5MHz
Since an audio intermediate frequency can be obtained, a stable descrambling pulse can be generated.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a descramble pulse detection circuit according to one embodiment of the present invention. In FIG. 1, 2 is a video intermediate frequency amplifier circuit, 3 is a phase comparison circuit, 4 is a 4.5 MHz audio intermediate frequency detection circuit, 5 is a + 45 ° phase shifter, 6 is a voltage controlled oscillator, and 7 is a −45 ° shifter. A phase detector, 8 is a video detection circuit, 9 is a leading value AGC circuit, 20 is a low-pass filter, and the output of the video intermediate frequency amplification circuit 2 is a phase comparison circuit 3, a 4.5 MHz audio intermediate frequency detection circuit 4, a video detection circuit 8 And a voltage-controlled oscillation circuit 6 connected to the phase comparison circuit 3 via a low-pass filter 20 to generate a video intermediate frequency carrier without distortion. The closed loop of the phase comparison circuit 3, the low-pass filter 20, the voltage controlled oscillation circuit, and the + 45 ° phase shifter 5 constitutes a PLL circuit, and the output of the + 45 ° phase shifter 5 is the intermediate image of the 4.5 MHz audio intermediate frequency detection circuit 4. Input to the frequency carrier input terminal. The distortion-free video intermediate frequency carrier generated by the voltage controlled oscillation circuit 6 is input to the video intermediate frequency carrier input terminal of the video detection circuit 8 via the -45 ° phase shifter 7. 4.5M
The 4.5 MHz audio intermediate frequency signal output from the Hz audio intermediate frequency detection circuit 4 is input to an AM detection circuit 11 through a 4.5 MHz band pass filter 10, and a descrambling pulse is detected by a comparator 12 and a pulse width adjuster 13. A pulse corresponding to the width of the synchronization signal is generated at the position of the synchronization signal. The output of the pulse width adjuster 13 is applied to the gain control terminal of the video detection circuit 8, and the video detection circuit 8
Is applied to the gain control terminal of the video intermediate frequency amplification circuit 2 via the leading value AGC circuit 9.

The video intermediate frequency signal as shown in FIG. 2A input from the tuner 1 is amplified by the video intermediate frequency amplifying circuit 2 and divided into three, and each of the phase comparison circuit 3 as a first multiplier and The signal is input to a 4.5 MHz audio intermediate frequency detection circuit 4 as a multiplier of 2 and a video detection circuit 8 as a third multiplier. The closed loop of the phase comparator 3, the low-pass filter 20, the voltage controlled oscillator 6, and the + 45 ° phase shifter 5 constitutes a PLL circuit, and the phase comparator 3 is a multiplier.
Assuming that the phase of the video intermediate frequency signal input from the video intermediate frequency amplification circuit 2 is 0 °, the PLL is locked when the output of the + 45 ° phase shifter is either 90 ° or −90 °. further,
The 4.5 MHz audio intermediate frequency detection circuit 4 is also formed of a multiplier, and the phase difference between the input video intermediate frequency signal and the output of the + 45 ° phase shifter 5 is 90 ° or −90 °. Components are not detected. Accordingly, of the video intermediate frequency signal and the audio intermediate frequency signal input to the 4.5 MHz audio intermediate frequency detection circuit 4, the audio intermediate frequency signal as shown in FIG. 2 (c) and the video as shown in FIG. The intermediate frequency carrier is converted by multiplication into a 4.5 MHz audio intermediate signal, which is the difference between the two, and the video component is output without detection as shown in FIG. 2 (d).

4.5MHz output from 4.5MHz audio intermediate frequency detection circuit 4
The audio intermediate frequency passes through a 4.5 MHz bandpass filter 10 and is AM
The signal is detected by the detection circuit 11, and a descrambling pulse as shown in FIG. 2 (e) is obtained. From the descramble pulse, the comparator 12 generates a rectangular pulse as shown in FIG. 2 (f), and the pulse width adjuster 13 adjusts the delay and pulse width of the rectangular pulse for a fixed time to adjust the position of the synchronization signal. A synchronized pulse is generated, and the gain of only the synchronous signal portion is increased by the synchronous signal reproducing circuit 14 to reproduce the synchronous signal.

The 4.5 MHz band-pass filter 10 outputs a high-frequency component of the video signal from the 4.5 MHz audio intermediate frequency detection circuit 4 because the video intermediate frequency signal is in the residual sideband. Since a beat component between the tuner 1 and the video intermediate frequency is output, it is inserted to prevent such a component. Therefore, it can be deleted depending on the condition of the input signal from the tuner 1 or the like.

The phase of the output of the + 45 ° phase shifter 5 is 90 ° or −90.
Therefore, the phase of the output of the voltage controlled oscillation circuit 6 becomes 45 ° or −135 °, and the phase of the output of the −45 ° phase shifter 7 becomes 0 ° or −180 °. Therefore, the video detection circuit 8 composed of a multiplier performs AM detection on the video intermediate frequency and outputs a video signal. The video detection circuit 8 is provided with a gain control terminal. By applying the output from the pulse width adjuster 13 to this terminal, the gain of the video detection circuit 8 can be increased to reproduce the synchronization signal. . Thereby, the leading value AGC circuit 9 is operated, and the gain of the video intermediate frequency amplifier circuit 2 can be controlled by the leading value of the synchronization signal.

It is needless to say that the same effect can be obtained by using the + 45 ° phase shifter 5 as the + 90 ° phase shifter and the −45 ° phase shifter 7 as the 0 ° phase shifter.

Further, the television input signal is not limited to the intermediate frequency, and may be, for example, Japanese channel 1 or 2, or US channel 2 or 3, or 4.

As described above, according to the present embodiment, by applying the distortion-free video intermediate frequency carrier generated by the voltage controlled oscillation circuit 6 as shown in FIG. 2 (b) to the 4.5 MHz audio intermediate frequency detection circuit 4, Even if the image modulation degree is overmodulated by more than 95%, the second
A distortion-free 4.5 MHz audio intermediate frequency signal as shown in FIG. 2D can be detected, and thus a correct descrambling pulse as shown in FIG. 2E can be detected. In addition, by forming the video detection circuit 8 and the 4.5 MHz audio intermediate frequency detection circuit 4 as separate circuits, a 4.5 MHz audio intermediate frequency signal in which no video signal component is superimposed as shown in FIG. As shown in FIG. 6 (b), the dynamic range can be given a margin and a 4.5 MHz audio intermediate frequency signal without distortion can be detected. Further, a gain control terminal is provided in the video detection circuit 8 to reproduce a synchronizing signal, and the head value AGC circuit 9 stabilizes the gain of the video intermediate frequency amplification circuit 2, thereby changing the video modulation degree due to a change in video content. Even if the frequency changes, it is possible to detect a 4.5 MHz audio intermediate frequency signal with no change in gain.

Advantageous Effects of the Invention As described above, according to the present invention, even if the image modulation degree becomes overmodulation of 95% or more, or even if the image modulation degree changes due to a change in the content of the image, the descrambling pulse is generated. It can be detected correctly.

[Brief description of the drawings]

FIG. 1 is a block diagram of a descramble pulse detector according to one embodiment of the present invention, FIG. 2 is a waveform diagram of the descramble pulse detector, FIG. 3 is a block diagram of a conventional descramble pulse detector, FIG. FIG. 4 is a waveform diagram showing the descrambling operation of the CATV receiver, FIG. 5 is a waveform diagram of the conventional example, and FIGS. 6 (a) and 6 (b) are waveform diagrams comparing the conventional example with the present embodiment. 2... Video intermediate frequency amplification circuit, 3... Phase comparison circuit, 4
… 4.5 MHz audio intermediate frequency detection circuit, 5… + 45 ° phase shifter, 6… voltage controlled oscillator, 7… −45 相 phase shifter, 8
…… Video detection circuit, 9… Top value AGC circuit, 10… 4.5MH
z bandpass filter, 11 AM detector circuit, 12 comparator, 13 pulse width controller.

Claims (1)

(57) [Claims] An amplifier connected to a television signal input terminal, a third multiplier having a first multiplier, a second multiplier, and a gain control terminal connected to the amplifier, and a second multiplier connected to the amplifier. A voltage controlled oscillation circuit connected to the multiplier through a low-pass filter, a leading value AGC circuit interposed between an output terminal of a third multiplier and a gain control terminal of the amplifier circuit, A first phase shifter for shifting the output of the oscillation circuit with a phase difference between the first and second phase shifters; an output terminal of one of the phase shifters is connected to a video carrier input terminal of the first multiplier and a second phase shifter; Connect the output terminal of the other phase shifter to the video carrier input terminal of the third multiplier so as to obtain a 4.5 MHz audio intermediate frequency signal from the first multiplier. The configured descramble pulse detector.