JP2950625B2 - Voltage supply circuit for nonvolatile memory cells - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage supply circuit for supplying a voltage to a nonvolatile memory cell.

[0002]

2. Description of the Related Art Conventionally, there is a circuit as shown in FIG. 11 as a voltage supply circuit for supplying a voltage to a nonvolatile memory cell.

As shown in FIG. 11, a booster circuit 102 is connected to an EEPROM memory cell 100. The booster circuit 102 supplies a high voltage (for example, 20 V) that is used when writing data in the EEPROM memory cell or when erasing the data. For example, the operating power supply voltage (for example, 5 V) is boosted by the booster circuit 102 to the high voltage. A wire 104 connecting the booster circuit 102 and the EEPROM memory cell 100 to each other is connected to a diode 106 which is connected to a cathode and grounds the anode. This diode 106 is a limiter, and when an excessive voltage is applied to the diode, the diode 106 breaks the diode.
This is to protect the EEPROM memory cell 100 so that the gate oxide film and the like are not destroyed. A pad 108 is connected to a node a between the diode 106 and the EEPROM memory cell 100. The pad 108 is used at the time of testing. For example, at the time of a screening test (selection inspection process) performed during the manufacturing process, a voltage is applied to the pad 108 to apply a voltage to the EEPROM memory cell 100. It is supplied.

[0006] The screening test is a screening test in which, for example, erasing / writing of memory is repeatedly performed on a memory cell, and a good product and a defective product are sorted out. Of course, those broken by this screening test are regarded as defective, while those which are normal are regarded as good and sent to the next step, for example. There are various rules for this screening test. For example, erasing / writing of memory is repeated tens of thousands of times.

However, a screening test in which erasing / writing of memory is repeated tens of thousands of times takes a very long time, and as a result, a period from the start of manufacturing the device to completion of the device is lengthened. This is one of the factors.

As a method of shortening the time required for the screening test, it is considered that the voltage supplied to the memory cell during the screening test is made higher than the voltage used for normal erasing / writing. I have. This is a method called "electric field acceleration screening". According to this, the voltage is set higher than in the normal use, so that stress is easily applied, and the number of repetitions is reduced.

However, in the voltage supply circuit as shown in FIG. 11, a diode (limiter) 106 is
8 to the node a between the memory cells 100. Therefore, the potential E between the node a and the memory cell 100 does not rise above the limit voltage limited by the diode 106. Therefore, even if a high voltage is applied to the pad 108, the limit is applied by the diode 106, and the electric field acceleration screening cannot be performed.

[0008]

As described above, an inspection process typified by a screening test, for example, requires a very long time. For this reason, the inspection process is one of the causes of increasing the period from the start of manufacturing the device to the completion of the device.

As a method for solving this problem, there is electric field acceleration screening. However, in a conventional voltage supply circuit, a limiter is connected between a pad and a memory cell. The voltage cannot be switched between at the time of the screening test.

The present invention has been made in view of the above points, and an object of the present invention is to provide a circuit for supplying a voltage to a nonvolatile memory cell capable of performing electric field acceleration screening.

[0011]

According to a first aspect of the present invention, there is provided a voltage supply circuit for a nonvolatile memory cell, comprising: a booster for boosting a power supply voltage; one end connected to the booster; A step-down unit for stepping down the boosted voltage, a nonvolatile memory cell connected to the other end of the step-down unit, and a pad having one end connected to a point between the step-down unit and the memory cell. In normal use, a voltage stepped down by the step-down means is supplied to the memory cell, and a voltage applied to the pad and higher than the stepped-down voltage is supplied to the memory cell in an inspection step. It is characterized by having done.

According to a second aspect of the present invention, there is provided a voltage supply circuit for a non-volatile memory cell, comprising: a booster for boosting an operating power supply voltage; Step-down means for stepping down, a non-volatile memory cell connected to the other end of the step-down means, a first terminal provided between the step-down means and the non-volatile memory cell; And a second terminal provided between the first terminal and the second terminal during normal use, wherein a voltage stepped down by the step-down means is supplied to the memory cell during normal use. Is short-circuited to supply the boosted voltage to the memory cell.

According to a third aspect of the present invention, there is provided a voltage supply circuit for a nonvolatile memory cell, comprising: a booster for boosting an operating power supply; one end connected to the booster, for reducing a voltage boosted by the booster; A non-volatile memory cell connected to the other end of the step-down means via a first switch; a point between the first switch and the non-volatile memory cell; And a voltage transmission path having a second switch, wherein the first switch is turned on and the second switch is turned off in a normal use. Supplying the voltage stepped down by the step-down means to the memory cell, turning off the first switch and turning on the second switch during the inspection step, and passing the stepped-up voltage through the voltage transmission path. Before Characterized by being configured to supply to the memory cell. In the first to third aspects,
The step-down means is a diode having a cathode connected to the memory cell.

[0014]

In the voltage supply circuit for the nonvolatile memory cell according to the first to third aspects as described above, in the normal use,
The voltage is supplied to the memory cell via the step-down means. Along with this, for example, a pad having one end connected to one point between the step-down unit and the memory cell, or a terminal provided at each end of the step-down unit, or a switch connected to each end of the step-down unit, for example, Further, there is further provided a portion mainly used during the inspection process, such as a voltage transmission path having the following. One end of each of these parts is connected between the memory cell and the step-down unit so that a voltage different from the voltage stepped down by the step-down unit can be supplied to the memory cell. As a result, the voltage supplied to the memory cell can be switched between the normal use and the inspection step, and the electric field acceleration screening can be performed.

Further, the step-down means is constituted by a diode having a cathode connected to the memory cell, so that a current flowing from the portion toward the step-up means can be prevented.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a circuit for supplying a voltage to a nonvolatile memory cell according to a first embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 10 are denoted by the same reference numerals.

As shown in FIG. 1, an EEPROM memory cell 100 (hereinafter simply referred to as a cell 100) and a booster circuit 102 which boosts an operating power supply voltage and generates a high voltage used for erasing / writing of memory, They are connected to each other by a wiring 104. A step-down circuit 110 is inserted into the wiring 104. The step-down circuit 110 is composed of a plurality of diodes D1 to Dn, for example. For the plurality of diodes D1 to Dn, for example, an N-channel MOS
An FET in which one of the source / drain and the gate is short-circuited may be used. A plurality of diodes D1 to Dn are connected in series such that a cathode is connected to the cell 100 and an anode is connected to the booster circuit 102.
Node between the cathode of diode D1 and cell 100
The pad 108 is connected to a pad 108 used during a test.

According to the voltage supply circuit configured as described above, the voltage E1 stepped down by the step-down circuit 110 is supplied to the cell 100 in, for example, a normal operation. For example, the voltage E1 is
The voltage becomes lower than the voltage boosted by the booster circuit 102 by (the number of connection stages of the diode n × the forward drop voltage VD of the diode). In an inspection process such as a screening test, the voltage E2 applied to the pad 108 from the external power supply 111 is supplied to the cell 100.

With the voltage supply circuit having the above configuration, the voltage supplied to the cell 100 can be switched between the normal use and the inspection step, and electric field acceleration screening can be performed. As a result, a voltage supply circuit for the nonvolatile memory cells that can reduce the time required for the inspection process can be obtained.

When a voltage is supplied from the pad 104 to the cell 100, the potential of the node a increases. However, at this time, since the cathodes of the diodes D1 to Dn constituting the step-down circuit 110 are connected to the node a as shown in FIG. , A reverse bias is applied, and no current flows. When a voltage is supplied from the pad 108 to the cell 100, the booster circuit 102 may be maintained at a predetermined voltage. For example, the voltage applied to the pad 108 is maintained at the same or lower voltage.

FIGS. 2 and 3 are diagrams showing a voltage supply circuit to a nonvolatile memory cell according to a second embodiment of the present invention. 2 and 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.

As shown in FIG. 2 or FIG.
The first terminal 120A is connected to a node a between
The second terminal 120B is connected to a node b between the step-down circuit 110 and the step-up circuit 102.
These first and second terminals 120A and 120B are each open in a normal state, and are used only at the time of a test, for example.

For example, FIG. 2 shows a normal state (at the time of actual use). The voltage boosted by the boosting circuit 102 is stepped down to some extent by the step-down circuit 110 and then supplied to the cell 100 (voltage E1). .

FIG. 3 shows a state at the time of, for example, a screening test. The first terminal 120A and the second terminal 120B are short-circuited by the short-circuit means 122.
In this short-circuited state, the voltage boosted by the booster circuit 102 is supplied to the cell 100 via the short-circuiting means 122 (voltage E2).

As described above, by short-circuiting the first terminal 120A and the second terminal 120B, the booster circuit 10
2 while keeping the voltage boosted in step 2 almost unchanged.
Can be supplied. On the other hand, unless short-circuited, the boosted voltage is stepped down by the step-down circuit 110 and then the cell 1
00 can be supplied. As a result, as in the first embodiment, the voltage supplied to the cell 100 can be switched between the normal use and the inspection step. Various methods are conceivable as the short-circuiting means 122. For example, short-circuiting may be performed via a wafer prober or the like.

FIG. 4 is a diagram showing a circuit for supplying a voltage to a nonvolatile memory cell according to a third embodiment of the present invention. 4, the same parts as those in FIG. 2 are denoted by the same reference numerals, and only different parts will be described.

As shown in FIG. 4, the second terminal 120B
May be connected to the step-down circuit 110. For example, the second terminal 12 is connected to one of the interconnection points (nodes c) of the diodes D1 to Dn connected in series in the step-down circuit 110.
0B is connected.

In this case, similarly to the second embodiment, only by short-circuiting the first terminal 120A and the second terminal 120B, the voltage sufficiently lowered by the step-down circuit 110 and the terminal 120B Two types of voltages can be obtained, namely, the extracted voltage and the voltage can be supplied to the cell 100.

FIG. 5 is a diagram showing a circuit for supplying a voltage to a nonvolatile memory cell according to a fourth embodiment of the present invention. 5, the same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.

As shown in FIG. 5, the step-down circuit 110 and the node
A first MOSFET 130 connected in series with the gate a and functioning as a switch is provided. Also,
A node a and a node b are connected to each other, and a voltage transmission path 128 for transmitting the voltage of the node b to the node a is provided. This voltage transmission path 128 is provided with a second MOSFET 132 that functions as a switch.
The gates of the MOSFETs 130 and 132 have a signal A as a control signal and an inverted signal A thereof, respectively.
Driven by (-).

For example, in this circuit, in a normal state (at the time of actual use), the MOSFET 130 is turned on,
The MOSFET 132 is turned off. Thereby, the voltage stepped down by the step-down circuit 100 is supplied to the cell 100 (voltage E1).

On the other hand, during the inspection process,
130 is turned off and the MOSFET 132 is turned on. Thus, the voltage boosted by the booster circuit 100 is supplied to the cell 100 via the voltage transmission path 128 (voltage E2). In this way, as in the first embodiment, the voltage supplied to the cell 100 can be switched between the normal use and the inspection step. Also, MOS
The FETs 130 and 132 may be replaced by other switch means. Other switch means include:
For example, a fuse or the like.

FIG. 6 is a diagram showing a circuit for supplying a voltage to a nonvolatile memory cell according to a fifth embodiment of the present invention. 6, the same parts as those in FIG. 5 are denoted by the same reference numerals, and only different parts will be described.

As shown in FIG. 6, a second node is provided between a node a and a node c which is an interconnection point of the diodes D1 to Dn.
A voltage transmission path 128 having a MOSFET 132 may be inserted.

FIG. 7 is a diagram showing a circuit for supplying a voltage to a nonvolatile memory cell according to a sixth embodiment of the present invention. 7, the same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.

As shown in FIG. 7, in the circuit described in the first embodiment, a diode 1 functioning as a limiter is connected to a node b between the step-down circuit 110 and the step-up circuit 102.
06 is further connected. The diode 106 has a cathode connected to the node b and an anode grounded so that it can function as a limiter. Thus, the diode 106 as a limiter may be connected between the step-down circuit 110 and the step-up circuit 102.

FIG. 8 is a diagram showing a circuit for supplying a voltage to a nonvolatile memory cell according to a seventh embodiment of the present invention. 8, the same parts as those in FIG. 2 are denoted by the same reference numerals, and only different parts will be described. As shown in FIG. 8, a diode 106 functioning as a limiter is further connected to the node b in the circuit described in the second embodiment.

In this case, the voltage boosted by the boosting circuit 102 is limited by the diode 106. This limited voltage is stepped down by the step-down circuit 110 and supplied to the cell 100, or the limited voltage short-circuits the terminals 120A and 120B so that the voltage is maintained almost unchanged and the cell 100 To be supplied to either. Thus, the voltage for performing the electric field acceleration screening can be limited.

FIG. 9 is a diagram showing a circuit for supplying a voltage to a nonvolatile memory cell according to an eighth embodiment of the present invention. In FIG. 9, the same portions as those in FIG. 5 are denoted by the same reference numerals, and only different portions will be described. As shown in FIG. 9, a diode 106 functioning as a limiter is further connected to the node b in the circuit described in the fourth embodiment. In this case, the voltage for performing the electric field acceleration screening can be limited as in the seventh embodiment. Next, the effect of performing the electric field acceleration screening will be described in more detail.

FIG. 10 is a characteristic diagram (Weibull plot) showing the relationship between the number of erase / write operations on the horizontal axis and the cumulative failure rate of the EEPROM on the vertical axis. FIG. 10 is a diagram for explaining electric field acceleration screening, and is schematically shown for this purpose.

In FIG. 10, a line I is a line showing a case where the screening test is performed at the voltage E1 (voltage during normal use). Line II is a line showing the case where the screening test was performed by the voltage E2 (voltage higher than in normal use: indicating electric field acceleration screening). The relationship between the voltage E1 and the voltage E2 is E1 <E2
It is.

As shown in FIG. 10, for example, it is assumed that the erasing / writing has been performed 100 times on both the line I and the line II. At this time, in the line II, the number of times of 100
A defect rate equivalent to about 3000 times is realized. .DELTA.F1 in the figure is a failure rate at the time when erasing / writing has reached 10,000 in 100 screenings of erasing / writing. ΔF2 is the erase / write 100
This is the defect rate at the time when erasing / writing becomes 10,000 times in the screening of 0 to 3000 times. The relationship between these defect rates is ΔF1> ΔF2. Due to such a difference in the defective rate, the defective rate after the product is shipped can be reduced, and the time required for the screening test can be reduced.

According to the voltage supply circuit for the non-volatile memory cell having the above-described configuration, an external power supply of the device or a second power supply, as typified by the first embodiment, between the normal use and the inspection step As typified by the fourth embodiment, the voltage supplied to the EEPROM memory cell can be switched by boosting inside the device. As a result, the electric field acceleration screening having the above-described excellent effects can be realized by a simple circuit having only a step-down circuit, for example.

[0045]

As described above, according to the present invention,
It is possible to provide a voltage supply circuit for a nonvolatile memory cell capable of performing electric field acceleration screening.

[Brief description of the drawings]

FIG. 1 is a diagram showing a voltage supply circuit to a nonvolatile memory cell according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a voltage supply circuit to a nonvolatile memory cell according to a second embodiment of the present invention.

FIG. 3 is a first diagram showing a voltage supply circuit to a nonvolatile memory cell according to a third embodiment of the present invention;

FIG. 4 is a second diagram showing a voltage supply circuit to a nonvolatile memory cell according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a voltage supply circuit to a nonvolatile memory cell according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a voltage supply circuit to a nonvolatile memory cell according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a voltage supply circuit to a nonvolatile memory cell according to a sixth embodiment of the present invention.

FIG. 8 is a diagram showing a voltage supply circuit to a nonvolatile memory cell according to a seventh embodiment of the present invention.

FIG. 9 is a diagram showing a circuit for supplying a voltage to a nonvolatile memory cell according to an eighth embodiment of the present invention.

FIG. 10 is a characteristic diagram showing a relationship between erasing / writing and the cumulative failure rate of the EEPROM.

FIG. 11 is a diagram showing a conventional voltage supply circuit for a nonvolatile memory cell.

[Explanation of symbols]

100: an EEPROM memory cell, 102: a booster circuit,
106: diode (limiter), 108: pad, 1
10: step-down circuit, 120A: first terminal, 120B: second terminal, 122: short-circuit means, 128: voltage transmission path,
130, 132 ... MOSFET.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 29/788 29/792 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/8247 G11C 16/06 H01L 21/822 H01L 27/04 H01L 27/10 H01L 29/788

Claims (4)

(57) [Claims] 1. A booster for boosting a power supply voltage, a step-down unit having one end connected to the booster, and stepping down a voltage boosted by the booster, and a nonvolatile unit connected to the other end of the step-down unit. A memory cell, a pad having one end connected to one point between the step-down unit and the memory cell,
And supplying a voltage stepped down by the step-down means to the memory cell during normal use, and supplying a voltage higher than the stepped-down voltage applied to the pad during the inspection step to the memory cell. A voltage supply circuit for a non-volatile memory cell, characterized in that: 2. A booster for boosting a power supply voltage, a step-down unit having one end connected to the booster and stepping down a voltage boosted by the booster, and a nonvolatile unit connected to the other end of the step-down unit. A memory cell, a first terminal provided between the step-down unit and the non-volatile memory cell, and a second terminal provided between the step-down unit and the step-up unit, During normal use, the voltage stepped down by the step-down means is supplied to the memory cell. At the time of the inspection step, the first terminal and the second terminal are short-circuited, and the stepped-up voltage is supplied to the memory cell. A voltage supply circuit for a non-volatile memory cell, wherein 3. A step-up means for stepping up an operating power supply, a step-down means having one end connected to the step-up means and stepping down a voltage boosted by the step-up means, and a first switch connected to the other end of the step-down means. A non-volatile memory cell connected through the first switch and the non-volatile memory cell, and a point between the step-down unit and the step-up unit are connected to each other; And a voltage transmission path having two switches, wherein in normal use, the first switch is turned on, the second switch is turned off, and the voltage stepped down by the step-down means is supplied to the memory cell; In the inspection step, the first switch is turned off, the second switch is turned on, and the boosted voltage is supplied to the memory cell via the voltage transmission path. Sex note Voltage supply circuit for recell. 4. The voltage supply circuit according to claim 1, wherein said step-down means is a diode having a cathode connected to said memory cell. .