JP2949988B2 - Flat panel display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display using an electron emission cathode.

[0002]

2. Description of the Related Art In a flat panel display using an electron emission cathode, minute electron emission cathodes are arranged vertically and horizontally, and each pixel emits light by performing vertical and horizontal two-dimensional addressing to constitute a display. FIG.
FIG. 1 is a schematic cross-sectional view of a part of a matrix address flat panel display disclosed in Japanese Patent Application Publication No. 0065-0065. In the figure, 2 is an electron emission cathode, 3 is an insulating layer, 6 is a column, 7a,
7b and 7c are phosphors, 8 is an anode, 9 is a face panel, 10 is a substrate, 11a, 11b, 11c is a base, 12
Denotes an inter-substrate insulating layer, and 13 denotes a gate.

Next, the operation will be described. When a voltage is applied between the electron-emitting cathode 2 and the gate 13, electrons are emitted from the tip of the conical electron-emitting cathode 2 located near the gate hole, and travel toward the anode 8 to which a high voltage is applied. At this time, electrons hit the phosphor on the lower surface of the anode 8, and the phosphor emits light. The selection of a matrix of pixels arranged two-dimensionally as a display is performed, for example, by dividing the substrate in the vertical direction and dividing the gate 13 in the horizontal direction, and applying a voltage between a divided substrate and a divided gate. Do it by doing.

According to this method, it is possible to form a display by causing each pixel to emit light by performing vertical and horizontal addressing.

[0005]

In the above-described method, it is necessary to divide a substrate on which an electron emission cathode is formed in order to address a pixel.
When an i-wafer is used as a base and formed by etching of Si or the like, it is difficult to divide the Si wafer as the base.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a flat panel display which can easily address two-dimensional pixels with a simple element configuration and is easy to manufacture. .

[0007]

A flat panel display according to the present invention comprises a gate for controlling electrons emitted from an electron emission cathode, a first gate in an array parallel to one axis, and a gate in a direction orthogonal to the one axis. It has a two-stage structure with a parallel array of second gates, and is disposed so that the tip of the electron emission cathode is located between the two-stage gates. Is used to select electron emission according to the pixel.

[0008]

In the flat panel display constructed as described above, the addressing of the pixels can be easily performed by the first and second two-stage gates. Becomes Further, this gate is easy to form.

[0009]

【Example】

Embodiment 1 FIG. FIG. 1 is a schematic cross-sectional view of a part of a flat panel display using an electron emission cathode according to one embodiment of the present invention, and FIG. 2 is a schematic plan view of a gate in FIG. In this figure, 1 is a substrate, 2 is an electron emission cathode, 3
Is an insulating layer, 4 is a lower gate which is a first gate, and 4a,
Reference numerals 4b and 4c denote lower gates divided in parallel in the uniaxial direction, and 5 denotes an upper gate which is a second gate, 5a and 5c.
Reference numerals b and 5c denote upper gates divided in parallel in a direction perpendicular to one axis, 6 a support, 7 a phosphor, 8 an anode, 9
Is a face panel. The tip of the electron emission cathode 2 is arranged between the upper and lower gates 4 and 5. Many circles in FIG. 2 indicate gate holes. Also,
In this figure, for the sake of explanation, a configuration in which 3 × 3 electron emission cathodes 2 are provided in one pixel where the X and Y columns intersect is shown, but an arbitrary M × N configuration may be used.

Next, the operation will be described. When a voltage is simultaneously applied to any one of the X columns and any one of the Y columns of the gate shown in FIG. 2, an appropriate electric field is applied to the electron emission cathode 2 and electrons are emitted to cause the phosphor 7 to emit light. However, even if a voltage is applied to only one of the rows X or one of the rows Y, the electric field applied to the electron emission cathode 2 is too small to emit electrons. Therefore, the XY of a certain pixel
The pixel emits light when a voltage is applied to both gates. As described above, in this flat panel display, the gates have a two-tiered structure in the upper and lower parts, and each gate is separated and crossed so as to correspond to a pixel, and a voltage is applied to each gate independently. Thus, electron emission can be selected, and pixel addressing can be easily performed. Also, this gate is easy to form,
There is no need to electrically divide a substrate that is difficult to divide as in the prior art, and it is easy to manufacture.

By the way, any one of the X rows of the gate or Y
Even when a voltage is applied to only one of the columns, an electric field may be increased and electron emission may occur depending on the positional relationship between the electron emission cathode 2 and the gates 4 and 5 to which the voltage is applied. Is not done properly.

FIG. 3 is a graph showing the difference between the gate / cathode height, which is the difference between the height of the center of the insulating layer 3 in the thickness direction between the two-stage gates 4 and 5 and the height of the electron emission cathode 2, and The result of calculating the relationship of the electric field at a point 0.01 μm away from the tip of the emission cathode 2 using the finite element method is shown. Here, the voltage applied to the gate is 100 V when on, 0 V when off, and the gate hole diameter is 1 μm. In the figure, the characteristic curve indicated by a white circle indicates the case where a voltage is applied to the upper gate 5 and the voltage is not applied to the lower gate 4 of the two-stage gate. The configuration is intended to prevent pixels from emitting light when no voltage is applied to the upper gate 5. The characteristic curve shown by the broken line is for the case where a voltage is applied to both the gates 4 and 5 in the two stages, and the purpose is for the pixel to emit light. When a voltage is applied to only one of the gates, the electric field is affected by the gate / cathode height difference, and the electric field is lowest when the gate / cathode height difference is about 0.15 μm. The extent to which the electric field is reduced and electrons are not emitted and the phosphor does not emit light depends on the general relationship between the electric field at the tip of the electron emission cathode and the current of the anode 8 shown in the graph of FIG. It is considered to be. In FIG. 5, when a voltage is applied to both of the two-stage gates 4 and 5 (corresponding to the broken line in FIG. 3), the electric field and the anode current are reduced by one.
It is shown as a standardized value in the case of. Therefore, as shown in FIG. 3, the difference in gate / cathode height is 0.1 μm to 0.2 μm.
The electric field is less than 60% of the maximum when
No electrons are emitted, and appropriate pixel addressing can be performed. Two gates 4 and 5 in two gates 4 and 5
The height of the center in the thickness direction of the insulating layer 3 between the electron emitting cathodes 2
The height is preferably 0.1 to 0.2 μm higher than the height of the tip. That is, it is preferable that the tip of the electron emission cathode 2 is arranged to be lower than the intermediate position between the two gates 4 and 5 by 0.1 to 0.2 μm.

Further, in the graph of FIG.
When a negative voltage is applied to the other gate, the difference between the height of the gate / cathode, which is the difference between the height of the center of the insulating layer between the two gates in the thickness direction and the height of the electron emission cathode, The result of calculating the relationship of the electric field at a point 0.01 μm away from the tip of the emission cathode by using the finite element method is shown. In the figure, the characteristic curve indicated by a white circle indicates that when a positive voltage is applied to the upper gate 5 and a negative voltage is applied to the lower gate 4 of the two-stage gates.
The characteristic curve indicated by a black circle is a configuration in which a pixel does not emit light when a positive voltage is applied to the lower gate 4 and a negative voltage is applied to the upper gate 5 of the two gates.
The broken line indicates the case where a voltage is applied to both of the two-stage gates, and the purpose is to cause the pixel to emit light. When a positive voltage is applied to one of the gates, the electric field is affected by the gate / cathode height difference, and the electric field becomes lowest when the gate / cathode height difference is about 0.15 μm. If the electric field is negative, no electrons are emitted. By applying a negative voltage, the electric field when the pixel does not want to emit light can be significantly reduced. Therefore,
The voltage applied to the two-stage gates 4 and 5 is preferably a positive voltage when the electron emission is on and a negative voltage when the electron emission is off. As described above, it is possible to easily control the electron emission by optimizing the positional relationship between the electron emission cathode 2 and the gates 4 and 5, and selecting the polarity of the voltage applied to the gates 4 and 5.

[0014]

As described above, according to the flat panel display of the present invention, the first gate in the form of an array in which the gates are parallel to one axis and the second gate in the form of an array which are parallel to the direction perpendicular to the one axis. And a two-stage structure in which the tip of the electron-emitting cathode is located between the first and second gates, and a voltage is applied independently to the first and second gates to form a two-dimensional structure. Electron emission according to the arranged pixels can be easily selected, and there is an effect that the entire device configuration and creation are easy.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a part of a flat panel display according to an embodiment of the present invention.

FIG. 2 is a schematic plan view of a gate portion of the flat panel display according to one embodiment of the present invention.

FIG. 3 is a graph showing an electric field analysis result according to one embodiment of the present invention.

FIG. 4 is a graph showing an electric field analysis result according to one embodiment of the present invention.

FIG. 5 is a graph showing a general relationship between an electric field and an anode current at the tip of an electron emission cathode according to the present invention.

FIG. 6 is a schematic cross-sectional view showing a part of a conventional flat panel display.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Electron emission cathode 3 Insulating layer 4 Lower gate 5 Upper gate 7 Phosphor 8 Anode 9 Face panel

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-48-85074 (JP, A) JP-A-54-47472 (JP, A) JP-A-3-208241 (JP, A) JP-A-3-20841 22329 (JP, A) JP-A-63-237340 (JP, A) JP-A-3-261103 (JP, A) JP-A-61-221783 (JP, A) JP-A-63-237340 (JP, A) Special table Hei 1-502307 (JP, A) Special table Hei 4-506280 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01J 31/08-31/24 H01J 1/30 H01J 29/46-29/52

Claims (1)

(57) [Claims] A plurality of electron-emitting cathodes formed on a substrate;
A plane having a gate for emitting electrons from these electron emission cathodes and controlling the emitted electrons, and a face panel having a phosphor that emits visible light in response to the collision between the anode and the electrons on the surface facing the electron emission cathode. In the panel-type display, the gate has a two-stage structure of a first gate in an array parallel to a single axis direction and a second gate in an array parallel to a direction orthogonal to the single axis. The first and second gates are arranged so as to be located between the first and second gates, and the first and second gates are independently applied with a voltage to select electron emission according to pixels arranged two-dimensionally. A flat panel display characterized by the above-mentioned.