JP2944500B2 - Compiling apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a compiling apparatus and method, and more particularly to a compiling apparatus and method for a processor having parallel instructions for simultaneously accessing data in two independent address space memories.

[0002]

2. Description of the Related Art Generally, a compiling apparatus and method of this type are realized by a data processing apparatus storing a compiler which is software means for compiling a source program (source program) into a target program. This compiler has been widely used in the field of software development as a translation program for a program description language, and has also spread to the field of software development in microprocessors with the advent of the C compiler.
In recent years, it has begun to be used in software development of a signal processing microprocessor that enables parallel execution by dual load / store. A compiler is required to output parallel execution instructions effectively and output code that can be executed at high speed.

FIG. 10 is a block diagram showing a configuration and an operating environment of a conventional compiling device which is a data processing device storing the compiler. As shown in FIG. 10, this conventional compiling device 101 includes a lexical analysis unit 1001, a syntax analysis unit 1002, and a data arrangement unit 10
03, a code generation means 1004, and are connected to the auxiliary storage device 102 for storing the source program 1005 and the assembler description program 1006.

In FIG. 10, first, the lexical analysis means 10
In 01, the source program 1005 read by the auxiliary storage device 102 is decomposed into lexical characters and lexical analysis is performed. In response to the result of the lexical analysis performed by the lexical analysis means 1001, the syntax analysis means 1002 constructs a syntax and recognizes the syntax. Then, in the data arranging unit 1003, the arrangement destination of all data is Y
Determined in memory. In the code generation means 1004,
The assembler description program 1006 is generated based on the result of the syntax analysis performed by the syntax analysis unit 1002 and the data location determined by the data allocation unit 1003, and stored in the auxiliary storage device 102.

Next, a specific example of an assembler description program generated by the conventional compiling device shown in FIG. 10 will be described with reference to the drawings.

FIG. 6 is an explanatory diagram showing an example of a source program input by the compiling device 101. In the source program 601, the data definition statement 602 is a description that instructs to secure a data area on the memory.
Variable work of 50 elements, variable wo of 100 elements
rk2 and work3 are defined. The product-sum operation 603 outside the loop is a process of multiplying the element at address 0 of the variable work1 by the element at address 0 of the variable work2, and adding the result to the variable result. The product-sum operation processing 604 during the 50 loops is performed by using the i of the variable work1.
This is a process of multiplying the element at address and the element at address i of the variable work3, and adding the result to the variable result. At the time of the loop processing, the variable i changes from 0 to 49 in order, so that the value of the work 1 and the work 3 from address 0 to 4
The elements up to address 9 are each multiplied and the data resu
It is added to lt. The same applies to the product-sum operation processing 605 during 100 loops.

FIG. 2 is an explanatory diagram showing a configuration example of a target processor of an assembler description program output by the compiling device 101. The memory configuration 201 includes an instruction memory 202, a data memory X ... 203, a data memory Y ... 204, and the data memory X ...
203 and the data memories Y... 204 have the same memory space. The general-purpose register 205 includes three registers R0, R1, and R2, and is mainly used for calculation. The data pointer register 206 is composed of a total of four registers including DP0 and DP1 for accessing the data memories X... 203 and DP2 and DP3 for accessing the data memories Y. Use when you do. The data pointer register syntax 207 includes an address setting instruction syntax 208 for setting an address to the data pointer register;
Access instruction syntax 209 for accessing data memory
There is. In addition, there is an increment instruction syntax 210 for accessing a data memory and updating an address with one instruction. The parallel instruction syntax 211 corresponds to the data memory X... 20
.. 212 and an access field Y... 213 of the data memory Y... 204, so that the data memory X... 203 and the data memory Y. However,
Simultaneous access to the same data memory is not possible. For example, data memory X ... 203 and data memory X ... 2
03 cannot be accessed simultaneously by one instruction. Hereafter, the data memories X... 203 are called X memories, the data memories Y... 204 are called Y memories, and the data pointer registers are called DP registers.

FIG. 11 is an explanatory diagram showing an example of an assembler description program which receives the source program 601 shown in FIG. 6 and is output by the conventional compiler 101 based on the processor configuration shown in FIG.

The variables work1, work2, and work3 defined by the data definition statement 602 in FIG. 6 are all translated into the Y memory data arrangement 1101 in FIG. The product-sum operation 603 outside the loop in FIG.
2, access instruction A 1103, operation instruction A 1109
Translated to An address setting instruction A... 1102 is an instruction for setting the addresses of the variables work1 and work2 assigned to the Y memory in the DP3 register and the DP2 register dedicated to the Y memory access, respectively. The access instruction A. The content pointed to, that is, the element at address 0 of the variable work1 is set in the R1 register, and the content pointed to by the DP2 register, ie, the variable work
This is an instruction for setting the element at address 0 of k2 in the R2 register. Note that the DP2 and DP3 registers are both Y
Because of memory access only, parallel instructions cannot be used. The operation instruction A... 1109 multiplies the R1 register and the R2 register and substitutes the result in the R1 register.
This is an instruction for adding the 0 register and the R1 register and assigning the result to the R0 register. The product-sum operation processing 604 during the 50 loops shown in FIG.
04, increment instruction B ... 1105, operation instruction B ...
Translated to 1110. Increment instruction B 110
5 is the content pointed to by the DP3 register, that is, the variable
After the element at address i of k1 is set in the R1 register, the DP3 register is incremented by 1, and the content indicated by the DP2 register, that is, the element at address i of the variable work3 is set in the R2 register, and then the DP2 register is incremented by 1. . Note that D
Since the P2 register and the DP3 register are both dedicated to Y memory access, parallel instructions cannot be used. The operation instruction B... 1110 is an instruction for multiplying the R1 register and the R2 register and assigning the result to the R1 register, adding the R0 register and the R1 register and assigning the result to the R0 register. The product-sum operation processing 605 during 100 loops in FIG. 6 is similar to the product-sum operation 604 during 50 loops, and is similar to the address setting instruction C... 1106, increment instruction C. ... translated into 1111.

For reference on compiler optimization, see "Compiler Sangyo Tosho Ikuo Nakata"
(P216-P268), “Compiler Baifukan Original Author A. V. Eiho, J.A. D. Ullman translator Norihisa Doi (P366-P506), Programming language processing system Iwanami Shoten Masataka Sasa (P396-P496)
Is referred to.

[0011]

In a conventional compiling device, data in two independent address space memories is stored in one memory.
For processors with parallel instructions that are accessed simultaneously by instructions, all data defined in the source program is located in the same data memory, so no parallel instructions can be generated, resulting in poor code generation efficiency. There are drawbacks. This is because the data in the two independent address space memories must be accessed by specifying addresses using separate dedicated registers, so that the instruction code including the parallel instruction cannot be determined until after the data allocation memory is determined. is there.

[0012] Therefore, an object of the present invention is to solve at least one of the above problems by providing a processor having parallel instructions for simultaneously accessing data in two independent address space memories with one instruction, thereby improving the code generation efficiency. It is an object of the present invention to provide a compiling apparatus and method for generating a good, particularly fast assembler description program.

[0013]

Therefore, the present invention provides a lexical analysis means for reading a source program stored in an auxiliary storage device and decomposing the read lexical data, and a syntax for recognizing a syntax lexically analyzed by the lexical analysis means. A compiling device that has an analyzing unit, determines a location of data used for a program instruction, generates an assembler description program based on the analysis result of the syntax analyzing unit and the location, and stores the program in the auxiliary storage device. When the program instruction is a parallel instruction for simultaneously accessing data in two independent address space memories, a temporary location of each data is determined, and an intermediate program is determined based on the analysis result of the syntax analysis unit and the temporary location. Refer to code generation means for generating, and the parallel instruction and the loop instruction in the intermediate program Calculating the number of loops total from parallel instruction reference count and loop count as a parallel instruction execution count of each of the parallel instructions, each independent address space memory
Generates a memory type table for registering selected for each of the temporary placement destination large instruction order of the parallel instruction execution count the memory type that identifies a data placement optimization means for optimizing the data arrangement, the intermediate program and Code regenerating means for regenerating code based on the memory type table to generate the assembler description program and storing the program in the auxiliary storage device.

Further, the present invention has a lexical analysis step of reading a source program stored in an auxiliary storage device and reading the lexical data, and a syntax analyzing step of recognizing a syntax lexically analyzed by the lexical analysis step. A compiling method for determining a location of data to be accessed by a program instruction, generating an assembler description program based on the result of the analysis in the syntax analysis step and the location, and storing the program in the auxiliary storage device; A code generation step of, when the instruction is a parallel instruction for simultaneously accessing data of two independent address space memories, respectively determining a temporary allocation destination of each data, and generating an intermediate program based on an analysis result of the syntax analysis means and the temporary allocation destination And the parallel instruction and the loop instruction in the intermediate program Calculates the loop count accumulated as a parallel instruction execution count of each of the parallel instructions from irradiation Mr parallel instruction reference count and loop count, each independent address space memory
Generates a memory type table for registering selected for each of the temporary placement destination large instruction order of the parallel instruction execution count the memory type that identifies a data arrangement optimization step for optimizing the data arrangement, the intermediate program and A code regenerating step of regenerating code based on the memory type table to generate the assembler description program and storing the program in the auxiliary storage device.

[0015]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration and operating environment of a first embodiment of the compiling device of the present invention. As shown in FIG. 1, the compiling device 11 of the present embodiment includes a lexical analyzer 101, a syntax analyzer 102,
Code generating means 103, data arrangement optimizing means 104,
A code regenerating means 105;
6, an intermediate program 107, a parallel instruction execution count table 108, a memory type table 109, and an assembler description program 110.

The lexical analysis means 101 reads the source program 106 for the processor having the configuration example shown in FIG. 2 from the auxiliary storage device 12 and decomposes it into lexical data to perform lexical analysis.

The syntactic analysis means 102 includes the lexical analysis means 10
Receiving the result of the lexical analysis in 1, a syntax is constructed and the syntax is recognized.

The code generation means 103 includes the syntax analysis means 1
In response to the result of the syntax analysis in step 02, a temporary location is allocated as a data location, that is, a data pointer register used when accessing the data memory has a DP corresponding to data in a one-to-one correspondence. The intermediate program 107 is assigned a register pseudonym and all instructions that can be generated as parallel instructions are regarded as parallel instructions.
To be stored.

The data arrangement optimizing means 104 receives the intermediate program 107 generated by the code generating means 103 and executes a parallel instruction execution composed of two DP register pseudonyms used in the parallel instructions and the number of parallel instruction executions. The frequency table 108 is stored in the auxiliary storage device 12. further,
A memory type for each temporary allocation destination is selected in the order of the instruction having a value of the number of times of parallel instruction execution, and a memory type table 109 including a DP register pseudonym and a memory type to which the temporary allocation destination is allocated is generated and stored in the auxiliary storage device 12. I do.

FIG. 3 shows the data arrangement optimizing means 104.
6 is a flowchart showing the processing procedure of FIG. This processing procedure will be described in detail with reference to FIG.

First, in a loop number initialization step 302, a variable LOOP_CN for counting the number of loops is set.
Initialize T with 1. Next, in an intermediate program reading step 303, one line is read from the intermediate program 107 created by the code generation means 103 in FIG. 1, and in an intermediate program reading end determination step 304 in FIG. When the processing is completed, the process proceeds to the parallel instruction execution count table sorting step 313. If the reading has not been completed, the process proceeds to the loop instruction determination step 305.

In the loop instruction determination step 305,
It is determined whether the read line is a loop instruction or not.
OP_CNT is multiplied by the number of loops and assigned to LOOP_CNT. Then, the intermediate program reading step 3
Return to 03. If the read instruction is not a loop instruction, it is determined in a loop instruction end determination step 307 whether or not the loop instruction has ended. If the loop instruction has ended, the variable LOOP_CNT is divided by the number of loops to determine the LO instruction.
Substitute for OP_CNT. Then, the process returns to the intermediate program reading step 303. If the instruction is not a loop end instruction, the process proceeds to a parallel instruction determination step 309.

In the parallel instruction determination step 309, it is determined whether or not the instruction is a parallel instruction. If the instruction is a parallel instruction, the same parallel instruction determination step 310 determines whether or not the same parallel instruction already exists in the parallel instruction execution count table. If not, the parallel instruction execution count table 40 shown in FIG.
1, the DP register pseudonym and LOOP_CNT, which are the operands of the parallel instruction, are set, and the process returns to the intermediate program reading step 303 in FIG. If the parallel instruction execution count table already exists, the process proceeds to the same parallel instruction reference count addition step 312.

The same parallel instruction reference count addition step 312
, LOOP_CNT is set to the same element in the parallel instruction execution count table 401 of FIG. If the instruction is not a parallel instruction, an intermediate program reading step 303 in FIG.
Return to

In the parallel instruction execution frequency table sorting step 313, the instructions are sorted in the order of the total number of loop times 404 of the parallel instruction execution frequency table 401 of FIG. Next, in the memory type table generation step 314 of FIG. 3, the DP register pseudonym registered in the parallel instruction execution count table 401 of FIG.
Register with. Further, the memory type setting step 3 in FIG.
In step S15, “X” is set to one memory type 407 of the two DP register pseudonyms having the largest total loop count 404 in the memory type table 405 of FIG. 4, and “Y” is set to the other. Next, in the unsolved memory type determination step 316 in FIG.
It is determined whether or not there is an unresolved element in the memory type 407 of 05, and if there is an unresolved element, the process proceeds to step 318.

In step 318, the parallel instruction execution count table 401 is referred to,
Type of two DP register pseudonyms for instructions with large ４
07 is set. If the memory types 407 of the two DP register pseudonyms are both set, the process proceeds to the unresolved memory type determination step 316 in FIG. When the memory type 407 in FIG. 4 is set for only one of the DP register pseudonyms, a memory type 407 different from the DP register pseudonym in which the memory type 407 is set is set. Further, if neither DP register pseudonym is set, "X" is set in one memory type 407 and "Y" is set in the other memory type, and the process proceeds to the unresolved memory type determination step 316 in FIG. Return.

If there is no unresolved element in the unresolved memory type determination step 316, the processing of the data arrangement optimizing means 104 of FIG. 1 is terminated, and the process proceeds to the code regenerating means 105 of FIG.

The code regenerating means 105 receives the intermediate program 107 and the memory type table 109 generated by the code generating means 103 and the data layout optimizing means 104, and performs data allocation according to the memory type of the memory type table 109. And assigns the determined DP register name to the DP register pseudonym of the intermediate program 107. Instructions that can generate parallel instructions are regarded as parallel instructions, and those that are not can be regarded as instructions obtained by dividing a parallel instruction into two instructions. 110 is generated and stored in the auxiliary storage device 12.

Next, a second embodiment of the compiling device of the present invention will be described. The compiling device of the present embodiment differs from the compiling device of the first embodiment only in the processing procedure of the data arrangement optimizing means 104 in the first embodiment shown in FIG. FIG. 5 is a flowchart showing a processing procedure of the data arrangement optimizing means in the present embodiment. With reference to FIG. 5, only this processing procedure will be described in detail.

First, in a loop number initialization step 501, a variable LOOP_CN for counting the number of loops is set.
Initialize T with 1. Next, in the intermediate program reading step 502, one line is read from the intermediate program 107 created by the code generation means 103 in FIG. 1, and in the intermediate program reading completion determining step 503 in FIG. When the processing is completed, the process proceeds to the parallel instruction execution number table sorting step 513. If the reading has not been completed, the process proceeds to the parallel instruction determination step 504. In the parallel instruction determination step 504, it is determined whether or not the instruction is a parallel instruction. If the instruction is not a parallel instruction, the process proceeds to a loop instruction determination step 509. If the instruction is a parallel instruction, the process proceeds to the same parallel instruction determination step 505.

In the same parallel instruction determination step 505, it is determined whether or not the same parallel instruction already exists in the parallel instruction execution count table. If the same parallel instruction already exists, the flow proceeds to the same parallel instruction reference count addition step 508; The process proceeds to the parallel instruction execution count table setting step 506. Same parallel instruction execution count table setting step 50
6, the parallel instruction execution count table 401 shown in FIG.
And the DP register pseudonym and L which are the operands of the parallel instruction
Set OOP_CNT. In the memory type table generation step 507 of FIG. 5, the memory type table 405 of FIG. 4 for setting the type of memory is generated.
The process returns to the step 502 for reading an intermediate program. Further, in the same parallel instruction reference count addition step 508, LOOP_CNT is set to the same element in the parallel instruction execution count table 401 in FIG.

In the loop instruction determination step 509,
It is determined whether or not the read line is a loop instruction. If the read instruction is a loop instruction, the variable LOO
P_CNT is multiplied by the number of loops and assigned to LOOP_CNT, and the process returns to the intermediate program reading step 502.
On the other hand, if the read instruction is not a loop instruction, the process proceeds to a loop instruction end determination step 511.

In loop instruction end determination step 511, it is determined whether or not the loop instruction has ended. If the loop instruction has ended, in step 512 the variable LOOP_C
NT is divided by the number of loops and assigned to LOOP_CNT,
The process returns to the intermediate program reading step 502. on the other hand,
If the instruction is not a loop end instruction, the process returns to the intermediate program reading step 502.

In the parallel instruction execution count table sorting step 513, the parallel instruction execution count table 401 in FIG. next,
According to the memory type setting step 514 in FIG. 5, “X” is set to one of the two memory types 407 of the two DP register pseudonyms having the largest total loop count 404 in the memory type table 405 of FIG. Set “Y”. Further, the unresolved memory type determination step 51 in FIG.
5, it is determined whether or not there is an unresolved element in the memory type 407 of the memory type table 405 in FIG. 4. If there is an unresolved element, the process proceeds to step 516.

In step 516, the parallel instruction execution count table 401 is referred to,
Are set, the memory type 407 of the two DP register pseudonyms with the larger. Memory type 407 of two DP register pseudonyms
If both are set, the process proceeds to the unresolved memory type determination step 515 in FIG. When the memory type 407 in FIG. 4 is set for only one of the DP register pseudonyms, a memory type 407 different from the DP register pseudonym in which the memory type 407 is set is set. further,
If neither DP register pseudonym is set,
“X” is set in one memory type 407 and “Y” is set in the other memory type, and the process returns to the unresolved memory type determination step 515 in FIG.

If there is no unresolved element in the unresolved memory type determination step 516, the processing of the data arrangement optimizing means 104 in FIG. 1 is terminated, and the flow advances to the code regenerating means 105 in FIG.

Next, the operation of the compiling device of the present invention shown in FIG. 1 will be described with reference to the drawings.

First, the lexical analysis means 101 of FIG.
The source program 601 in FIG. 6 is read from the auxiliary storage device 12, and the source program 601 is decomposed into lexical characters and lexical analysis is performed. Next, the syntax analysis unit 102 shown in FIG. 1 receives the result of the lexical analysis by the lexical analysis unit 101 and constructs and recognizes the syntax.

Next, the code generation means 103 receives the result of the syntax analysis by the syntax analysis means 102 and assigns a temporary location as the data location, ie,
Data pointer used when accessing memory
A DP register pseudonym corresponding to the data in a one-to-one correspondence is assigned to the register, and all instructions that can be generated as parallel instructions are generated as parallel instructions to generate an intermediate program code.
It is stored in the auxiliary storage device 12. FIG. 7 is an explanatory diagram showing an example of this intermediate program. At this time, the instructions that can be generated as the parallel instructions are the parallel instructions A 702, the parallel instructions B 704, and the parallel instructions C 707 in FIG.

Next, the data arrangement optimizing means 104 shown in FIG.
The description will be continued with reference to FIG. 3 which is a flowchart showing the processing procedure in. FIG. 8 is an explanatory diagram showing an example of a change in specific setting contents of the parallel instruction execution count table and the memory type table in the processing procedure of FIG.

First, in a loop number initialization step 302, a variable LOOP_CN for counting the number of loops is set.
Initialize T with 1. Next, in the intermediate program reading step 303, the clear instruction 70 is obtained from the intermediate program 700 of FIG. 7 created by the code generation means 103 of FIG.
Read 1 In the intermediate program reading completion determination step 304, it is determined that the reading has not been completed. Since the read line is the clear instruction 701 in FIG. 7, it is determined that the read instruction is not a loop instruction in the loop instruction determination step 305 in FIG.
It is determined that the instruction is not a loop end instruction, and it is further determined that the instruction is not a parallel instruction in the parallel instruction determination step 309.
The process returns to the intermediate program reading step 303. This processing is continued until a loop instruction, a loop end instruction, or a parallel instruction appears, and the parallel instruction A 702 in FIG.

Next, in the intermediate program reading completion determining step 304 in FIG. 3, it is determined that the reading has not been completed, and in the loop instruction determining step 305, it is determined that the reading is not a loop instruction.
At 7, it is determined that the instruction is not a loop end instruction. In the next parallel instruction determination step 309, the instruction is determined to be a parallel instruction, and the flow advances to the same parallel instruction determination step 310 to determine whether the same parallel instruction already exists in the parallel instruction execution count table. Since there is no such instruction, the parallel instruction execution count table 8 shown in FIG.
01 is the DP register pseudonym D which is the operand of the parallel instruction
P @ work1, DP @ work2 and LOOP_CNT
Is set in the parallel instruction execution count table 801.
The element 802 is the set content. Then, the process returns to the intermediate program reading step 303 of FIG.

Next, the appearance of a loop instruction, a loop end instruction, or a parallel instruction is caused by the loop instruction A... 703 in FIG.
It is when I read. In the intermediate program reading completion determination step 304 in FIG. 3, it is determined that the reading is not completed. Next loop instruction determination step 305
Is determined as a loop instruction, and a loop number multiplication step 30
Proceed to 6 and set the variable LOOP_CNT to 1 to set the number of loops to 5
Multiply by 0 and substitute for LOOP_CNT. LOOP_
50 is substituted for CNT, and the process returns to the intermediate program reading step 303.

Next, a loop instruction, a loop end instruction or a parallel instruction appears when the parallel instruction B... 704 in FIG. 7 is read. The processing is performed in the same manner as when the parallel instruction A... 702 is read, and the same parallel instruction determination step 310 in FIG. 3 determines whether the same parallel instruction already exists in the parallel instruction execution count table. Since there is no such instruction, the same parallel instruction execution count table setting step 311
As a result, the DP register pseudonym DP @ wo which is the operand of the parallel instruction is stored in the parallel instruction execution count table 801 of FIG.
rk1, DP @ work3 and LOOP_CNT 50
Is set in the parallel instruction execution count table 801. The element 803 is the content set. Then, the process returns to the intermediate program reading step 303 of FIG.

Next, the appearance of the loop instruction, the loop end instruction or the parallel instruction is caused by the loop end instruction A.
05. In the intermediate program reading completion determination step 304 of FIG. 3, it is determined that the reading is not completed, and a loop instruction determination step 305 is performed.
Is not a loop instruction. In the next loop instruction end determination step 307, it is determined that the instruction is a loop end instruction, and the flow advances to the loop number division step 308, where LOOP_CNT
Is divided by 50 of the number of loops, and LOOP_CNT
Substitute for 1 is assigned to LOOP_CNT, and the process returns to the intermediate program reading step 303.

The following are the same as loop instructions A 703, parallel instructions B 704, and loop end instructions A 705 for loop instructions B 706, parallel instructions C 707, and loop end instructions B 708 in FIG. The process is performed to generate the parallel instruction execution count table 801 in FIG.

Next, in the parallel instruction execution count table sorting step 313 in FIG. 3, the parallel instruction execution count table 801 in FIG. 8 is sorted in descending order of the total loop count. The result of the sorting is a sorted parallel instruction execution count table 809. The table for storing the memory type for each DP register pseudonym by the memory type table generation step 314 in FIG. 3, the memory type table A... 80 in FIG.
5 is generated. By the memory type setting step 315 of FIG. 3, the parallel instruction execution count table 809 of FIG.
, The memory type of the element 810 having the maximum total number of loop times is set in the memory type table A. 813 are the results set.

Next, the memory type table B... 813 of FIG.
It is determined whether or not there is any unresolved element. Since there are unresolved elements, the parallel instruction execution count table 809 after sorting is referred to. For the element of pseudonym B, the memory type of the memory type table B... 813 is set.
Since the memory type of the element of the DP register pseudonym A of the element 811 has not been determined and the memory type of the element of the DP register pseudonym B of the element 811 has been determined, it differs from the memory type of the element of the DP register pseudonym B of the element 811. Memory type "Y"
Is set in the memory type table B... 813. The memory type table C... 816 is the result of the setting.

Next, the memory type table C... 816 of FIG.
It is determined whether there are any unresolved elements. Since there are no unresolved elements, the process proceeds to the code regenerating unit 105 in FIG. 1 and the processing of the data arrangement optimizing unit 104 is terminated.

Next, the intermediate program 700 of FIG. 7 generated by the code generation means 103 by the code regenerating means 105 of FIG. 1 and the memory type table of FIG. 8 generated by the data arrangement optimizing means 104 of FIG. Based on C. 816, the element 814 of the memory type table C... 816 and the element 817 of the memory type table C.
5 in the "X" memory and regenerate the code of the assembler description program. FIG. 9 is an explanatory diagram showing an output example of the assembler description program. The Y memory data arrangement 901 in FIG. 9 is the result of arrangement in the “Y” memory, and the X memory data arrangement 902 is the result of arrangement in the “X” memory. Also, the determined Y memory data arrangement 90
1 and X memory data arrangement 902, a parallel instruction A... 904 and a parallel instruction B... 905 that can generate a parallel instruction generate a parallel instruction, and an access instruction 903 that cannot generate a parallel instruction includes a parallel instruction. An access instruction is generated without generating it. As a result, the assembler description program 110 of FIG. 1 is generated and stored in the auxiliary storage device 12.

In the above description of the operation of the compiling device of the present invention, an example of inputting the source program 601 of FIG. 6 and generating an assembler description program has been described, similarly to the description of the operation of the conventional compiling device. A comparison is made between the assembler description program 1108 of FIG. 11 generated by the compiling device according to the prior art and the assembler description program 900 of FIG. 9 generated by the compiler according to the present invention. As a result, the execution steps of the assembler description program 1108 in FIG. 11 generated by the compiler according to the prior art are 614 steps in the entire program, whereas the execution steps of the assembler description program 900 in FIG. Is 464 steps in the whole program, and generates a code whose execution speed is about 1.32 times faster.

[0053]

As described above, according to the compiling apparatus and the compiling method of the present invention, data defined in a source program is arranged and parallelized so that parallel instructions can be generated in the order of the instruction code having the largest number of executions. Since the instruction is generated, there is an effect of generating a code of an assembler description program with high code generation efficiency, particularly, high execution speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration and an operating environment of a first embodiment of a compiling device of the present invention.

FIG. 2 is an explanatory diagram showing an example of a processor configuration targeted by the compiling devices of FIGS. 1 and 10;

FIG. 3 is a flowchart showing a data arrangement optimizing means of the compiling device of FIG. 1;

FIG. 4 is an explanatory diagram showing a configuration of a parallel instruction execution count table and a memory type table of FIG. 1;

FIG. 5 is a flowchart showing a processing procedure in a data arrangement optimizing means of a second embodiment of the compiling device of the present invention.

FIG. 6 is an explanatory diagram showing an example of a source program input to the compiling device of FIGS. 1 and 10;

FIG. 7 is an explanatory diagram showing an example of an intermediate program output by the compiling device of FIG. 1;

8 is an explanatory diagram showing an example of a change in specific setting contents of a parallel instruction execution count table and a memory type table in the processing procedure of FIG. 3;

FIG. 9 is an explanatory diagram showing an example of an assembler description program output by the compiling device of FIG. 1;

FIG. 10 is a block diagram showing the configuration and operating environment of a conventional compiling device.

11 is an explanatory diagram showing an example of an assembler description program output by the compiling device of FIG. 10;

[Explanation of symbols]

11, 101 Compiling device 12, 102 Auxiliary storage device 101, 1001 Lexical analysis means 102, 1002 Syntax analysis means 103, 1004 Code generation means 104 Data layout optimization means 105 Code re-generation means 106, 1005, 601 Source program 107, 700 Intermediate program 108,401,801 Parallel instruction execution count table 109,405, Memory type table 110,1006,900 Assembler description program 201 Memory configuration 202 Instruction memory 203 Data memory X 204 Data memory Y 205 General-purpose register 206 Data Pointer register 207 Data pointer register syntax 208 Address setting instruction syntax 209 Access instruction syntax 210 Increment instruction syntax 21 Parallel instruction syntax 212 Access field X 213 Access field Y 302 to 318, 501 to 516 Processing step 402 DP register pseudonym A 403 DP register pseudonym B 404 Total loop count 406 DP register pseudonym 407 Memory type 602 Data definition statement 603 Product outside loop Sum operation processing 604 Product-sum operation processing during 50 loops 605 Product-sum operation processing during 100 loops 701 Clear instruction 702 Parallel instruction A 703 Loop instruction A 704 Parallel instruction B 705 Loop end instruction A 706 Loop instruction B 707 Parallel instruction C 708 Loop end instruction B 802-804, 806-808, 810-812, 8
14 to 815,817 elements 805 Memory type table A 809 Sorted parallel instruction execution count table 813 Memory type table B 816 Memory type table C 901 Y memory data arrangement 902 X memory data arrangement 903 Access instruction 904 Parallel instruction A 905 Parallel instruction B 1003 Data arrangement means 1101 Y memory data arrangement 1102 Address setting instruction A 1103 Access instruction A 1104 Address setting instruction B 1105 Increment instruction B 1106 Address setting instruction C 1107 Increment instruction C 1108 Assembler description program 1109 Operation instruction A 1110 Operation instruction B 1111 Operation Instruction C

──────────────────────────────────────────────────続 き Continuation of the front page (56) References “Electronic Information and Communication Engineers Autumn Meeting 1992 Collection”, p. 1-104-105 "Proceedings of the 1990 IEICE Spring Conference," p. 1-212 “IEICE Technical Report”, Vol. 94, no. 121 (DPS94 43-60) P. 83-90 (58) Fields surveyed (Int. Cl. ⁶ , DB name) G06F 9/45

Claims (4)

(57) [Claims] 1. A lexical analyzer for reading a source program stored in an auxiliary storage device into read lexicals, and a lexical analyzer for recognizing a lexical analyzed syntax by the lexical analyzer. Determine the location of the data to be used, generate an assembler description program based on the analysis result of the syntax analysis means and the location,
In the compiling device for storing in the auxiliary storage device, when the program instruction is a parallel instruction for simultaneously accessing data of two independent address space memories, a provisional destination of each of the data is determined, and an analysis by the syntax analysis unit is performed. Code generating means for generating an intermediate program based on a result and the temporary placement destination; and referring to the parallel instruction and the loop instruction in the intermediate program, from the number of parallel instruction references and the number of loops as a parallel instruction execution number for each parallel instruction. A memo for calculating the total number of loop times and identifying each of the independent address space memories.
A data type optimizing means for generating a memory type table for selecting and registering a re-type for each of the temporary allocation destinations in the order of the number of times of parallel instruction execution, and optimizing data allocation; and the intermediate program and the memory type A code regenerating means for regenerating code based on a table, generating the assembler description program, and storing the program in the auxiliary storage device. 2. The apparatus according to claim 1, wherein the code generation unit includes a unit that assigns a data pointer register pseudonym as a name of a data pointer register that specifies data accessed by the parallel instruction and specifies the temporary placement destination. The compiling device according to claim 1. 3. A lexical analysis step of decomposing a source program stored in an auxiliary storage device into a read lexical,
A syntax analysis step of recognizing a syntax lexically analyzed by the lexical analysis step, determining a location of data accessed by a program instruction, and assembler description program based on the analysis result of the syntax analysis step and the location. Wherein the program instruction is a parallel instruction for simultaneously accessing data in two independent address space memories, a temporary destination of each of the data is determined, and the syntax A code generation step of generating an intermediate program based on an analysis result of the analysis means and the temporary placement destination; and a parallel processing for each of the parallel instructions based on a parallel instruction reference count and a loop count by referring to the parallel instruction and the loop instruction in the intermediate program. calculates the loop count accumulated as an instruction execution count, each Note identifies the stand address space memory
Generates a memory type table for registering by selecting re type for each of the temporary placement destination large instruction order of the parallel instruction execution count, and data placement optimization step of optimizing the data arrangement, said intermediate program and the memory type Regenerating code based on a table to generate the assembler description program and storing the program in the auxiliary storage device. 4. The code generating step includes a step of assigning a data pointer register pseudonym as a name of a data pointer register designating data to be accessed by the parallel instruction and designating the temporary placement destination. The compiling method according to claim 3.