JP2937704B2 - Delay fluctuation absorption buffer memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory control system, and more particularly to a delay fluctuation absorbing process required for transmitting CBR (constant bit rate) information using a packet-like communication technology (for example, ATM communication). The present invention relates to a delay fluctuation absorbing buffer memory control method capable of recovering from underflow and overflow of a buffer memory.

[0002]

2. Description of the Related Art As an example of a delay fluctuation absorbing process for realizing a cell segmentation / reassembly function (hereinafter referred to as CLAD) of CBR information in an ATM communication network, there is a (k + 1) cell buffering system. (For example, Uematsu and Ueda: "Study of STM signal transmission method using ATM network", IEICE Technical Report, IN91-2, pp. 7-12 (19)
In this method, the delay amount is set to the maximum delay amount (for example, 10 ⁻ⁿ or less) such that the occurrence probability becomes sufficiently small under certain conditions (values such as the cell usage rate and the number of passing queues). Assuming that Q _max and T are cell transmission intervals of the transmitting-side CLAD (that is, cell reading intervals from the delay fluctuation absorbing buffer), (k +
1) Reading from the buffer is started after arrival of cells (where k is the minimum integer satisfying kT ≧ Q _max ). FIG. 2 shows a configuration example of a conventional delay fluctuation absorbing buffer memory control method. As the buffer memory 2 for absorbing delay fluctuation, a memory capable of storing data corresponding to 2k cells is used. As a result, the amount of delay at the start of reading becomes Q
If it is less than or equal to _max , the probability of occurrence of overflow in the buffer memory 2 is zero. The underflow occurrence probability is the worst value (in the case where the amount of delay at the start of reading is minimum) is 10
⁻ⁿ .

[0003]

In the (k + 1) buffering system described above, control of the process from the initial state to the steady state is considered. However, in practical use, overflow and underflow occur in the buffer memory due to other factors. It is necessary to take into account the case in which

[0004]

According to the buffer memory control method of the present invention, a packet received from a communication network for performing communication by packetizing CBR (constant bit rate) information is temporarily written into a buffer memory, and is written into a fixed bit rate. A buffer processing unit that reads out at a rate and reproduces the original CBR information performs a write or read phase shift or initializes the buffer memory when an overflow or underflow occurs in the buffer memory. I do.

[0005]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. Input data 1 and a write clock 3 for controlling the write timing of input data 1 are input to buffer memory 2. A write address 10 for designating a data storage position in the buffer memory 2 is taken out from a write address counter 4 that operates in a step-by-step manner by a write clock 3 and applied to the buffer memory 2.

The read clock 6 is connected to the buffer memory 2 and controls the read timing of the written data.
A read address 11 for designating a data read position is taken out from a read address counter 9 which operates in a stepwise manner by a read clock 6 and applied to the buffer memory 2. The read address counter 9 is turned on / off by a read start control signal 5 in a stepping operation. When performing a process of changing the write address or the read address of the buffer memory 2 by a fixed amount (hereinafter referred to as a phase shift process),
The capacity of the buffer memory 2 is set to an integral multiple of the frame length of the user information.

The write address 10 and the read address 11 are also input to the phase difference detecting section 12, and the phase difference detecting section 12 detects an overflow judgment result 13 and an underflow judgment result 14 detected from the difference between the two addresses. Is output. Of the two determination results, the overflow determination result 13 is connected to the direct read address counter 9, and the underflow determination result 14 is connected to the read address counter 9 via the underflow protection unit 15. Also, the underflow protection unit 1
5 and the overflow determination result 13 are as follows:
The initialization protection unit 17 is connected to the initialization protection unit 17.
Outputs the initialization control signal 18 when the above-described determination results (13, 14) are repeated a predetermined number of times or when the recovery is not performed after a predetermined time.

Next, the operation of this embodiment will be described.

First, in a normal state, each time a cell arrives, the write address counter 4 steps up by the write clock 3, and the data write address 10 to the buffer memory 2 changes. On the other hand, on the read side, after a certain number of cells have arrived or a certain amount of data has been written (approximately 1/2
, The read address counter 9 starts the stepping operation, and the read address 11 changes according to the clock speed of the CBR information 7 to be reproduced (that is, the clock speed of the read clock 6).

When an underflow occurs, the write speed is relatively reduced due to, for example, network congestion, lower layer failure, malfunction of the buffer control unit, etc., and the read address 11 of the buffer memory 2 overtakes the write address 10. In this case, the phase difference detector 12 determines that the buffer memory 2 is underflowed, and outputs an underflow determination result 14.
The underflow determination result 14 is the underflow protection unit 1
If it is determined in step 5 that the occurrence occurs at a certain frequency or higher, the read address counter 9 performs a process of delaying the read address 11 by an integral multiple of the frame length of the user information.
Further, when the initialization protection unit 17 determines that this processing has occurred at a certain frequency or higher, it issues an initialization control signal 18 to initialize the buffer control.

When an overflow occurs, for example, at the start of reading, there is network congestion, lower layer failure, and thereafter the delay amount decreases, or the writing speed relatively increases due to a malfunction of the buffer control unit and the like. When the write address 10 of the memory 2 exceeds the read address 11, the phase difference detector 12 determines that the buffer memory 2 overflows, and outputs an overflow determination result.
In response to the overflow determination result 13, the read address counter 9 performs a process of advancing the read address 11 by an integral multiple of the frame length of the user information (phase shift process).
Further, when the initialization protection unit 17 determines that this processing has occurred at a certain frequency or higher, the buffer control is initialized.

The processing at the time of underflow or overflow of the buffer memory 2 described above can be changed according to required characteristics. The nature of underflow and overflow due to the delay variation is as follows.

The amount of delay at the start of reading is within the design range (0 to 0).
In the case of Q _max ) The underflow occurrence probability is larger than zero and less than the allowable range (10− ⁿ ). The underflow returns autonomously. The overflow occurrence probability is zero. The amount of delay at the start of reading is out of the design range. In case of (Q _max or more) ・ The underflow occurrence probability is larger than zero and smaller than the allowable range (10 ⁻ⁿ ) ・ The underflow returns autonomously ・ The overflow occurrence probability is not zero ・ Overflow continues That is, the probability of occurrence of underflow is greater than zero in any case and is within the allowable range at the time of design. On the other hand, the probability of occurrence of overflow is normally zero, but depending on the amount of delay at the start of reading, it may be other than zero, sometimes very large, or may occur continuously.

From the above properties, when it is desired to reduce the circuit scale, it is possible to recover from a continuous failure only by processing the overflow. The simplest configuration is
There is a configuration in which buffer initialization is unconditionally performed at the time of overflow.

If the capacity of the buffer memory is large and a sufficient amount of cells can be stored, the probability of occurrence of both overflow and underflow can be sufficiently reduced. In this case, to simplify the buffer control hardware,
There is also a method of unconditionally initializing a buffer at overflow and underflow.

In the overflow processing, if it is desired to minimize the frame synchronization of the user information, which is an alarm (hereinafter referred to as a secondary alarm) which is generated at the downstream side, as much as possible, at the same time as the overflow occurs, What is necessary is just to perform a shift process. As a result, it is possible to recover from the overflow while suppressing the secondary alarm to only the payload error of the user information. In the case of overflow due to delay variation, the occurrence probability can be made zero by repeating the phase shift processing.

When the ratio between the memory capacity and the amount of phase shift is large, when an extremely large overflow occurs, it is more efficient to perform initialization than to perform recovery by repeating the phase shift. Be shorter. Therefore,
If the phase shift processing is executed continuously for a fixed number of times, or if the overflow does not recover after a fixed time after the execution of the phase shift processing, initialization control may be performed.

On the other hand, in the case of an underflow, the occurrence probability does not usually exceed the allowable range (10 ⁻ⁿ ).
The phase shift processing or initialization is not performed simultaneously with the occurrence of the underflow, and the phase shift processing is performed after a certain protection period. As a result, the probability of occurrence of underflow can be reduced.

Depending on the magnitude relationship between the memory capacity and the amount of phase shift, if a very large underflow occurs, it is better to perform initialization than to restore by repeating the phase shift. The time may be short. For this reason, when the phase shift processing is continuously performed a fixed number of times, or when the underflow does not recover after a predetermined time after the execution of the phase shift processing, the initialization control may be performed.

If the phase shift processing is executed continuously for a fixed number of times, or if the underflow does not recover after a certain period of time after the execution of the phase shift processing, there is a possibility of a failure in the transmission path. Perform control. Table 1 exemplifies combinations of required items and corresponding processes.

[0022]

[Table 1]

[0023]

As described above, according to the present invention, when an overflow or an underflow occurs in a buffer that absorbs a delay variation, a recovery process can be effectively performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional system.

[Description of Signs] 1 Input data 2 Buffer memory 3 Write clock 4 Write address counter 5 Read start control signal 6 Read clock 7 CBR (constant bit rate) signal 9 Read address counter 10 Write address 11 Read address 12 Phase difference Detection unit 13 Arbor flow judgment result 14 Underflow judgment result 15 Underflow protection unit 16 Underflow protection unit output signal 17 Initialization protection unit 18 Initialization control signal

Continuing on the front page (72) Inventor Beni Murakami 5-7-1 Shiba, Minato-ku, Tokyo Within NEC Corporation (72) Inventor Jin Agematsu 1-6-1 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Hiromi Ueda 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Hiroshi Takeo 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Corporation (72) Invention Person Kazuo Iguchi 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-6-46084 (JP, A) JP-A-61-260733 (JP, A) JP-A-1-280286 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 13/08 H04L 12/56

Claims (5)

(57) [Claims] A buffer processing for temporarily writing a packet received from a communication network for performing communication by packetizing CBR (constant bit rate) information into a buffer memory, reading out the packet at a constant bit rate, and reproducing the original CBR information. When the buffer memory overflows or underflows, the write or read phase shift is performed by the
Or delay fluctuation for initializing the buffer memory
An absorption buffer memory control method, wherein a size of the buffer memory is determined by a frame length of user information.
When the overflow occurs, the buffer
Write the address of the write or read side of the memory to the user information.
Process in units of an integral multiple of the report frame length.
After a certain number of consecutive executions, or
The overflow does not recover after a certain period of time
Is a delay fluctuation absorbing buffer memory control method , wherein the buffer memory is initialized . 2. A buffer process for temporarily writing a packet received from a communication network for performing communication by packetizing CBR (constant bit rate) information into a buffer memory, reading the packet at a constant bit rate, and reproducing the original CBR information. A delay fluctuation absorbing buffer memory control method for performing a write or read phase shift or initializing the buffer memory when an overflow or an underflow occurs in the buffer memory; Is an integral multiple of the frame length of the user information, and if the buffer memory underflow occurs at a certain frequency or more, the address of the write side or the read side of the buffer memory is a unit of an integral multiple of the frame length of the user information. Delay fluctuation absorbing buffer memory characterized by performing a process of changing by a delay Your system. 3. When an overflow occurs in the buffer memory, a process of changing a write-side or read-side address of the buffer memory in a unit of an integral multiple of a frame length of user information is performed, and the process is repeated a predetermined number of times. 3. The delay fluctuation absorbing buffer memory control method according to claim 2 , wherein the buffer memory is initialized when the overflow does not recover after a certain period of time after the execution or the execution of the processing. 4. A buffer process for temporarily writing a packet received from a communication network for performing communication by packetizing CBR (constant bit rate) information into a buffer memory, reading the packet at a constant bit rate, and reproducing the original CBR information. A delay fluctuation absorbing buffer memory control method for performing a write or read phase shift or initializing the buffer memory when an overflow or an underflow occurs in the buffer memory; Is an integral multiple of the frame length of the user information, and if an underflow of the buffer memory occurs at a certain frequency or more, the address on the write or read side of the buffer memory is set to an integral multiple of the frame length of the user information. Perform a process of changing a fixed amount in units, and execute the process continuously for a fixed number of times. After, or process if the underflow after a predetermined time after execution does not recover, delay variation absorbing buffer memory control method and performing initialization of the buffer memory. 5. When overflow occurs in the buffer memory, a process of changing a write side or a read side address of the buffer memory in a unit of an integral multiple of a frame length of user information is performed, and the process is performed continuously for a fixed number of times. 5. The delay fluctuation absorption buffer memory control method according to claim 4, wherein the buffer memory is initialized when the buffer overflow does not recover after a certain time after the execution or the execution of the processing.