JP2935283B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit having an open drain type output circuit used for an information processing device.

[0002]

2. Description of the Related Art Conventionally, as an interface circuit in a semiconductor integrated circuit, a TTL circuit in which logic "0" and logic "1" of binary information correspond to voltage levels of about 0V and + 3.5V, etc., is widely used. Have been. However, in order to transfer a signal at high speed, a method of reducing the voltage amplitude of the signal and terminating the signal at both ends of the transmission line with a characteristic impedance in consideration of a load has been considered.
(For example, Ref .: The Proposed IEE 896 Future Bus, A Solution Two
The Bus Driving Problem (The Pro
Posted IEEE 896 Futurebus-
A solution to the Bus Divi
ng Problem), August 1984).

FIG. 4 is a circuit diagram showing a conventional semiconductor integrated circuit output circuit described in the above-mentioned document and a system for performing signal transmission using a plurality of semiconductor integrated circuits of this kind.
A plurality of semiconductor integrated circuits 100-1 to 100-1 are connected to the signal line 200.
00-n is connected, and both ends of the signal line 200 are connected to a terminating power supply (voltage Vt) via a terminating resistor Rt.

The semiconductor integrated circuit 100-1 has an input circuit 20, a diode D1, and an output transistor Q connected to a terminal Tm.
1, an output circuit 10 composed of a Schottky barrier diode D2 is connected. The terminating power supply voltage Vt is +2 V, and the terminating resistor Rt is a resistance value of a characteristic impedance in consideration of the load of the signal line 200, which is usually about 30 to 50Ω.

When the output transistor Q1 of the bipolar transistor is off, the input impedance of the input circuit 20 is high, so that the terminal Tm is at the voltage level of the terminal power supply voltage Vt, ie, + 2V. Output transistor Q
1 is on, the level of the terminal Tm is (diode D1
) + (The voltage between the base and the emitter of the output transistor Q1) − (the voltage of the Schottky barrier diode D2), and becomes approximately + 1V. At this time, the output signal O
FIG. 5 shows a waveform diagram of the UT.

This circuit is an example in which the output circuit 10 is constituted by using bipolar transistors. Recently, however, the spread of semiconductor integrated circuits using MOS transistors has been remarkable, and signal transmission of this kind of semiconductor integrated circuit has been performed at high speed. To achieve this, an output circuit using MOS transistors is required.

FIG. 6 shows an example of a semiconductor integrated circuit having an output circuit using MOS transistors.

In this circuit, the drain-in of the output transistor M1 is connected to the terminal To, the source is connected to the ground potential point, and the gate receives a signal IIN from the internal circuit via the CMOS inverter 1. I have.

[0009]

In this conventional semiconductor integrated circuit, when the output circuit is constituted by MOS transistors, the output transistor M1 is directly connected to the terminal To, so that the variation in the ON resistance of the MOS transistors is large. In addition, there is a problem that the low-level variation of the output signal OUT becomes large, and the influence of noise on other signals due to an increase in delay time and a large voltage amplitude in consideration of the variation becomes extremely large.

An object of the present invention is to provide a semiconductor integrated circuit which is constituted by MOS transistors, can reduce the amplitude of an output signal, can reduce a delay time, and can eliminate adverse effects on other signals. It is in.

[0011]

A semiconductor integrated circuit according to the present invention has a terminal for inputting and outputting a signal having a binary logic level, a drain connected to the terminal, a source connected to a reference potential point, and an internal circuit connected to a gate. MOS to input signal from output stage of
Type output transistor, an input terminal is connected to the terminal, an output terminal is connected to the gate of the output transistor, and a signal from an output stage of the internal circuit is at a level at which the output transistor is turned on. An output voltage control circuit for controlling the voltage of the gate of the output transistor so that the level becomes a preset level.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, a MOS transistor M1
1 and M12, a CMOS inverter 1 for inverting and amplifying a signal IIN from an internal circuit, an output terminal To, a drain connected to the output terminal To, a source connected to a reference potential point (ground potential point), and a gate connected to the CMOS inverter. Output transistor M for inputting the output signal of
1, a first MOS transistor M21 having a gate connected to the drain of the output transistor M1, a source connected to the reference potential point, and having a predetermined threshold voltage, and one end connected to this MOS transistor M21.
A resistor R1 connected to the drain of the transistor M21 and the other end to which the power supply voltage Vcc is applied, a gate connected to one end of the resistor R1, the drain of the MOS transistor M21, a source connected to the reference potential point, and a drain connected to the output transistor M1. Second MOS transistor M2 connected to the gate
1 and the voltage of the output terminal To is the MOS transistor M
21 is lower than the threshold voltage of MOS transistor M.
When the MOS transistor 21 is turned off, the MOS transistor M22 is turned on, and the P-channel MO of the CMOS inverter 1 is turned off.
A voltage determined by the ON resistance of the S transistor M11 and the ON resistance of the MOS transistor M22 is supplied to the gate of the output transistor M1, and the output terminal To is output when the output signal of the CMOS inverter 1 is at a level at which the output transistor M1 is turned on. And an output voltage control circuit 2 for controlling the level of the output voltage to a preset level.

Next, the operation of this embodiment will be described.

The output signal of the CMOS inverter 1 has a low level and a high level of 0V and + V, respectively, when the MOS transistor M22 in the output stage of the output voltage suppressing circuit 2 is off.
cc (usually + 5V). The N-channel output transistor M1 is off when the voltage level of the gate is 0V, and an output signal OUT of the external terminal power supply voltage Vt, that is, + 2V appears at the output terminal To.

The output of the CMOS inverter 1 is at a high level,
That is, when the P-channel MOS transistor M11 is on, the output transistor M1 is on and the voltage level of the output terminal To decreases.

The voltage at the output terminal To is the output voltage suppression circuit 2
MOS transistor M21 is turned off from on,
Since the power supply voltage Vcc is applied to the gate of the N-channel MOS transistor M22 through the resistor R1,
The transistor M22 turns on.

The voltage level at the gate of the output transistor M1 is an intermediate value between 0V and + 5V (Vcc) determined by the on-resistance ratio of the P-channel MOS transistor M11 and the N-channel MOS transistor M22.

The output voltage suppression circuit 2 controls the voltage level of the gate of the output transistor M1 so that the low level of the output terminal To becomes a predetermined value, in this example, the threshold voltage of the MOS transistor M21. The current driving capability of the output transistor M1 is adjusted.

Therefore, the low level of the output terminal To is not influenced by the on-resistance of the output transistor M1 and is always determined by the threshold voltage of the MOS transistor M21. Can be done.

FIG. 2 shows a waveform diagram of the output signal OUT according to this embodiment.

In the conventional example shown in FIG. 6, the low level is set lower than the low level Va of the present invention as shown by the broken line in FIG.

This is because the low level of the conventional example is expected to fluctuate due to variations in the on-resistance of the output transistor M1.

On the other hand, in the present invention, since the low level Va can be determined with high accuracy, the level difference (amplitude) between the high level Vt and the low level Va can be reduced. Therefore, the delay time of a signal can be reduced, and adverse effects such as noise on other signals can be eliminated.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the output voltage control circuit 2a
Resistors R4 and R5 forming a circuit for generating reference voltage Vr
The first input terminal is connected to the drain of the output transistor M1 and the reference voltage Vr is input to the second input terminal. If the voltage at the drain of the output transistor M1 exceeds the reference voltage Vr, the level is low. MOS transistors M23 forming a differential circuit for outputting a high level signal,
M24, the resistors R3 and R4, and the drain are connected to the gate of the output transistor M1. When the output signal of the differential circuit is at a low level, the output is turned off, and when the output signal is at a high level, the output is turned on. The configuration includes a MOS transistor M25 for supplying a predetermined voltage to the gate of the output transistor M1 and a MOS transistor M26 for level shift, in addition to the transistor M11.

In this embodiment, since the low level of the output signal OUT is determined by the reference voltage Vr generated by the resistors R4 and R5, the low level of the output signal OUT can be determined more accurately than in the first embodiment. It can be controlled to a constant value.

[0029]

As described above, according to the present invention, the output signal is input and compared with the threshold voltage or the reference voltage, and the voltage supplied to the gate of the output transistor is controlled based on the comparison result, so that the output transistor By providing an output voltage control circuit for controlling the level of the output signal of the ON state, the level of the output signal of the output state of the ON transistor is accurately and stably maintained at a constant value. Therefore, the amplitude of the output signal can be reduced, the delay time of the signal can be reduced, and the adverse effect of other signals due to noise or the like can be eliminated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram of an output signal for explaining the operation and effect of the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram when a first example of a conventional semiconductor integrated circuit and a plurality of semiconductor integrated circuits of the same type are used.

5 is a waveform diagram of an output signal of the semiconductor integrated circuit shown in FIG.

FIG. 6 is a circuit diagram of a second example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

Reference Signs List 1 CMOS inverter 2, 2a output voltage control circuit 10 output circuit 20 input circuit 100-1 to 100-n semiconductor integrated circuit 200 signal line D1 diode D2 Schottky barrier diode M1 output transistor M11, M12, M21 to M26 MOS transistor Q1 output transistor R1 to R5 Resistance Rt Termination resistance

Claims (3)

(57) [Claims] 1. A MOS type terminal for inputting and outputting a signal having a binary logic level, a drain connected to the terminal, a source connected to a reference potential point, and a gate for inputting a signal from an output stage of an internal circuit. An output transistor, an input terminal is connected to the terminal, an output terminal is connected to the gate of the output transistor, and a signal from an output stage of the internal circuit is at a level at which the output transistor is turned on. An output voltage control circuit for controlling a voltage of a gate of the output transistor so that the output transistor has a predetermined level. 2. The output stage of the internal circuit is formed by a CMOS type inverter, and an output voltage control circuit has a gate connected to a drain of the output transistor, a source connected to a reference potential point, and a predetermined threshold voltage. A first MOS transistor, a resistor having one end connected to the drain of the first MOS transistor and being supplied with power from the other end, a gate connected to one end of the resistor, a source connected to the reference potential point, and a drain connected to the reference potential point. A second MOS transistor connected to the gate of the output transistor, and when the voltage at the terminal is lower than the threshold voltage of the first MOS transistor, the second MOS transistor is turned off. MOS transistors are turned on, and the CMO
2. The semiconductor integrated circuit according to claim 1, wherein the circuit determines the voltage of the gate of the output transistor based on the ON resistance of the MOS transistor of the S-type inverter and the ON resistance of the second MOS transistor. 3. An output voltage control circuit, comprising: a circuit for generating a reference voltage; a first input terminal connected to a drain of the output transistor; a second input terminal receiving the reference voltage, and a drain of the output transistor. And a differential circuit for outputting a signal having a first level when the voltage exceeds the reference voltage and a second level when the voltage does not exceed the reference voltage, and an output signal of the differential circuit, wherein a drain is connected to the gate of the output transistor. Is the first
2. The semiconductor integrated circuit according to claim 1, further comprising: a MOS transistor which is turned off when said level is at a predetermined level and turned on when said level is at a second level, and supplies a predetermined voltage to a gate of said output transistor. .