JP2930770B2 - Design method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LS using a computer.
More particularly, the present invention relates to a method of designing a semiconductor integrated circuit capable of optimizing an operation characteristic of a circuit.

[0002]

2. Description of the Related Art A gate array system (also called a master slice system) has been widely known as a method of designing a semiconductor integrated circuit.

According to this method, basic cells and input / output cells consisting of a fixed number of transistors are regularly arranged on a master chip, these gates are appropriately wired to meet the specifications of a user, and an LSI having a desired function is formed. It is completed.

In general, a wafer before the wiring process in which basic cells are simply arranged is called a master wafer, and laying wiring on the wafer and forming a dedicated circuit as an individual LSI is called personalization. .

In such a gate array type LSI, by selecting an appropriate number of the above-described basic cells and arranging them, logic cells such as inverters, NANDs, and flip-flops (hereinafter abbreviated as cells) are formed. It can be realized freely. Many of these standard cell wiring patterns (referred to as macro cells) are all prepared as a library, and by selecting and using them appropriately, efficient design can be performed. I have.

FIG. 8 is an explanatory diagram showing an example of a chip constituting a master wafer.

As shown in FIG. 1, the outer peripheral portion of the chip 81 is an input / output cell arrangement area 82, and the inside surrounded by the input / output cell arrangement area 82 is an array area 8
It is 3. Although not shown, a plurality of input / output cells are arranged in the input / output cell arrangement area 82.

[0008] The user needs a required number of macrocells of the required number in the array area 8 according to the circuit of the LSI to be realized.
3 and wiring between terminals on the cell in accordance with the circuit connection information, thereby enabling personalization.

At this time, in the gate-layout type gate array type LSI, all locations in the array area 83 can be used as an arrangement area, and cells can be placed at arbitrary positions. The wiring between the terminals is performed by using the area where the cell is not placed and the area where the wiring can be laid on the cell.

By the way, it is difficult to design by hand in the arrangement and wiring processing of a highly integrated and large scale gate array, and a layout method using a computer is usually employed.

In this layout, it is required to obtain a result of arrangement and wiring with a high degree of integration, and it is necessary to guarantee the operation as specified by the user. Among these, many methods have been proposed as the former for improving the degree of integration, and many of them have a proven track record. However, in cases where circuit operation assurance and a high operating frequency are required in addition to high integration, sufficient optimization of the layout can be achieved by the conventionally proposed design apparatus or design method. Absent.

In general, in order to improve the operating frequency of a circuit, it is effective to optimize the operation performance of a signal path (hereinafter referred to as a critical path) having a small delay time margin with respect to a required specification of a maximum delay time. is there. Usually, the characteristics of the critical path are determined at an early stage of the layout, that is, a floor plan for determining the position of a block composed of a plurality of functionally integrated cells such as ROM / RAM on a chip and a detailed position of the cell. This is almost determined at the stage of the placement process to be performed, and it is unlikely that it will change greatly during wiring. Therefore, it is necessary to give due consideration to the operation characteristics of the circuit at the stage of arranging the cells.

As a method of optimizing the operation characteristics, a net (a wiring route between cells) or a path which becomes an operation constraint is extracted based on the result of the timing analysis of the circuit, and weights and processing priority are given to these. A method of performing layout by adding degrees has been proposed (AEDunlop, et al, “Chip Layout Optim
ization Using Critical Path Weighting ", Proc. 21stDA
C, pp. 133-136, 1984.).

However, in this method, a constraint is added to each net, and it is difficult to optimize the entire critical path. For this reason, since the path route is determined while avoiding other wiring, the bending and meandering of the path cannot be prevented, and the path route becomes complicated.

On the other hand, a wiring area is defined by two cut lines.
In the placement algorithm based on the two-part improvement, the constraints on the wiring length of the net are determined based on the timing analysis. A method has been proposed in which a comparison is made between the size of a region and a weight corresponding to the magnitude relationship between the two is added to the net (Yasushi
Ogawa, et al, "Efficient Placement Algorithms Optimi
zing Delay for High-Speed ECL Masterslice LSI's ", Pr
oc. 23rd DAC, pp. 404-410, 1986.).

However, in this method, when the critical path is composed of many nets, the number of constraints becomes extremely large, so that the performance of the division improvement is reduced and the degree of integration is not significantly impaired. Also, in this case, since the constraint condition is added to each net, it is difficult to optimize the entire critical path mutually restricted.

Similarly, as an example in which the wiring length constraint of a critical net given from the outside is incorporated into the MIN-CUT placement method, (Masayuki Terai, et al, "A New Min-Cu
t Placement Algorithm for Timing Assurance Layout
Design Meeting Net LengthConsttaint ", Proc.DAC, pp.9
6-102, 1990.). However, since the multiple nets that compose the path are handled separately, there is the above-mentioned problem.

FIG. 9 is a diagram for explaining a method of laying out by adding weights and priorities to the nets and paths described first.

In FIG. 1, two paths Pa and Pb are drawn, and it is assumed that the cell a2 is subject to both constraints. The rhombic regions Ra and Rb are regions equidistant in time from the cells a1 and b1. At this time, the cell a2 must be within the area Rb when viewed from the path Pb, and must be positioned within the area Ra when viewed from the path Pa. That is, the cell a2 must be located in the region R to simultaneously satisfy the two timing constraints. However, if the weights of the net b12 and the net a12 are set equal, the mechanical equilibrium point (point at which the attractive force is balanced) is G and is not included in the region R.

As described above, in the conventional method, the wiring delay of the net to which the weight is added is reduced by shortening the wiring length of the net, but the required operation characteristics cannot be satisfied reliably. .

Furthermore, in the conventional method, the operation characteristics are always improved for all the critical paths in the chip. Therefore, when a large-scale circuit is handled, it takes a long processing time, and the operation characteristics are reduced. We cannot guarantee.

[0022]

As described above, in the conventional design method, optimization is performed for each net, and optimization of the entire critical path is not performed. For this reason, it was insufficient to improve the operation characteristics.

Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to optimize the entire critical path while considering mutual constraints between the critical paths. It is another object of the present invention to provide a method for designing a semiconductor integrated circuit that can reliably guarantee required operation characteristics.

[0024]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a method for arranging a plurality of logic cells on a semiconductor chip and wiring between the logic cells. A signal path with a small delay time margin is extracted, the upper limit value of the delay time allowed for the extracted signal path is distributed to each net constituting the signal path, and the upper limit value of the distributed delay time is determined. The upper limit value of the wiring length allowed for each net is determined based on the upper limit value of the determined wiring length. Determine the optimal existence area of the logic cell that constitutes, determine the arrangement position of the logic cell in this optimal existence area, based on the size of the optimal existence area,
It is characterized in that the priority of the wiring processing of the net constituted by the logic cells arranged in the optimum existence area is determined, and the wiring processing between the logic cells is performed based on the determined priority.

[0025]

According to the present invention, first, all the critical paths in the integrated circuit are extracted, and the upper limit value of the delay time allowed for this path is evenly distributed to each net. The upper limit value of the wiring length allowed for each net is determined based on the upper limit value of the distributed delay time. From the determined upper limit of the wiring length of the net, as seen from each of the input side and output side of this path,
The optimum existence area of the logic cell constituting the net is obtained. Then, the arrangement position of the logic cell is determined at the center of gravity of the optimum existence area. Further, the priority of the wiring processing of the net constituted by the logic cells arranged in the optimal existence area is set to be higher in the order of the smallest optimal existence area, and the wiring processing is performed from the net to which the higher priority is added.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a hardware configuration of an automatic cell placement apparatus which realizes a method of designing a semiconductor integrated circuit according to the present invention.

As shown in FIG. 1, this apparatus is controlled by a CPU 100 mainly composed of a microprocessor. The system bus 1 of the CPU 100
01, a video RAM 102, a CRT controller 1
03, a magnetic storage device 105, a RAM 106, a keyboard 107, and a pointing device 108 are connected.

The video RAM 102 serves as a storage area for data to be displayed on the CRT 104. The data is stored in the CRT controller 103 under the control of the CPU 100.
And is finally displayed on the screen of the CRT 104.

The magnetic storage device 105 includes a hard disk,
It is composed of a floppy disk or the like, and stores a library and the like in which various data on the macro cell are described. Further, the magnetic storage device 105 is also used as an input device for programs and data to be loaded into the RAM 106 described later.

The RAM 106 is used as a storage area for application programs, a work area, and the like. As described above, the programs and data are loaded into the RAM 106 from a floppy disk, a hard disk, or the like that forms the magnetic storage device 105.

The keyboard 107 is used for various input operations by the operator. Switching between a batch arrangement mode and a partial arrangement correction mode, which will be described later, is performed by an instruction from the keyboard 107.

The pointing device 108 includes a mouse, a trackball, a light pen, a tablet, and the like, and is used by an operator to specify a specific position on the screen.

FIG. 2 is a flowchart showing a procedure of a wiring process performed by the automatic cell placement apparatus shown in FIG.

The design method according to the present invention includes a batch processing mode (step f) for all critical paths.
7) and a partial processing correction mode (steps f8 to f1) in which only one critical path or one part in the path is performed.
6) Two operation modes are provided. The operator can alternatively select one of these modes by using the keyboard 107.

FIG. 3 shows a CRT 10 during the wiring process.
FIG. 11 is a simplified diagram illustrating a state where a path or a cell is displayed on the screen of FIG.

The wiring process according to the present invention will be described below with reference to FIGS.

When the process is started, various registers and flags in the RAM 106 are initialized by an initial process (step f1).

Next, in order to confirm the current layout state, the operation characteristics of the entire circuit are analyzed, and all the critical paths that restrict the operation of the circuit are extracted (step f2).

At this time, if the layout result has been subjected to the wiring processing, the operation of the circuit is analyzed based on the wiring delay calculated using the internal delay specific to the cell and the actual wiring length.
When the actual wiring length is used, the delay value of the net is the sum of the delay of each wiring layer.

However, if no cells are arranged, the virtual wiring length is calculated based on the cell area Ac, the utility (gate use rate) Ut of the cells on the chip, and the like.
Further, a delay value for each wiring direction is obtained, and the sum thereof defines a net delay. The following equation (1) is an example. tn is the delay value of net n, twx, twy
Is a wiring length-time conversion coefficient, and α is a constant.

[0042]

(Equation 1)

On the other hand, if the delay is the result after the placement and routing, and if the delays of all the extracted critical paths are within the range of the design requirement specification, the processing is completed, but there is a path that does not satisfy the requirement. The processing for improving the operation characteristics is performed as follows (step f3). The processing is also performed when the layout has not been executed.

As shown in FIG. 3, the cells connected to the extracted critical path 9 (shaded portions in the figure) are changed in color so that each path can be recognized, and the layout completed screen of the chip 6 is displayed. 5 and is in a standby state for reading the operation mode (step f4). At this time, although not shown, the cells shared by a plurality of paths on the screen 5 are displayed by the display brightness or the line width and the line type of the cell outer shape are changed, so that the operator can improve the layout. It is displayed so that necessary parts can be easily recognized.

The operator selects an operation mode by operating the keyboard 107 based on the layout information on the entire chip displayed by such a method (step f5). Switching between the batch arrangement mode and the partial arrangement correction mode is performed according to the selected contents (step f).
6).

When the batch arrangement mode is selected, the operation characteristic optimizing layout process, which is a main part of the present invention, is executed with all the critical paths in the chip being processed (step f7).

On the other hand, when the partial arrangement correction mode is selected, the pointing device 108 is operated by the operator.
The process waits until an area is designated by using (steps f8 and f9).

When the lower left point LLP and the upper right point URP of the area where the signal delay time is desired to be improved are designated (step f9 YES), an enlarged screen of the designated area 7 is displayed (step f10). Thereby, critical path 9
Can be known from the macro cell type of each cell constituting.

After that, the system is in a state of waiting for execution of cell addition / change (steps f11, f12, f13). In this state, when the addition / change cell 8 for improving the operation characteristics is selected and the change cell or the insertion position P is designated, the selected cell 8 is arranged at the insertion position P (step f14).

Thereafter, a predetermined addition /
The above processing (steps f11 to f14) is repeated until the operation of ending the change operation is performed.

When a predetermined addition / change operation end operation is performed from the keyboard 107 (step f15YE).
S), the same operation characteristic optimization layout processing as in step f7 is executed, and the final layout state is obtained (step f16).

Next, FIG. 4 shows a detailed flowchart of the layout process for optimizing the operation characteristics (steps f7 and f16), which is a main part of the present invention.

When the layout processing is performed in step f7, the designated area is the entire chip, and when the layout processing is performed in step f16, it is the designated area 7.

When the instruction is executed, layout information on the boundary of the designated area is extracted so that the connection relationship between the subsequent layout processing of the designated area and the layout result of the area other than the designated area does not shift. The information is changed or created (step p1). Specifically, the position of the cell on the boundary side is temporarily fixed, and for the wiring passing on the boundary side, a virtual terminal corresponding to the currently used wiring layer is generated on the boundary side. (Step p2).
Thereafter, all of the wiring paths in the region are deleted except for special wiring such as power supply wiring.

The designated area is divided into pieces of information for each small area divided in a grid (step p3), and layout information such as the current cell belonging to each area is held. Dividing the information in this manner has the advantage that layout information such as the arrangement position of cells indicated by coordinate values can be easily associated with geometric information such as the shape of a signal path and that data access can be speeded up. is there.

Next, all the critical paths in the designated area are extracted (step p4), and if the delay of the path does not fall within the allowable value calculated from the design requirement specification (NO in step p5), the current arrangement state is determined. Improvement is performed (steps p6 to p8). In the placement improvement, first, the optimal existence area where the nets related to all the extracted paths should be placed is obtained as the area constraint condition (step p).
6).

For a net under a plurality of region constraints, a region constraint condition in which all the constraint conditions are superimposed is determined (step p7).

Then, based on the determined region constraint conditions, cell movement or cell exchange is performed so that cells constituting each net are arranged at the center of gravity of the target optimal existence region (step p8).

The placement state is improved in the above steps, and if the delay of all the paths in the designated area can be kept within the allowable value, the placement improvement is terminated and the wiring priority is determined (step p5 YES). And p9).

Further, based on the determined wiring priority, nets are taken out in descending order of the priority, and wiring is performed in the designated area (step p10).
By performing the wiring processing at this time using the conventional maze method, a net having a higher wiring priority can be connected with a shorter wiring path. can do.

Based on the layout result determined in this way, the operation characteristics of the entire circuit are analyzed again (step f2), and it is checked whether the operation of the entire circuit satisfies the design requirements (step f2). f3). If the circuit operation does not satisfy the design specifications, the above procedure is repeated again, and if so, the process ends.

The whole repetition is performed until the layout result satisfies the design requirement specification or until the layout is executed a specified number of times.

The method of determining the priority performed in step p9 will be described below.

The upper limit value of the delay time allowed for each path, which is determined from given design specifications, is evenly distributed to the individual nets constituting the path. The distributed delay time is converted into an upper limit of the allowable wiring length of each net. For example, if the i-th wiring layer is used, the conversion coefficient of the i-th layer is twi, and the wiring length of the i-th layer is wl.
If i, the delay time tn of net n is

[0065]

(Equation 2)

Is as follows. Therefore, if the upper limit value of the delay time of the path is Dp and the number of nets constituting the path is cn,
The constraint of net n is

[0067]

(Equation 3)

Is obtained. This restriction on the wiring length is sequentially determined for each net from both the signal input and output sides in accordance with the flow of the signal of the path.

FIG. 5 is a schematic diagram showing an example of a method of obtaining the area constraint condition in step p6 and a method of determining the cell arrangement position in step p8 in the case of two-layer wiring.

I1 to I4 and O1 to O4 are constraints on nets a12 to a45, respectively. I1 to I4 are restrictions from the input side (cell a1). For example, all cells constituting the net a12 must be located on the left side of I1. On the other hand, O1 to O4 are restrictions from the output side (cell a5). For example, all cells forming the net a45 must be located on the right side of O4.

In this example, cell a2 is composed of nets a12 and a23.
Region constraints I1, O1,
I2 and O2 are satisfied, and the rectangular optimal existence region R1
And R2. Similarly,
The area constraint conditions I2, O2, I3, and O3 for the nets a23 and a34 are also satisfied for a3. However, the cell a4 contains the region constraints I3, O3 on the net a34.
Is satisfied, but does not satisfy the constraint condition O4 regarding the net a45. Accordingly, the position of the cell a4 is shifted to the area where I3 and O4 overlap or exchange with another cell is performed so that the cell a4 falls within the center of gravity of the rectangular optimal existence areas R3 and R4 satisfying the constraint. In other words, the position of the cell directly constituting the path is moved or exchanged with another cell so that the cell exists at the intersection of the constraint conditions of the left and right nets connected to the path.

FIG. 6 is a schematic diagram showing a method of determining a region restriction condition when different restrictions are applied to a plurality of paths performed in step p7.

The cell a2 shown in the figure receives two constraints of paths Pa and Pb at the same time, and its area constraints are Ia1 and Oa1 (restrictions from the cell a1) and Ib, respectively.
1, Ob1 (restriction from cell b1). At this time, the optimal existence area of the cell a2 is determined as a rectangular area R where the areas Ra1 and Rb1 intersect.

In the figure, the cell a2 satisfies the constraint Ra1, but does not satisfy the constraint Rb1. Therefore,
The cell a2 is moved to the center of gravity of the optimal existence region R that simultaneously satisfies the two constraints of the paths Pa and Pb. Here, a2 must of course also satisfy the region constraints of nets a23 and b23.

Finally, how to determine the wiring priority performed in step p9 will be described.

In the present invention, at the stage of the placement processing, the optimal existence area to be accommodated by each net is set on the chip,
The arrangement position of each cell is determined so as to comply with this as a constraint. The priority of the processing is set to the wiring of each net so as to keep this constraint condition in the wiring processing stage. The priority of the wiring is determined such that the stricter the region constraint set in the arrangement stage, the higher the priority, and the higher the priority of the wiring. In other words, the wiring is performed first with the net having the smaller size of the optimum existing area as the constraint.

By arranging in this way, a net having a smaller area size has a shorter wiring length, and a larger net has a greater detour, so that the wiring length is longer.

FIG. 7 is a table showing the restriction area size added to each net and the wiring priority determined from this. The priority 1 net is the net to be routed first, and as the priority number increases,
The order of the wiring processing is later. At the stage where all the nets shown in this table have been wired, the routing process is terminated.

[0079]

As described above, according to the present invention, the optimum existence area of each net constituting each critical path is determined in consideration of the mutual relationship, and the center of gravity of this area is determined. Cells are placed in Also, the wiring priority of each net is determined based on the determined size of the optimal existence area.

As a result, the entire critical path can be optimized, and the operating characteristics of the integrated circuit can be satisfied.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an automatic cell placement apparatus that realizes a design method of the present invention.

FIG. 2 is a general flowchart showing a processing procedure of a design method of the present invention.

FIG. 3 is a simplified diagram showing a display state of a screen of a CRT 104 shown in FIG.

FIG. 4 is a flowchart showing details of an operation characteristic optimization layout process in steps f7 and f16 shown in FIG. 2;

FIG. 5 is a conceptual diagram for explaining how to obtain a region constraint condition.

FIG. 6 is a conceptual diagram for explaining how to obtain an area constraint condition when a plurality of paths are restricted.

FIG. 7 is a table for explaining a method of determining a wiring priority;

FIG. 8 is a plan view showing a chip configuration of a gate-layout type gate array type LSI.

FIG. 9 is a conceptual diagram for explaining how to obtain a region constraint condition by a conventional design method.

[Explanation of symbols]

Reference Signs List 100 CPU 101 System bus 102 Video RAM 103 CRT controller 104 CRT 105 Magnetic storage device 106 RAM 107 Keyboard 108 Pointing device a1 to a5 Logic cell a12 to a45 Net I1 to I3, Ia1, Ia2, Ib1, Ib2 Input side constraint conditions O1 to O3, Oa1, Oa2, Ob1, Ob2 Output side constraints R, R1 to R3 Optimal existence area Ra1, Rb1 Constraint area

Claims (1)

(57) [Claims] When arranging a plurality of logic cells on a semiconductor chip and wiring between the logic cells, a signal path having a small delay time margin with respect to a required specification of a maximum delay time is extracted and extracted. The upper limit value of the delay time allowed for the signal path is distributed to each net constituting the signal path, and the upper limit value of the wiring length allowed for each net based on the upper limit value of the distributed delay time. Is determined, and based on the determined upper limit value of the wiring length, the optimum existence area of the logic cell constituting each net is determined based on each of the input side and the output side of the signal path. Determining the arrangement position of the logic cell in the region, based on the size of the optimal existence region, determines the priority of wiring processing of a net constituted by the logic cells arranged in the optimal existence region, Each logic based on the determined priority A method for designing a semiconductor integrated circuit, comprising performing wiring processing between cells.