JP2929871B2 - NAND ROM and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a NAND ROM.

[0002]

2. Description of the Related Art In recent years, the degree of integration of MOS semiconductor integrated circuits has been significantly improved.

With the improvement in the degree of integration, the memory capacity of one chip of a NAND type ROM using MOS transistors is shifting from 32 Mbits to 64 Mbits.

[0004] A NAND type ROM has a unit array composed of a plurality of memory transistors connected in series in the column direction. That is, a unit array is connected between a digit line and a ground line via a unit selection transistor. In a semiconductor chip, a plurality of unit arrays are arranged in one or two rows along one digit line. A plurality of such digit lines are arranged in parallel to form one cell array block. Usually, a plurality of cell array blocks are arranged on one chip.

[0005]

In the case of MOS devices, a selective oxidation method has been used for a long time in the case of MOS devices, but trench isolation technology has been used recently. That is, a groove having a predetermined width is formed in a semiconductor chip, a silicon oxide film is formed on the surface, and then filled with an insulator such as a BPSG film to form an element isolation structure. The dimensions, especially the width, of this element isolation structure are NA
This is one of the major factors that limit the integration degree of the ND ROM, and the lower limit of this width is given by the minimum processing size of the lithography technology. When the minimum processing dimension is, for example, 0.4 μm, the distance between adjacent unit array rows is 0.4 μm
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SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a NAND which can be more highly integrated using trench isolation.
To provide a type ROM.

[0007]

A NAND type RO according to the present invention is provided.
M has a plurality of cell array block regions partitioned by a first element isolation structure selectively formed on the surface of the semiconductor substrate. In each of these cell array block regions, a plurality of grooves having a predetermined width are provided at a predetermined pitch, and an insulating film is provided on a side wall of each of the grooves as a second element isolation structure. A region sandwiched between two adjacent ones of the trench is defined as a first active region, and a portion of the bottom surface of the trench that is not in contact with the element isolation sidewall insulating film and a lower portion thereof are defined as a second active region. Area. Intersecting the first active region and the second active region on the surface of the first active region and the surface of the second active region via a first gate insulating film and a second gate insulating film, respectively. There are provided a plurality of branch lines of the word lines arranged in the direction.
Source and drain regions are provided in the first active region and the second active region in self-alignment with the branch lines of the word line. That is, the first active region and the second active region
A first unit array and a second unit array each having a plurality of cell transistors connected in series are arranged in the active region. One end of each of the one first unit array and the one adjacent second unit array is connected to one digit line via a first unit selection circuit and a second unit selection circuit, respectively. And the other end is connected to a ground line.

[0008] Such a NAND ROM can be realized by the following manufacturing method.

First, a field oxide film is selectively formed on the surface of a semiconductor substrate to partition a cell array block region. A first gate insulating film is formed on the surface of the cell array block region, and a first polycrystalline silicon film and an etching stopper film are sequentially deposited. The etching stopper film,
Preferably, it is a silicon oxide film, which has a lower etching rate than the means for etching the first polycrystalline silicon film. In the cell array block region, a three-layer film including the etching stopper film, the first polycrystalline silicon film, and the first gate insulating film is patterned to form a mask for dividing a plurality of groove formation regions.
Next, a groove is formed by etching the semiconductor substrate in the groove forming region. Thus, a first active region is defined by the feed oxide film and the groove. Next, after an insulating film such as a silicon oxide film is deposited on the entire surface, anisotropic etching is performed to leave a second active region only on the side wall of the groove as an insulating film for element isolation. The second
A second gate insulating film on the surface of the active region. Next, a second polycrystalline silicon film is deposited on the entire surface, and the second polycrystalline silicon film and the etching stopper film are formed using a resist film covering the second polycrystalline silicon film only in the trench as a mask. Remove. A refractory metal silicide film such as a tungsten silicide film is deposited and patterned to form branch lines of word lines. Most of the branch lines of the word line have a polycide structure. Next, ion implantation for forming a low concentration source / drain region is performed, an insulating spacer is formed on the side wall of the branch line of the word line, and ion implantation for forming a high concentration source / drain is performed. Next, coding is performed by performing ion implantation on a selected one of the first active region and the second active region below the branch line of the word line.

Since the thickness of the side wall insulating film for element isolation existing between adjacent active regions can be made smaller than the minimum processing dimension in lithography, the integration degree of the NAND type ROM can be further improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.
The bit NAND type ROM is 7.6 mm × 12.
It has a rectangular semiconductor chip 100 of 5 millimeters. The semiconductor chip 100 has eight cell array block areas 101 of 0.65 mm × 9.7 mm at intervals of 0.2 mm.
X-block decoders 102 each having 1024 output lines are arranged in these intervals. In addition, the peripheral circuits 104 and 1 are closer to the two short sides, respectively.
05 is arranged. The peripheral circuit 104 includes eight X-main decoders having 16 output lines. The peripheral circuit 105 includes eight Y-selectors for selecting 512 digit lines. Further, the peripheral circuit 105 has a Y-line for selecting 512 digit lines.
It includes a selector and a Y-decoder for selecting eight cell array blocks.

Next, the cell array block includes a plurality of unit arrays.

Referring to FIG. 3, one digit line Y
, A first unit array UA1 and a second unit array UA2 are connected in parallel via selection transistors S11 and S12, S21 and S22, respectively. Such a unit array pair is connected to 512 pairs of one digit line as described later. The first unit array UA1 has 16 cell transistors M11,
, M116 are connected in series, and the second unit array UA2 is similarly connected to M21, M22,.
, M216 are connected in series. Although all of these cell transistors are shown as enhancement type for convenience, depletion type is actually mixed. Which cell transistor is a depletion type depends on data to be written to the ROM. The selection transistors S12 and S21 are of the depletion type. When the potential of one of the unit selection lines US1 and US2 is set to “H”, one of the first unit array UA1 and the second unit array UA2 is connected to the digit line. .., x16 are branch lines of a word line described later. As shown in FIG. 4, a plurality of such unit array pairs UAP are connected to one digit line Y. In FIG. 4, M1 and M2 represent 16 cell transistors, respectively, and S1 and S2
Reference numeral 2 denotes two selection transistors. Similarly, US represents two unit selection lines, and x represents a branch line of 16 word lines. GNDX is a ground line (hereinafter referred to as an X-direction ground line) running in a direction orthogonal to the digit line in the cell array block, and GND is a ground line (hereinafter referred to as a Y-direction ground line) interconnecting a plurality of X-direction ground lines. is there.

As shown in FIG. 5, in the cell array block area 101, digit lines Y1, Y2,.
512 are provided, and branch lines x1 and x of word lines are provided in the horizontal direction.
2,..., X16 are 512 sets, unit selection lines US1, U
S is running 512 pairs. Digit lines Y1, Y2, ...
Are connected to the peripheral circuits (105 in FIG. 2), and the branch lines x1, x2,... Of the word lines join the main lines X1, X2,. 2) 104-X-main decoder 104a. Unit selection lines US1 and US2 are connected to X-block decoder 102. Further, every 64 digit lines, Y-direction ground lines GND1, GND2,.
Is provided. In the figure, white circles indicate connection points between the digit lines and the unit array.

The configuration of the cell array block outlined above is not specific to the present invention.

Next, the specific structure of the cell array block will be described with reference to FIGS.

The surface portion of the P-type silicon substrate has a depth of 4 to 6
A P-well having a micrometer and an impurity concentration of 5 × 10 ¹⁶ cm ⁻³ is formed. When the peripheral circuit is composed of N-channel MOSFETs, almost the entire area is provided.
It is formed in almost the entire region except the channel MOSFET formation region (hereinafter, a case where the peripheral circuit is formed by an N-channel MOSFET will be described).

Next, as shown in FIG. 6, a field oxide film 2 having a thickness of 0.4 .mu.m is formed by a selective oxidation method to form a cell array block region 101 and elements (not shown) of an X-block decoder and peripheral circuits. Partition the formation area. Further, a first gate oxide film 3 having a thickness of 10 to 20 nm is formed on the surface of the P-well 1 in the cell array block region 101 and the element formation region, and a first 100 nm-thick phosphorus-doped first surface is formed on the entire surface. The polycrystalline silicon film 4 and the silicon oxide film 5 having a thickness of 200 nanometers are sequentially deposited as an etching stopper film.

Next, as shown in FIG. 7, a photoresist film 6 is applied, and a plurality of stripe-shaped openings 7a having a width of 0.8 μm are formed at intervals of 0.5 μm over the entire cell array block. The silicon oxide film 5 is etched using the photoresist film 6 as a mask. The photoresist film 6 is removed, and anisotropic etching using a carbon tetrachloride CCl ₄ -based gas is performed using the silicon oxide film with openings as a mask, as shown in FIG.
First polycrystalline silicon film 4 and first gate oxide film 3
Is removed, and a mask for defining a groove forming region having an opening 7b is formed.

Next, as shown in FIG. 9, anisotropic etching is applied to the P-well 1 by 0.2 μm in the vertical direction.
The first active region is defined by the trench 8 and the field oxide film 2 by removing the silicon and forming the trench 8.
At this stage, the thickness of the silicon oxide film 5a has been reduced to about 100 nanometers. The etching gas is hydrogen bromide HB
r, nitrogen trifluoride NF ₃ , a mixed gas of oxygen and helium at a volume ratio of 5: 1: 1, and a pressure of 50 mTorr.
r, power is constant at 500 W. When etching is performed under such conditions, a groove having a vertical side wall can be formed. Next, as shown in FIG. 10, a silicon oxide film 9 having a thickness of 200 nanometers is deposited on the entire surface by a reduced pressure CVD method utilizing thermal decomposition of Si (OC ₂ H ₅ ) ₄ .

Next, anisotropic etching using a mixed gas of CHF ₃ and O ₂ is performed to form an insulating film 9a for element isolation on the side wall of the groove as shown in FIG. At this time, the thickness of the silicon oxide film 5b is 50 nanometers, and the width of the insulating film 9a (the thickness of the portion in contact with the bottom surface) is 150 nanometers. The portion of the bottom surface of the groove that is not covered with the insulating film 9a becomes the second active region. A second gate oxide film 10 is formed on the surface of the second active region. The second gate oxide film 10 is preferably formed to have substantially the same thickness by the same method as the first gate oxide film 3 described above. Next, a 100-nm-thick second polycrystalline silicon film 11 doped with phosphorus is deposited on the entire surface. Next, only the upper part of the groove is covered with the photoresist film 12.

Next, using the photoresist film 12 as a mask, the second polycrystalline silicon film is removed by isotropic etching using a mixed gas of CF ₄ and O ₂ as shown in FIG. Subsequently, as shown in FIG. 13, by anisotropic etching using a mixed gas of CHF ₃ and O ₂ ,
The silicon oxide film 5b is removed.

Next, the photoresist film 12 is removed, and as shown in FIGS. 14 and 15, a tungsten silicide film 13 having a thickness of 100 nanometers is deposited on the entire surface and then patterned to form a word line which also functions as a gate electrode. Branch line 13
(X1),..., 13 (x16) and unit selection line U
S1 and US2 are formed. Branch lines 13 of these word lines
(X1) and the like cross over the first active region 14 and the second active region 15 in the cell array block region 101. At this stage, a MOS is formed on the element formation region such as the peripheral circuit.
The gate electrode of the FET is formed.

Next, as shown in FIGS. 16 and 17, branch lines 13 (x1) of the word line,.
A low concentration source / drain region is formed in self-alignment with SU2. That is, about 5 × 10 ¹³ cm ^{−2 of} phosphorus ions are implanted at 60 keV, and
(Indicated by oblique lines) are formed and heat treatment is performed for activation. This activation treatment is substituted for a heat treatment step of about 900 ° C. for the interlayer insulating film to be performed later.

Next, a silicon oxide film having a thickness of 100 nanometers is deposited on the entire surface and etched back, so that the word line branch line 13 is formed as shown in FIGS.
An insulating spacer 22 is formed on the side wall such as (x1). At this time, the shape of the insulating film for element isolation slightly changes to 9b.

Subsequently, as shown in FIG. 20, after a silicon oxide film 16 having a thickness of 10 nm is deposited on the entire surface,
In order to form a high concentration source / drain region, arsenic ions are implanted at 70 keV and about 5 × 10 ¹⁵ cm ⁻² to form an arsenic ion implanted layer 17 (shown by dense oblique lines).

Next, as shown in FIGS. 1 and 21, the first active region and the second active region below the branch line 13 (x1) of the word line, that is, the channel region of the cell transistor or the selection transistor. Phosphorus ions are implanted into the selected one at 180 keV at about 1 × 10 ¹⁴ cm ⁻² to form the code injection layer 18-1 (shown by oblique lines falling to the right). Thus, the selection transistors S12 and S21 are depletion-type, and data corresponding to a predetermined code is written to the cell transistors. In this step, the phosphorus implantation layer 18-2 is also provided on one side of the branch line 13 (x16) of the word line.
Is similarly formed. This is for forming the X-direction ground line. Similarly, the phosphorus injection layer 18-3 is formed on one side of the unit selection line US1. The phosphorus implantation layer 18-3 is formed to connect the first unit array arranged in the first active region and the second unit array arranged in the second active region to the same digit line.

Next, as shown in FIGS. 22 and 23, in order to form an interlayer insulating film 19, BPSG or the like is deposited and flattened. At this stage, the phosphorus ion implanted layer 21,
The arsenic implanted layer 17 and the code implanted layer 18-2 are activated and a small amount of impurities are diffused. Become.
Next, the contact holes C1 (displayed by drawing one oblique line in a rectangle) and C2 (displayed by drawing two oblique lines in a rectangle), and the ends of word line branch lines 13 (x1)... After forming through-holes C3 (represented by rectangles) on the portions, an Al—Si alloy film 20 is deposited and patterned to form word line trunks 20 (X1),
.., Digit lines 20 (Y512),..., Y-direction ground lines 20 (GND9),.

In the above description, the exposure step of the photoresist film 12 in FIG. 11, the patterning of the tungsten silicide film 13 and the like in FIGS. 16 and 17, and the patterning of the Al—Si alloy film 20 in FIGS. C in the photoresist film exposure process
EL technology can be used. For more information on CEL technology, see IE ELECTRON DEVICE LETTER (IEEE ELECTRON DEVI
CE LETTERS), Volume EDL-4, Issue 1, 1
1983, "Contrast Enhanced Photolithography" (Contrast
Enhanced Photolithography)
Has been introduced. That is, the surface of the positive type photoresist film is coated with a fading substance such as GE CEM-2 having a thickness of 100 to 300 nanometers and then exposed, and after the exposure, the CEL film is removed, and the photoresist film is developed. It does. The positive type photoresist film originally increases transparency by exposure, and at present, a fine pattern can be formed without necessarily using the CEL technique.

In this embodiment, the minimum processing dimension on photolithography is 0.4 micrometers. The dimension required for the insulation between the first active region and the second active region is the width (approximately 0.15 micrometers) of the sidewall isolation 9b for element isolation. When the trench isolation technique is used, a trench is arranged between adjacent unit arrays, and the dimension required for that is at least 0.4 micrometers. Therefore, the width of the cell array block area increases by about 0.25 millimeter. According to this embodiment, the length of the short side of the semiconductor chip can be reduced by about 2 millimeters.

In the embodiment described above, the thickness of the second polycrystalline silicon film 11 deposited after forming the side wall insulating film 9a shown in FIG. 11 was set to 100 nanometers. After the grooves are completely filled to a thickness of 6 micrometers, an etchback may be performed to leave only 100 nanometers thick on the second active region. Then, there is an advantage that the formation of the photoresist film 12 becomes unnecessary.

The mask ROM has been described above.
It will be apparent to those skilled in the art that the present invention can be applied to a flash EEPROM.

[0033]

As described above, according to the present invention, a groove is formed in a semiconductor substrate, and a first active region sandwiched between two grooves and a second active region at the bottom of the groove are formed on the side wall of the groove. By providing an insulating film and isolating each other and forming a memory transistor in each active region, it is possible to perform element isolation in a size smaller than the size limited by the minimum processing size in lithography. Has the effect of improving the degree of integration of layers.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor chip used for explaining a first embodiment of the present invention.

FIG. 2 is a schematic plan view of a semiconductor chip according to one embodiment of the present invention, showing an arrangement of a cell array block region and the like.

FIG. 3 is a circuit diagram showing a unit array pair in the embodiment.

FIG. 4 is a circuit diagram schematically showing a unit array pair group connected to one digit line in the embodiment.

FIG. 5 is a plan view schematically showing a cell array block in the embodiment.

6A and 6B are a plan view (FIG. 6A) for explaining the manufacturing method of the embodiment and an enlarged sectional view taken along line AA of FIG. 6A (FIG. 6B).

7 is a plan view (FIG. 7 (a)) for explaining a step following the step corresponding to FIG. 6, and an enlarged cross-sectional view (FIG. 7 (b)) along the line AA in FIG. 7 (a). is there.

8 is a cross-sectional view for describing a step subsequent to the step corresponding to FIG.

9 is a cross-sectional view for describing a step subsequent to the step corresponding to FIG.

10 is a cross-sectional view for describing a step subsequent to the step corresponding to FIG.

FIG. 11 is a plan view (FIG. 11A) for explaining a step subsequent to the step corresponding to FIG. 10 and AA in FIG. 11A;
It is an expanded sectional view in a line (FIG. 11B).

FIG. 12 is a cross-sectional view for illustrating a step subsequent to the step corresponding to FIG.

13 is a cross-sectional view for describing a step subsequent to the step corresponding to FIG.

FIG. 14 is a plan view for explaining a step subsequent to the step corresponding to FIG.

15 is an enlarged sectional view taken along line AA of FIG. 14 (FIG. 1);
5 (a)) and an enlarged sectional view taken along line BB (FIG. 15).
(B)).

FIG. 16 is a plan view for explaining a step following the step corresponding to FIGS. 14 and 15;

17 is an enlarged sectional view taken along line AA of FIG. 16 (FIG. 1);
7 (a)), an enlarged sectional view taken along line BB (FIG. 17).
(B)) and an enlarged sectional view taken along line CC (FIG. 17).
(C)).

FIG. 18 is a plan view for explaining a step subsequent to the step corresponding to FIGS. 16 and 17;

19 is an enlarged sectional view taken along line AA of FIG. 18 (FIG. 1);
9 (a)), an enlarged sectional view taken along line BB (FIG. 19).
(B)) and an enlarged sectional view along line CC (FIG. 19)
(C)).

20 is a cross-sectional view for explaining a step subsequent to the step described with reference to FIGS. 18 and 16; FIG.
FIG. 20 (b) corresponds to FIG. 19 (b), and FIG. 20 (c) corresponds to FIG. 19 (c).

21 is a cross-sectional view for explaining a step subsequent to the step corresponding to FIG. 20, wherein FIG. 21A is an enlarged cross-sectional view taken along line AA of FIG. 1, and FIG. 21B is a cross-sectional view of FIG. FIG. 21C is an enlarged sectional view taken along line CC of FIG. 1.

FIG. 22 is a plan view for explaining a step subsequent to the step corresponding to FIG. 21 and shows a cell array block.

23 is an enlarged sectional view taken along line AA of FIG. 22 (FIG. 2);
3 (a)) and an enlarged sectional view taken along line BB (FIG. 23).
(B)).

[Explanation of symbols]

 Reference Signs List 1 P well 2 Field oxide film 3 First gate oxide film 4 First polycrystalline silicon film 5, 5a Silicon oxide film 6 Photoresist film 7a, 7b Opening 8 Groove 9 Silicon oxide film 9a, 9b Insulating film 10 Second Gate oxide film 11 second polycrystalline silicon film 12 photoresist film 13 tungsten silicide film 13 (x1),..., 13 (x16) word line branch line 14 first active region 15 second active region 16 silicon oxide Film 17 Arsenic ion implanted layer 17a High concentration source / drain region 18-1 Code implanted layer 18-2 Phosphorus implanted layer 18-2a Code diffused layer 18-3 Code diffused layer 19 Interlayer insulating film 20 Al-Si alloy film 20 (X1 ), Word line trunk line 20 (Y512) Digit line 20 (GND9) Y-direction ground line 21 Phosphorus ion injection Layer 21a lightly doped source and drain regions 22 insulating spacer

Claims (6)

(57) [Claims] 1. A plurality of cell array block regions defined by a first element isolation structure selectively formed on a surface of a semiconductor substrate are arranged at a predetermined pitch in each of a plurality of cell array block regions, and a second element isolation is provided on a side wall. A plurality of grooves having a predetermined width each having an insulating film as a structure, and a surface of a first active region formed by the semiconductor substrate region sandwiched between two adjacent grooves and a bottom surface of the grooves. The first active region and the second active region are formed on a surface of a second active region formed by a portion not in contact with the insulating film and a lower portion of the second active region via a first gate insulating film and a second gate insulating film, respectively. A plurality of word lines arranged in a direction crossing the second active region, and source / drain regions respectively provided in the first active region and the second active region in self-alignment with the word lines. Has several First and second unit arrays each having cell transistors connected in series to each other, and a first unit array at one end of one of the first unit arrays and one of the second unit arrays adjacent thereto. Digit lines connected through a unit selection circuit and a second unit selection circuit, respectively, and connected to the other ends of one of the first unit arrays and one of the second unit arrays adjacent thereto, respectively. And a ground line. 2. The word line comprises a polycrystalline silicon film selectively covering the first gate insulating film and the second gate insulating film, respectively, and a refractory metal silicide film covering the polycrystalline silicon film. NA according to claim 1
ND ROM. 3. The second unit selection circuit, wherein the first unit selection circuit includes an enhancement-type first selection transistor and a depletion-type second selection transistor having the same shape as the cell transistor. 2. The NAND type RO according to claim 1, further comprising a depletion-type third selection transistor and an enhancement-type fourth selection transistor having the same shape as the cell transistor.
M. 4. The semiconductor device according to claim 1, wherein the ground line is selectively formed on the semiconductor substrate at a bottom of the first active region and the trench .
2. The NAND type ROM according to claim 1, further comprising an impurity diffusion layer of a conductivity type opposite to that of said semiconductor substrate . 5. A step of selectively forming a field oxide film on a surface of a semiconductor substrate to partition a cell array block region; forming a first gate insulating film on a surface of the cell array block region; Etching means for etching the crystalline silicon film and the first polycrystalline silicon film;
An etching stopper film having a lower rate is sequentially deposited, and a three-layer film including the etching stopper film, the first polysilicon film, and the first gate insulating film is selectively removed in the cell array block region. Forming a mask for partitioning a plurality of groove forming regions arranged at a predetermined pitch, and etching the semiconductor substrate in the groove forming region to form a groove, and forming a first groove on the field insulating film and the groove. A step of partitioning the active region; a step of depositing an insulating film on the entire surface and performing anisotropic etching to form an insulating film for element isolation on the side wall of the groove; Forming a second gate insulating film having substantially the same thickness as the first gate insulating film in a second active region whose surface is a portion not covered with a film; With membrane Depositing a second polycrystalline silicon film quality on the same thickness over the entire surface, the resist film covering the second polycrystalline silicon film only in the groove as a mask the second polysilicon film and A step of sequentially removing the etching stopper film, a step of depositing a high melting point metal silicide film on the entire surface, and applying a lithography technique to the high melting point silicide film, the first polycrystalline silicon film and the second polycrystalline silicon film. Forming a plurality of word lines in a direction intersecting with the first active region and the second active region, respectively, by patterning using the word line and the insulating film for element isolation; Performing ion implantation for forming a concentration source / drain region, and insulating the element isolation insulating film on the side wall of the word line while leaving the insulating film on the side wall of the trench. Forming a spacer; performing ion implantation for forming a high-concentration source / drain region using the word line, the insulating film for element isolation and the insulating spacer as a mask; Performing coding by performing ion implantation on predetermined ones of the active region and the second active region. 6. Injecting phosphorus ions for forming the low-concentration source / drain regions, implanting arsenic ions for forming the high-concentration source / drain regions, and performing the coding again with higher energy than the implantation of the phosphorus ions. 6. The NAND ROM according to claim 5, wherein phosphorus ions are implanted.
Manufacturing method.