JP2927002B2 - DRAM backup device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM backup device and, more particularly, to a CPU having a refresh function.
And a DRAM backup device controlled by the DRAM.

[0002]

2. Description of the Related Art Dynamic RAM (hereinafter referred to as DRA)
M), as is well known, it is necessary to perform refresh processing for holding stored information at regular intervals.

[0003] Such refresh processing has been performed by a refresh controller until now, but recently, it is often performed by a CPU having a refresh processing function. In addition, in a system using a CPU having a refresh processing function, DRA can be performed even during a power failure.
A backup device is connected to the CPU and the DRAM so that the stored information of M is not lost, so that the refresh processing is continued even in the event of a power failure.

FIG. 4 is a block diagram of a conventional DRAM backup device, and FIG. 5 is a timing chart for explaining its operation. Note that FIG. 4 shows only the components necessary for the description of the present invention for easy understanding.

The power supply circuit 10 includes a voltage conversion unit 11, a voltage drop detection unit 12, and a capacitor 13. The voltage conversion unit 11 steps down and rectifies AC 100V and outputs a DC 5V logic voltage. The value of the logic voltage is detected by the voltage drop detector 12. The logic unit 20 has C
A voltage drop detector 1 comprising a PU 21, a DRAM 22, a backup power supply 23, and a switching unit 24;
2, the detection signal S1 is input to the interrupt terminal 21a of the CPU 21.

The CPU 21 refreshes the DRAM 22 at regular intervals, and executes a predetermined interrupt process when an "H" level signal is input to the interrupt terminal 21a.

In such a configuration, while the external AC voltage is being supplied to the power supply circuit 10, a normal logic voltage is output from the voltage converter 11, so that the voltage drop detector 12 detects this. To output an "L" level signal. Therefore, the transistor Tr1 of the switching unit 24 is turned on, and the logic voltage output from the voltage conversion unit 11 is supplied to the CPU 21 and the DRAM 22 via the switching unit 24.
Supplied to

[0008] However, as shown in FIG.
When the AC power is cut off at the time, the logic voltage output from the voltage conversion unit 11 gradually decreases in accordance with the capacity 13, and when reaching the predetermined reference value Vth at time t1, the voltage drop detection unit 12 detects this. Detects and outputs an “H” level signal.

Since the allowable range of the operation guarantee voltage of each element is as narrow as 5 V ± 10% for the DRAM and 5 V ± 5% for the CPU, the reference value Vth is set to 4. It is set to about 8V.

In the logic section 20, the transistor Tr1 of the switching section 24 is cut off by this "H" level signal, so that the CPU 21 and the DRAM 22 are supplied with a logic voltage from the backup power supply 23.

On the other hand, the CPU 21 starts an interrupt process, executes an end process registered in advance as a process to be executed when the power is turned off, and then shifts to a low power consumption standby mode.

[0012]

As described above, in a system using a CPU having a refresh processing function, it is necessary to back up the CPU together with the DRAM so that the refresh processing can be continued even during a power failure. .

The operation of the CPU 21 is guaranteed and the DR
In order to reliably store the stored information of the AM, the voltage drop detection unit 12 needs to accurately determine whether the logic voltage output from the voltage conversion unit 11 is equal to or higher than a reference value.

However, in the voltage drop detection unit 12, there is a problem that the above determination may be erroneous due to aging deterioration of the circuit element, temperature drift, or the like, and the information stored in the DRAM may be lost.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a DRAM backup device capable of reliably backing up a DRAM.

[0016]

To achieve the above object, the present invention provides a CPU having a refresh function.
A backup device for a DRAM controlled by a control unit includes a cut-off detecting unit for detecting the presence or absence of an external AC voltage, a unit for interrupting a CPU when the cut-off is detected, and a CPU status monitor for detecting that the CPU is in a standby state. When the CPU terminates the interrupt processing and shifts to the standby state, the logic voltage source is switched to the backup power supply.

[0017]

[0018]

SUMMARY OF] With the above arrangement, CPU status monitor, since the CPU ends and when processing power shutdown will act to switch the logic voltage source to a backup power source when it becomes a standby state, the backup power supply Power consumption can be saved.

[0019]

FIG. 1 is a block diagram of a DRAM backup apparatus which is a basic configuration of the present invention, and the same reference numerals as those in FIG. 4 denote the same or equivalent parts.

In FIG. 1, a power supply circuit 10 includes a voltage conversion unit 11, a power supply cutoff detection unit 31, and a capacitor 13. The voltage conversion unit 11 steps down and rectifies an external AC voltage and outputs a logic voltage. The power-off detection unit 31 detects the presence or absence of an external AC voltage.

FIG. 2 is a circuit diagram showing the configuration of the power-off detection section 31, which is configured using a photocoupler.

In FIG. 1, an external AC voltage is rectified by a diode D1, and its DC component is supplied to a light emitting diode D2. On the light receiving side, the collector of the transistor Tr2 is pulled up via the resistor R1.

In such a configuration, while the external AC voltage is being generated, the transistor Tr2 is turned on by the light emitting diode D2, so that an "L" level signal is output to the interrupt terminal of the CPU 21.

On the other hand, when the external AC voltage is cut off, the transistor Tr2 is turned off, so that an "H" level signal is output to the interrupt terminal of the CPU 21.

At this time, the switching unit 24 uses the transistor T
r2 is cut off, so the backup power supply 23
21. Power supply to the DRAM 22 is started. Also, CP
In U21, an interrupt process is started, and after executing a scheduled end process, a transition is made to a standby mode in a low power consumption state.

According to such a configuration , the power-off detecting section 3
Since 1 detects the presence or absence of an external AC voltage, it is possible to immediately detect the power cut of the external AC voltage regardless of the aging of the circuit element or the temperature drift.

Therefore, when the power is turned off, the CPU and the DRAM are quickly and reliably connected to the backup power supply.

FIG. 3 is a block diagram of the first embodiment of the present invention, wherein the same reference numerals as those described above denote the same or equivalent parts.

In this embodiment, the CP which detects that the operation state of the CPU 21 is the standby mode and outputs a detection signal is provided.
A U status monitor 41 is provided to switch to the backup power supply 23 when the CPU 21 enters the standby mode.

According to the present embodiment, the end processing in which the power consumption of the CPU 21 is relatively large is performed by the logic voltage supplied from the capacitor 13 of the power supply circuit 10, and the backup is performed when the CPU 21 enters the standby mode in which the power consumption is low. Since the power source is switched to the power source 23, the power consumption of the backup power source 23 can be saved.

[0031]

As described above, according to the present invention, the power cutoff is determined based on the presence or absence of an external AC voltage, so that the power cutoff of the external AC voltage can be immediately detected, and At times, the CPU and the DRAM are quickly and reliably connected to the backup power supply.

A CPU status monitor is provided.
If the PU is switched to the backup power supply when the PU enters the standby mode with low power consumption, the power consumption of the backup power supply can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a basic configuration of the present invention.

FIG. 2 is a block diagram of a main part of FIG.

FIG. 3 is a block diagram of a first embodiment of the present invention.

FIG. 4 is a block diagram of a conventional technique.

FIG. 5 is a timing chart for explaining the operation of the conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Power supply circuit, 11 ... Voltage conversion part, 12 ... Voltage drop detection part, 13 ... Capacitance, 20 ... Logic part, 21 ... CPU,
Reference numeral 22: DRAM, 23: backup power supply, 24: switching unit, 31: power-off detection unit, 41: CPU status monitor

Claims (1)

(57) [Claims] 1. A backup device for a DRAM controlled by a CPU having a refresh function, comprising : a voltage conversion means for converting an external AC voltage into a logic voltage and outputting the logic voltage; , A means for interrupting the CPU with the cut-off detection signal and executing a scheduled power-off process, a backup power supply for outputting a logic voltage, and detecting that the CPU is in a standby state. A CPU status monitor that outputs a standby state detection signal in response to the standby state detection signal; and a switching unit that switches a logic voltage source from an output voltage of a voltage conversion unit to an output voltage of a backup power supply based on the standby state detection signal. And a backup device for a DRAM, which shifts to a standby state after a power-off process is completed .