JP2926048B2 - Apparatus and method for estimating performance of integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit performance estimating apparatus and method for estimating the performance of an integrated circuit such as an area and an operating speed in a register transfer level designing stage.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor manufacturing processes and the scale of integrated circuits, the design of integrated circuits has become more and more complicated, and correction after detailed design has become extremely difficult. For this reason, there is a problem that the design period is lengthened due to the rework of the design.

In order to prevent the design period from being prolonged due to design rework, there is a design method for estimating the performance of the integrated circuit at an early stage of the design and solving the problems before the detailed design based on the result of the performance estimation. It has been gaining importance.

Conventional methods for estimating the performance of integrated circuits include:
In some cases, logic synthesis with reduced optimization capability is executed using a logic synthesis tool.

Japanese Patent Laid-Open Publication No. Hei 7-160748 discloses a hardware description language (Hardware Description Language).
uage, hereinafter abbreviated as “HDL”). This identifies the HDL description unit,
This is a method for calculating a delay time and a circuit scale for each description unit.

[0006]

However, there have been the following problems in the prior art.

First, the performance estimation method using the logic synthesis tool has a problem that its processing requires a long time of tens of minutes to several hours.

In the method disclosed in Japanese Patent Application Laid-Open No. 7-160748, when obtaining the circuit area and delay time of an operator included in an input HDL description, a circuit configuration for realizing the operator is considered. Therefore, it is possible to search for a design space represented by a trade-off between the circuit area and the delay time, in which the delay time is increased in a configuration with a small circuit area and the circuit area is increased in a configuration with a small delay time. Therefore, there is a problem that accurate performance estimation cannot be performed on the result of logic synthesis.

Further, since this method only obtains the delay time of the logic portion of the integrated circuit, the performance of the integrated circuit is not improved in the design of deep submicron where the wiring delay greatly affects the operation speed of the integrated circuit. There is a problem that the estimation error becomes large.

In view of the above-mentioned problems, the present invention provides an integrated circuit capable of accurately estimating performance such as area and timing of an integrated circuit in a short time at an early stage of design, that is, at a register transfer level design stage. It is an object to provide a performance estimation device and a performance estimation method.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention determines an estimation model for estimating the performance of each component expressing an integrated circuit at a register transfer level, and determines a wiring delay time. Using a driver model obtained by modeling a driver, the area and timing of an integrated circuit at a register transfer level are estimated in consideration of the trade-off.

More specifically, a solution taken by the invention of claim 1 is a device for estimating the performance of an integrated circuit at a register transfer level design stage, wherein the performance of each component expressing the register transfer level integrated circuit is improved. Library that stores an estimation model for estimating, a driver library that models and stores the relationship between the driving capability and area of the driver that drives the wiring, and register transfer level integration expressed by the connection relation of parts Estimating the performance that satisfies predetermined constraints while applying the estimation model stored in the estimation library to each component and changing the application of the driver model stored in the driver library as necessary for each component. And a trade-off estimating means.

According to the first aspect of the present invention, the trade-off estimating means applies the estimation model stored in the estimation library to each component of the integrated circuit at the register transfer level represented by the connection relation of the components. Since the performance satisfying the predetermined constraint is estimated while changing the application of the driver model stored in the driver library as necessary, the area and timing of the integrated circuit after logic synthesis are considered in consideration of the trade-off. In addition, the estimation can be performed with high accuracy. In addition, since it is not necessary to perform logic synthesis, estimation can be performed in a shorter time than in the past.

According to a second aspect of the present invention, the trade-off estimating means in the integrated circuit performance estimating apparatus of the first aspect estimates a minimum area of the integrated circuit satisfying a given timing constraint. I do.

According to a third aspect of the present invention, in the integrated circuit performance estimating device according to the first aspect, an estimation model is stored in the estimation library, the expression being a parse tree representing the integrated circuit at the register transfer level. It is assumed that a parse tree allocating unit is provided which converts the obtained component to each node of the parse tree to convert it into an expression based on the connection relation of the component, and inputs the expression to the trade-off estimating unit.

According to the third aspect of the present invention, the expression based on the parse tree representing the integrated circuit at the register transfer level is converted into the expression based on the connection relation of the parts by the parse tree allocating means and input to the trade-off estimating means. Therefore, even for an integrated circuit at the register transfer level represented by a parse tree, the area and timing after logic synthesis can be accurately estimated.

Further, in the invention of claim 4, according to the above-mentioned claim 3,
The apparatus for estimating the performance of an integrated circuit described above converts a description in a hardware description language, which represents an integrated circuit at a register transfer level, into a representation by a parse tree by parsing the syntax, and inputs the syntax to the parse tree allocating means. It is assumed that analysis means is provided.

According to the fourth aspect of the present invention, the description in the hardware description language, which represents the integrated circuit at the register transfer level, is converted by the parsing means into a parse tree expression and input to the parse tree allocating means. Furthermore, since the expression is converted into an expression based on the connection relation of parts and input to the trade-off estimating means, the area and timing after logic synthesis can be accurately estimated even for an integrated circuit designed in a hardware description language. can do.

According to a fifth aspect of the present invention, the trade-off estimating means in the integrated circuit performance estimating apparatus according to the first aspect of the present invention includes a minimum area of the integrated circuit and a path of each inter-register path when the area is minimized. An area priority estimating unit for estimating a delay time, a timing analyzing unit for determining whether or not the delay time of each inter-register path of the integrated circuit satisfies a timing constraint given to the integrated circuit; Performance candidate list creation for creating a performance candidate list in which performance candidates are enumerated while changing the application of the driver model for each component on the inter-register path whose delay time does not satisfy the timing constraint of the integrated circuit. Part and the delay time of the register-to-register path that does not satisfy the timing constraint When the performance candidates are selected from the performance candidate list created by the performance candidate list creation unit, and the selected performance candidate is set as the performance of each component, so that the area increase of the integrated circuit is minimized, A performance candidate selection unit for estimating the area of the integrated circuit and the delay time of each register path is provided.

According to a sixth aspect of the present invention, the integrated circuit performance estimating apparatus according to the first aspect includes an integrated circuit having a hierarchical structure.
The integrated circuit is provided with floor plan means for determining the arrangement of modules in each layer and the route of wiring connecting between the modules, and the trade-off estimating means comprises: It is assumed that the performance of the integrated circuit that satisfies a predetermined constraint is considered, taking into account the wiring delay time between modules estimated from the wiring path determined by the floor plan means.

According to the sixth aspect of the present invention, the layout of the modules in each layer and the route of the wiring connecting the modules are determined for the integrated circuit having the hierarchical structure by the floor plan means, and the trade-off estimating means The performance of the integrated circuit, which satisfies a predetermined constraint, is estimated in consideration of the wiring delay time between modules estimated from the wiring path determined by the floor plan means. After considering the area and timing, considering the trade-off,
It can be estimated with high accuracy. In addition, since it is not necessary to perform logic synthesis, estimation can be performed in a shorter time than in the past.

Further, in the invention according to claim 7, in the integrated circuit performance estimating device according to claim 6, the hierarchical trade-off estimating means comprises a minimum area of the integrated circuit and a value between each register when the area is minimized. An area priority estimating unit for estimating the delay time of a path for each layer, a timing constraint given to the integrated circuit, and the arrangement of modules in each layer determined by the floor plan means and connection between modules A timing constraint setting unit for each layer that sets a timing constraint for each layer based on a route of a wiring to be performed, and a delay time of a path between registers in each layer of the integrated circuit is set by the timing constraint setting unit for each layer. Analysis unit that determines whether or not the delay constraint satisfies the timing constraint, and a register whose delay time does not satisfy the timing constraint. A performance candidate list creation unit that creates a performance candidate list listing performance candidates for each component on the inter-path while changing the application of the driver model; and an inter-register path where the delay time does not satisfy the timing constraint. For each of the above components, the performance created by the performance candidate list creating unit is such that the delay time of the inter-register path satisfies the timing constraint and the area increase of the integrated circuit in the hierarchy is minimized. A performance candidate selecting unit for selecting a performance candidate from the candidate list and estimating an area of the integrated circuit in the hierarchy and a delay time of each register path when the selected performance candidate is set as the performance of each component; Shall be provided.

According to another aspect of the present invention, as a method of estimating the performance of an integrated circuit at a register transfer level design stage, the performance of each component expressing the integrated circuit at the register transfer level is determined. Using an estimation model for estimation and a driver model that models the relationship between the driving capability and area of the driver that drives the wiring,
In addition, with respect to the integrated circuit of the register transfer level represented by the connection relation of the parts, a predetermined constraint is satisfied while applying the estimation model and changing the application of the driver model as necessary to each part. A trade-off estimation for estimating performance is performed.

According to the eighth aspect of the present invention, for an integrated circuit at the register transfer level represented by the connection relation of components, an estimation model for estimating performance is applied to each component, and application of a driver model is appropriately performed. Since the performance satisfying the predetermined constraint is estimated while changing, the area and the timing of the integrated circuit after the logic synthesis can be accurately estimated. In addition, since it is not necessary to perform logic synthesis, estimation can be performed in a shorter time than in the past.

According to a ninth aspect of the present invention, in the trade-off estimation in the integrated circuit performance estimation method according to the eighth aspect, a minimum area of the integrated circuit satisfying a given timing constraint is estimated. .

According to a tenth aspect of the present invention, in the method for estimating the performance of an integrated circuit according to the eighth aspect,
It is assumed that the representation by the parse tree representing the integrated circuit at the register transfer level is converted into the representation by the connection relation of the parts by allocating the parts for which the estimation model is prepared to each node of the parse tree.

According to the eleventh aspect of the present invention, in the method for estimating the performance of an integrated circuit according to the tenth aspect,
It is assumed that a description in a hardware description language representing an integrated circuit at a register transfer level is converted into an expression by a parse tree by parsing.

According to a twelfth aspect of the present invention, the trade-off estimation in the integrated circuit performance estimating method according to the eighth aspect is performed by obtaining an area of each component of the integrated circuit by using the estimation model, and Based on the area of the part,
Determining the area, for the integrated circuit, determine the internal delay time and wiring delay time of each component using the estimation model and the driver model, based on the determined internal delay time and wiring delay time of each component, Determining a delay time of an inter-register path; and, for the integrated circuit, determining whether delay times of all inter-register paths satisfy a given timing constraint. Area is estimated as the minimum area,
If not, for each component on the inter-register path whose delay time does not satisfy the timing constraint, while changing the application of the driver model, the inter-register path satisfies the timing constraint and the area of the integrated circuit. A step of obtaining a performance candidate that minimizes the increase, and obtaining the area of the integrated circuit and the delay time of each inter-register path when the obtained performance candidate is set as the performance of each component.

According to a thirteenth aspect of the present invention, in the performance estimation method for an integrated circuit according to the eighth aspect, an integrated circuit having a hierarchical structure is to be subjected to performance estimation. A floor planning step of determining a layout of the modules and a wiring path connecting the modules, wherein the trade-off estimation is performed on the integrated circuit based on a wiring path estimated from the wiring path determined by the floor planning step. It is assumed that the performance that satisfies the predetermined constraint is estimated in consideration of the delay time.

According to the thirteenth aspect of the present invention, for an integrated circuit having a hierarchical structure, the arrangement of modules in each layer and the route of wiring connecting modules are determined.
With respect to the integrated circuit, a performance satisfying a predetermined constraint is estimated for each hierarchy while considering a wiring delay time between modules estimated from the determined wiring path. And the timing can be accurately estimated. In addition, since it is not necessary to perform logic synthesis, estimation can be performed in a shorter time than in the past.

According to a fourteenth aspect of the present invention, in the trade-off estimating step in the integrated circuit performance estimating method according to the thirteenth aspect, the area of each component of the integrated circuit is determined by using the estimation model. Determining the area for each layer based on the area of each component; and determining the internal delay time and the wiring delay time of each component using the estimation model and the driver model for the integrated circuit; The wiring delay time between modules is obtained from the arrangement of modules in each hierarchy determined in the above and the wiring path connecting the modules, and the delay time of the inter-register path is obtained for each hierarchy based on the obtained delay times. Process, for the integrated circuit, a timing constraint given to the integrated circuit, and the floor plan process Setting a timing constraint for each layer based on the arrangement of modules in each layer determined in the above and a wiring path connecting the modules, and for the integrated circuit, all inter-register paths are defined for each layer. It is determined whether or not the timing constraint set for the hierarchy is satisfied, and if so, the currently calculated area is estimated as the minimum area in the hierarchy, and if not, the delay time is determined. For each component on the register-to-register path that does not satisfy the timing constraint,
While changing the application of the driver model, a performance candidate in which the inter-register path satisfies the timing constraint and the area increase in the hierarchy of the integrated circuit is minimized is determined, and the determined performance candidate is determined for each component. Determining the area of the integrated circuit in the hierarchy and the delay time of each inter-register path when the performance is set.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram of an integrated circuit performance estimating apparatus according to the first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an estimation library for storing an estimation model for estimating performance of components such as registers, adders, and multipliers which are components of an integrated circuit at a register transfer level (hereinafter abbreviated as RTL). Reference numeral 2 denotes a driver library that models and stores the relationship between the driving capability and area of the driver for driving the wiring, and 3 denotes an RTL to be subjected to performance estimation.
HDL description describing the integrated circuit of the above, 4 is timing constraint information specifying a clock cycle of the integrated circuit whose performance is to be estimated as a timing constraint, and 5 is a syntax analyzer for inputting the HDL description 3 and converting it into an expression by a parse tree. , 6 are parse tree allocating means for allocating components of the estimation library 1 to each node of the parse tree created by the parse means 5, and 7 is to use the driver library 2 to determine the area and timing of the integrated circuit whose performance is to be estimated. This is a trade-off estimating means for estimating. The trade-off estimating means 7 includes an area priority estimating section 8 for estimating the minimum area of the integrated circuit whose performance is to be estimated and the timing at the time of the minimum area; a timing analyzing section 9 for analyzing the estimated timing; 6 and a performance candidate list creating unit 10 for enumerating the performance candidates of the components assigned in 6 and the performance constraint information 4 from the performance candidates of each component created by the performance candidate list creating unit 10 and satisfying the condition that the area is minimum. It comprises a performance candidate selection unit 11 for selecting a combination of performance candidates. Reference numeral 12 denotes an estimated value output unit that outputs an estimation result 13.

Here, the estimation library 1 and the driver library 2 will be described.

FIGS. 2 and 3 are diagrams showing information held by the estimation library 1. FIG. The estimation library 1 classifies information on components expressing an RTL integrated circuit into two types and stores them. FIG. 2 is a diagram showing information of a type 1 component, and FIG. 3 is a diagram showing information of a type 2 component. Type 1 expresses that the number of input signals is variable.
Type 2 is a logic operation component such as ND or OR, and type 2 is another component expressing that the number of input signals is fixed.

As shown in FIGS. 2 and 3, in the estimation library 1, for each type of component, an area estimation model representing the area, a delay estimation model representing the gate delay time from input to output, and In addition, a stage number estimation model indicating the number of logical stages from input to output for obtaining the wiring delay time is set.

In FIG. 2, the row of 21 indicates each model of the AND gate as an example of the type 1 component. As shown in FIG. 2, in the type 1 component, each of the area estimation model, the delay estimation model, and the stage number estimation model is represented by a function of the number of input signals.

Also, in FIG.
Each model of a multiplexer as an example of parts of
Rows 23 and 24 are each model of the adder. For components that have several possible circuit configurations, such as adders, the area estimation model for each circuit configuration,
A delay estimation model and a stage number estimation model are set. 23
Denotes models when the adder is realized by a ripple carry having a small area, and 24 denotes models when the adder is realized by a carry look-ahead having a small delay time. As shown in FIG. 3, in the type 2 component, each of the area estimation model, the delay estimation model, and the stage number estimation model is represented by a function of the bit width of the input signal. In the case of 22 multiplexers, the delay in the delay estimation model is constant without depending on the bit width, and the number of stages in the stage number estimation model is always zero.

Each model of each component in the estimation library 1 as shown in FIGS. 2 and 3 is set from a cell library used for design.

FIG. 4 is a diagram showing information held by the driver library 2. The driver library 2 models drivers having different driving abilities, and FIG.
Is the standard driver. In FIG. 4, a row of 30 indicates the driving capability of each driver by a resistance value. In other words, the smaller the value shown in the row of 30, the greater the driving capability. In FIG. 4, the driving capability increases in the order of the driver A to the driver E, and the driver A is the driver with the minimum driving capability and the driver E is the driver with the maximum driving capability. Row 31 is the difference in area as compared with driver A, row 32 is the difference in delay time as compared with driver A, row 33 is the difference in the number of stages as compared with driver A, row 34. Is the capacitance of the input pin. The capacitance of the input pin uses the value of the driver A as a standard value. The driver model in the driver library 2 as shown in FIG. 4 is set from a cell library used for design.

Hereinafter, the operation of the integrated circuit performance estimating apparatus configured as described above will be described with reference to the drawings.

FIG. 5 is a flowchart showing a performance estimation method in the integrated circuit performance estimation device according to the first embodiment.
The operation of the apparatus for estimating the performance of an integrated circuit according to the present embodiment will be described with reference to FIG.

(Syntax Analysis Step ST1) As shown in FIG. 5, first, in the syntax analysis step ST1, the syntax analysis means 5
Converts the input HDL description 3 into an expression based on a parse tree, and inputs the expression to the parse tree allocating means 6. Syntax analysis step ST
1 is performed by a series of steps as follows. (ST1-1) The HDL description 3 is divided into process units, and the following steps ST1-2 to S1-2 are performed for each process.
Perform T1-5. (ST1-2) The process is parsed and a parse tree is created. (ST1-3) Successive AND (&) on the parse tree
Or merge OR (|). (ST1-4) NOT (!) And child A on the parse tree
ND (&) or OR (|) are merged to be NAND or NOR. (ST1-5) A bit width attribute is added to a node of the syntax analysis tree, and a fanout number attribute is added to a branch. FIG. 6 is a diagram showing the execution result of the syntax analysis step ST1 for the following HDL description expression. X =! a & b & c | d & e & f In the figure, (a) is a diagram showing a parse tree created as a result of executing step ST1-2 on the above expression,
(B) shows a step ST for the parse tree shown in (a).
It is a figure showing the parsing tree obtained as a result of performing 1-3. AND (&) 15, 16 in (a) is (b)
And (&) 17 are merged.

(Syntax Tree Assignment Step ST2) Next, in the parse tree assignment step ST2, the parse tree assignment means 6 assigns components stored in the estimation library 1 to each node of the parse tree.

FIG. 7 is a diagram showing the execution result of the parse tree allocating step ST2 for the parse tree of FIG. 6B. In FIG. 7, 2OR, 3AND, and INV each have two inputs O
R, a three-input AND, and an inverter. Reference numeral 18 denotes a three-input A assigned to an AND (&) 17 in FIG.
ND.

(Area Calculation Step ST3) Next, in the area calculation step ST3, the area priority estimation unit 8 in the trade-off estimation means 7 calculates the minimum area of the integrated circuit whose performance is to be estimated. Specifically, the area of the component allocated by the analysis tree allocating means 6 is determined based on the area estimation model, and the area of each of the determined components is summed up. Ask. For the type 1 component, the area per 1 bit is obtained according to the number of input signals based on the area estimation model, and the area per 1 bit is calculated in step ST1 of the syntax analysis step ST1.
The area is obtained by multiplying the bit width attribute set in -5. On the other hand, for the type 2 component, the area is determined according to the bit width attribute based on the area estimation model. In the case of a component having two or more types of circuit configurations, such as the adder in FIG. 3, the area is obtained using an area estimation model of a circuit configuration having the smallest area.

(Delay Calculation Step ST4) Next, in the delay calculation step ST4, the area priority estimating section 8 of the trade-off estimating means 7 determines whether or not each register in the integrated circuit whose performance is to be estimated when the area is minimized. Calculate the path delay time. Specifically, using the delay estimation model and the number-of-stages estimation model of each component allocated by the analysis tree allocating means 6 and the driving capability and input capacity of a standard driver model (driver A in FIG. 4), The delay time of each register path in the integrated circuit to be estimated is obtained.

FIG. 8 is a diagram showing an example of a circuit expression in the trade-off estimating means 7. In FIG. 8, 35 indicates a parse tree, and 36, 37, 38, and 39 are components allocated by the parse tree allocating means 6, and 36, 39.
Represents a register, and 37 and 38 represent parts other than the register. Reference numerals 40 and 41 denote branches on the parse tree, reference numeral 42 denotes a connection relationship between the parse trees, and reference numeral 43 denotes an input / output branch of the parse tree. The path from the component 36 to the component 39 indicated by the arrow in the drawing is an inter-register path, and the internal delay times of the components 36, 37, 38 on the path and the wiring relating to the branches 40, 41 between the components. The delay time of the register-to-register path is obtained from the sum of the delay time and the wiring delay time related to the connection relationship 42 between the parse trees. Input / output branch of parse tree 4
No delay time is given to 3.

In the delay calculation step ST4, the delay time of the inter-register path is obtained by a series of steps as described below using a circuit expression as shown in FIG. (ST4-1) The gate delay time from the input to the output of the component is obtained from the delay estimation model. (ST4-2) The wiring delay time in the component is obtained by the following equation (1). Wiring delay time in component = Drive capability of driver A × (Input capacitance of driver A + Wiring capacitance) × (Number of stages from input to output of component) (1) Here, the wiring capacitance is calculated in the area calculation step ST3. It can be obtained from the virtual wiring length obtained by multiplying the obtained circuit area by a constant and the capacitance per unit length, and the number of stages from input to output of the component can be obtained from the component number estimation model. (ST4-3) The internal delay time of the component is
It is obtained by the sum of the gate delay time obtained in 4-1 and the wiring delay time in the component obtained in step ST4-2. (ST4-4) The delay time from the start point to the end point of the syntax analysis tree is obtained by the following equation (2). Delay time from the start point to the end point of the syntax analysis tree = Σ (internal delay time of component) + Σ (driving capacity of driver A × (input capacity of driver A + wiring capacity)) (2) where equation (2) Represents the sum of the wiring delay times between the components, and the wiring capacitance in this term corresponds to the area calculation step ST.
It can be obtained from the virtual wiring length obtained by multiplying the circuit area obtained in step 3 by a constant depending on the fanout number attribute of the branch of the syntax analysis tree, and the capacity per unit length. (ST4-5) The delay time of the inter-register path is obtained by the following equation (3). Delay time of inter-register path = Σ (delay time from start point to end point of syntax analysis tree) + Σ (driving capacity of driver A × (input capacity of driver A + wiring capacity)) (3) where equation (3) ) Represents the sum of the wiring delay times between the parse trees, and the wiring capacity in this term can be obtained in the same manner as the wiring capacity in equation (2).

(Determination Step ST5) Next, the determination step ST5
, The timing analysis unit 9 in the trade-off estimation unit 7 determines whether the delay time obtained by the area priority estimation unit 8 satisfies the given timing constraint information 4. If it is determined that the condition is satisfied, the estimation value output unit 12 outputs the estimation result 13 describing the area and the delay time, and the process ends. If it is determined that the path is not satisfied, the information of the critical path having the longest delay time among the unsatisfied critical paths is output to the performance candidate list creation unit 10, and the process proceeds to the following steps.

(Performance candidate list creation step ST6)
In the performance candidate list creation step ST6, the performance candidate list creation unit 10 in the trade-off estimating means 7 sets the {Area, Internal Delay Time, Driving Capability} for the component on the inter-register path having the largest delay time. A performance candidate list enumerating the represented performance candidates is created, and the performance candidate selection unit 11
Output to In the case of a component having two or more types of circuit configurations, such as the adder shown in FIG. 3, the estimated value in each circuit configuration is used as a performance candidate, and a component having a fanout number attribute of 2 or more is shown in FIG. Performance candidates are obtained by applying each driver.

FIG. 9 is a flowchart showing a process of creating a performance candidate list for one component in the performance candidate list creating step ST6. Referring to FIG. 9, a performance candidate list creation step ST
Step 6 will be described.

First, in step ST6-1, the area of the one component obtained in the area calculation step ST3 is set to A0, and in step ST6-2, the performance candidate list is initialized.

Next, in step ST6-3, an area and an internal delay time when the driver A is applied to the circuit configuration selected for the one component are obtained.
A set of {area difference from A0, internal delay time, driving capability of driver A} is added to the performance candidate list. The method of obtaining the internal delay time is the same as that in steps ST4-1 to ST4-3 of the delay calculation step ST4.

Next, in step ST6-4, it is determined whether or not the fan-out number attribute of the one component is 2 or more. If the fan-out number is not 2 or more, that is, it is 1, the process proceeds to step ST6-7. . If the fan-out number is 2 or more, in steps ST6-5 and ST6-6, the area and internal delay time when another driver is applied are determined, and the area difference from ｛A0, the internal delay time, the selected driver Is added to the performance candidate list.

Next, in step ST6-7, it is determined whether or not another circuit configuration exists for the one component. If it does not exist, the process ends. If it does, the circuit configuration is changed in step ST6-8, and the process returns to step ST6-3. Step ST6 is performed until the performance candidates are obtained for all the circuit configurations for the one component.
-3 are repeated.

(Performance Candidate Selection Step ST7) Next, in the performance candidate selection step ST7, the performance candidate selection section 11 of the trade-off estimating means 7 selects one performance candidate from the performance candidate list of each component, and A combination of performance candidates is determined in which the delay time of the inter-path satisfies the timing constraint information 4 and the increase in the area of the integrated circuit whose performance is to be estimated is minimized. The method of obtaining the delay time of the path is determined in steps ST4-4 to ST4-5 of the delay calculation step ST4.
The same as before. However, the value of the selected performance candidate is used as the driving capability.

(Area and Delay Changing Step ST8) Further, the performance candidate selecting section 11 sets the area and delay changing step S8.
At T8, the area of the integrated circuit whose performance is to be estimated and the delay time of all paths passing through the component whose performance candidate has been changed are changed.

After the area and delay change step ST8, in a decision step ST5, the timing analysis section 9 determines whether or not the delay time obtained in the area and delay change step ST8 satisfies the given timing constraint information 4. Is determined. The operation after the determination is as described above.

As described above, according to the present embodiment, by providing the trade-off estimating means 7 for obtaining the minimum area satisfying the timing constraint information 4, it is possible to accurately estimate the performance of the circuit after logic design in RTL. The problem of the circuit can be solved in the early stage of the design,
It is possible to shorten the design period.

Further, since the components stored in the estimation library 1 have the delay estimation model and the stage number estimation model, the gate delay time and the wiring delay time can be separately estimated, and the height according to the circuit area can be increased. It is possible to accurately estimate the wiring delay time.

A part stored in the estimation library 1 has an estimation model with several types of circuit configurations, and a performance candidate list creation unit for creating a performance candidate in which the application of the driver model to a part having a large number of fanouts is changed. Providing 10 enables highly accurate performance estimation.

(Second Embodiment) A second embodiment of the present invention will be described with reference to the drawings.

FIG. 10 is a functional block diagram of an integrated circuit performance estimating apparatus according to the second embodiment of the present invention. FIG.
1 is different from FIG. 1 in that a trade-off estimation unit 44 for the hierarchy and a floor plan unit 45 for an integrated circuit having a hierarchical structure are provided. Hereinafter, a hierarchical unit in the hierarchical structure is called a module. 10, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted in the present embodiment.

Reference numeral 44 denotes a trade-off estimating means for estimating the area and timing of an integrated circuit having a hierarchical structure using the driver library 2. The layer-oriented trade-off estimating unit 44 includes an area priority estimating unit 8, a hierarchical timing constraint setting unit 46 for setting a timing constraint for each hierarchy, a timing analyzing unit 9, a performance candidate list creating unit 10, a performance candidate selecting unit. 11. Reference numeral 45 denotes a floor plan unit that determines the arrangement of modules in a lower layer in an arbitrary layer and a schematic wiring path connecting these modules.

The operation of the apparatus for estimating the performance of an integrated circuit configured as described above will be described below with reference to the drawings.

FIG. 11 is a flowchart showing a performance estimating method in the integrated circuit performance estimating apparatus according to the second embodiment. The operation of the apparatus for estimating the performance of an integrated circuit according to this embodiment will be described with reference to FIG.

The operation of the parsing means 5 in the parsing step ST1, the operation of the parse tree allocating means 6 in the parse tree allocating step ST2, and the operation of the area priority estimating section 8 in the area calculating step ST3 are described in the first embodiment. Is the same as However, in the area calculation step ST3, the area of the integrated circuit whose performance is to be estimated is estimated for each hierarchy.

FIG. 12 shows the trade-off estimating means 4 for the hierarchy.
FIG. 4 is a diagram showing a circuit expression in FIG. Assuming that the highest hierarchy including the entire circuit is the first hierarchy, in FIG.
49 is a module of the second hierarchy below the first hierarchy, and 50 and 5
1 is a third-layer module below the second-layer module 48, 52 and 53 are third-layer modules below the second-layer module 49, 54 is a connection relation in the first layer, and 55 is a second layer. Is a connection relationship in the module 48 of the second hierarchy, and 56 is a connection relationship in the module 49 of the second hierarchy. Reference numeral 47 denotes an I / O cell connected to the outside. However, in the case where an arbitrary hierarchy is expressed not by a structure but by an operation in the HDL description 3, it is assumed that the hierarchy is constituted by a plurality of parse trees as shown in FIG. Therefore, FIG. 12 shows a path from the I / O cell 47 to the register of the module 53 through each layer, but the modules 50, 51, and 52 in the middle may have lower layers in some cases. Sometimes represented by a tree.

The area of each hierarchy obtained in the area calculation step ST3 is obtained by the sum of the area of the syntax analysis tree included in the hierarchy and the area of the module of the lower hierarchy. For example, in FIG. 12, the area of the module 48 is obtained by the sum of the areas of the modules 50 and 51 which are the lower layers.

(Module Arrangement / Schematic Wiring Step ST1)
0) Next, in the module arrangement / schematic wiring step ST10, the floor plan unit 45 uses the area of each module obtained by the area priority estimating unit 8 to determine the arrangement of the module of the lower hierarchy in an arbitrary hierarchy. At the same time, a general wiring path connecting the modules is determined.
For example, in FIG. 12, the arrangement of the modules 48, 49 and the like included in the first hierarchy is determined, and the schematic wiring path of the connection relation 54 between these modules is determined. The wiring capacity between modules is obtained from the wiring length and the capacity per unit length obtained from the schematic wiring path, and is input to the hierarchical timing constraint setting unit 46.

Next, in the delay calculating step ST4, the area priority estimating unit 8 calculates the delay time of each inter-register path in the integrated circuit, as in the first embodiment. However, the wiring delay time between modules is determined from the arrangement of the modules in each hierarchy and the wiring route connecting the modules determined by the floor plan means 45, and the delay time of the inter-register path is determined for each hierarchy using this. Ask for time.

(Timing constraint setting step ST1 for each layer)
1) Next, in the hierarchical timing constraint setting step ST11, the hierarchical timing constraint setting unit 46 sets a timing constraint for each module based on the timing constraint information 4.

FIG. 13 is a timing constraint setting step S for each layer.
It is a flowchart which shows T11.

First, in step ST11-1, the maximum delay time from input to output of each component is determined using the delay estimation model of each component stored in the estimation library 1. At this time, for components having a plurality of circuit configurations, a circuit configuration that maximizes the delay time is adopted, and the delay estimation model is used.

Next, in step ST11-2, using the driver A of the driver library 2, the maximum delay time of each path from the input to the output, from the input to the register, or from the register to the output in the module is determined. The calculation method at this time is the same as the delay calculation step ST4 according to the first embodiment.

Next, in step ST11-3, using the delay estimation model of each component stored in the estimation library 1, the minimum delay time from input to output of each component is determined. At this time, for components having a plurality of circuit configurations, a circuit configuration that minimizes the delay time is adopted, and the delay estimation model is used. For components having only a single circuit configuration, the maximum delay time and the minimum delay time are the same.

Next, in step ST11-4, the driver E having the maximum driving capability is used for the parts whose fan-out number is equal to or more than the constant N, and the driver A is used for the other parts. The minimum delay time of each path from the input to the output, from the input to the register, or from the register to the output in the module is obtained from the sum of the wiring delay time and the minimum delay time of each component. Where the constant N
Sets the internal delay times of the driver A and the driver E to Ia and Ie (Ia <Ie), respectively, and
When a and De (Da> De), the fan-out number corresponds to the wiring capacitance L such that Ia + L × Da = Ie + L × De.

Next, in step ST11-5, the minimum delay time of the inter-module wiring is obtained from the driving capability of the driver E by using the wiring capacity between the modules obtained in the block arrangement / schematic wiring step ST10, and the maximum delay is obtained. The time is obtained from the driving ability of the driver A.

Next, in step ST11-6, a register-to-register path extending between modules is selected.
In T11-7, the difference ΔP between the maximum delay time and the minimum delay time of the selected inter-register path is determined, and in step ST11-8, the difference ΔP is given from the maximum delay time of the selected inter-register path and the timing constraint information 4. The difference S from the timing constraint value is obtained.

Next, in step ST11-9, for each path from the input to the register, from the register to the output, or from the input to the output in the module on the selected inter-register path, in step ST11-2. Using the obtained maximum delay time and the minimum delay time obtained in step ST11-4, the following equation (4) is used.
Determines the constraint value.

Constraint value = maximum delay time−max (0, S × (maximum delay time−minimum delay time) / ΔP) (4) Equation (4) indicates that the maximum delay time of the inter-register path is the timing constraint information 4 If it is less than or equal to the timing constraint value given by, the maximum delay time of the route is used as the constraint value.

(Step ST12 of Determining Minimum Area Satisfying Timing Constraint) Next, in a step ST12 of determining a minimum area satisfying the timing constraint, based on the timing constraint in each module, the timing analysis unit 9 and the performance candidate list creation unit 10 and the performance candidate selection unit 11 determine the area and delay time of each module in the same manner as in the first embodiment, and output the results to the estimated value output unit 12.

As described above, by providing the floor plan means 45, the wiring delay time can be accurately calculated in consideration of the wiring path of the connection relation between modules, and the performance of the integrated circuit having a hierarchical structure can be reduced. It can be estimated with high accuracy.

In each embodiment, the estimation library 1
Each of the estimation models described above is represented by a function of the number of input signals or the input bit width, but other representations are also possible. For example, {Area, delay, number of stages, number of input signals} or {Area, delay, number of stages, input bit width}, expressed as a set of area, delay, number of stages and number of input signals or input bit width Is also good. Further, an existing cell library can be used as the estimation library 1.

In each of the embodiments, the timing constraint information 4 is given as a predetermined constraint. However, even if an area constraint is given together with or instead of this, the area of the integrated circuit is similarly set. And the timing can be estimated.

In each embodiment, at the beginning of the trade-off estimation, a so-called area-priority initial setting for obtaining the minimum area of the integrated circuit is performed. Instead, a driver model having the highest driving capability is applied. Thus, an initial setting may be performed so that the operation speed of the integrated circuit becomes the highest. In this case, the application of the driver model may be changed by the performance candidate selection unit 11 so as to reduce the drive capability of the components on the path where there is enough timing. This makes it possible to obtain an estimation result for an integrated circuit with strict timing constraints in a shorter time than in the case of initial setting with area priority.

In each of the embodiments, the area and timing of the integrated circuit are estimated. However, it is of course possible to estimate other performances. For example, by storing, in the estimation library 1, a model for estimating a moving charge amount during charging / discharging inside a component, in addition to an area estimation model, a delay estimation model, and a stage number estimation model for each component.
Power consumption during normal operation can be estimated from the estimated operation speed and the power supply voltage.

[0089]

As described above, according to the present invention, the RTL
Of the integrated circuit can be accurately estimated.
Further, even in the case of an RTL integrated circuit having a hierarchical structure, the performance can be accurately estimated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an integrated circuit performance estimation device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating information of a type 1 component stored in an estimation library in the integrated circuit performance estimation device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing information of type 2 components stored in an estimation library in the integrated circuit performance estimation device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing information held by a driver library in the integrated circuit performance estimation device according to the first embodiment of the present invention.

FIG. 5 is a flowchart showing a performance estimation method by the integrated circuit performance estimation device according to the first embodiment of the present invention.

FIG. 6A is a diagram illustrating an example of a parse tree in the process of a parse process performed by the integrated circuit performance estimating apparatus according to the first embodiment of the present invention, and FIG. 6B is a diagram illustrating the result of the parse process. It is a figure which is a parsing tree and what merged with the parsing tree of (a).

FIG. 7 is a diagram showing an example of an allocation result in a parse tree allocation unit of the integrated circuit performance estimation device according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a circuit expression in a trade-off estimating means of the integrated circuit performance estimating apparatus according to the first embodiment of the present invention.

FIG. 9 is a flowchart showing a performance candidate list creation step by the integrated circuit performance estimation device according to the first embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of an integrated circuit performance estimation device according to a second embodiment of the present invention.

FIG. 11 is a flowchart illustrating a performance estimation method by an integrated circuit performance estimation device according to a second embodiment of the present invention.

FIG. 12 is a diagram showing a circuit expression in a hierarchical trade-off estimating means of the integrated circuit performance estimating apparatus according to the second embodiment of the present invention.

FIG. 13 is a flowchart showing a hierarchical timing constraint setting process by the integrated circuit performance estimating apparatus according to the second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 estimation library 2 driver library 3 HDL description 4 timing constraint information 5 syntax analysis means 6 parse tree allocation means 7 trade-off estimation means 8 area priority estimation section 9 timing analysis section 10 performance candidate list creation section 11 performance candidate selection section 12 estimated value Output means 44 Hierarchical trade-off estimating means 45 Floor plan means 46 Hierarchical timing constraint setting unit

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50 JICST file (JOIS)

Claims (14)

(57) [Claims] 1. An apparatus for estimating the performance of an integrated circuit at a register transfer level design stage, wherein an estimation model for estimating the performance of each component expressing the register transfer level integrated circuit is stored. A library, a driver library that models and stores the relationship between the driving capability and area of the driver that drives the wiring, and a register transfer level integrated circuit that is expressed by the connection relation of the parts. And a trade-off estimating means for estimating a performance satisfying a predetermined constraint while changing the application of the driver model stored in the driver library as necessary while applying the estimation model stored in the driver library. An integrated circuit performance estimation device. 2. The integrated circuit performance estimating apparatus according to claim 1, wherein said trade-off estimating means comprises:
An integrated circuit performance estimating apparatus for estimating a minimum area satisfying a given timing constraint. 3. The integrated circuit performance estimating apparatus according to claim 1, wherein the expression represented by the parse tree representing the integrated circuit at the register transfer level is expressed by a part in which the estimation model is stored in the estimation library. By assigning to each section,
An apparatus for estimating the performance of an integrated circuit, comprising: a parse tree allocating unit that converts the expression into a representation based on a connection relation of components and inputs the parse tree to the trade-off estimating unit. 4. The integrated circuit performance estimating device according to claim 3, wherein a description in a hardware description language, which represents the integrated circuit at a register transfer level, is converted into an expression by a syntax analysis tree by parsing, An apparatus for estimating the performance of an integrated circuit, comprising: a parsing means for inputting to the parse tree allocating means. 5. The integrated circuit performance estimating device according to claim 1, wherein the trade-off estimating means estimates a minimum area of the integrated circuit and a delay time of each inter-register path when the area is minimized. An area priority estimating unit, a timing analyzing unit that determines whether or not a delay time of each inter-register path of the integrated circuit satisfies a timing constraint given to the integrated circuit; A performance candidate list creator for creating a performance candidate list in which performance candidates are enumerated while changing the application of the driver model for each component on a register-to-register path whose delay time does not satisfy the timing constraint; For each component on the inter-register path that does not satisfy the timing constraint, the delay time of the inter-register path satisfies the timing constraint, and In order to minimize the product increase, each of the performance candidates is selected from the performance candidate list created by the performance candidate list creation unit, and the area of the integrated circuit when the selected performance candidate is set as the performance of each component. And a performance candidate selecting unit for estimating a delay time of each inter-register path. 6. The device for estimating the performance of an integrated circuit according to claim 1, wherein an integrated circuit having a hierarchical structure is a target of performance estimation. The apparatus further comprises floor plan means for determining a route of a wiring connecting between modules, and wherein the trade-off estimating means comprises:
While considering the wiring delay time between modules estimated from the wiring route determined by the floor plan means,
An integrated circuit performance estimating apparatus for estimating performance satisfying a predetermined constraint. 7. The integrated circuit performance estimating device according to claim 6, wherein said hierarchically oriented trade-off estimating means comprises: a minimum area of said integrated circuit; and a delay time of each inter-register path when the area is minimized. An area priority estimating unit for estimating each layer, a timing constraint given to the integrated circuit, an arrangement of modules in each layer determined by the floor plan means, and a wiring path connecting the modules. A timing constraint setting unit for each layer that sets a timing constraint for each layer based on the timing of the hierarchy, wherein the delay time of the register-to-register path in each layer of the integrated circuit is set by the timing constraint setting unit for the layer. A timing analyzer that determines whether the constraint is satisfied or not, and a register whose delay time does not satisfy the timing constraint A performance candidate list creator that creates a performance candidate list listing performance candidates while changing the application of the driver model to each component on the path; and a path between registers whose delay time does not satisfy the timing constraint. The performance candidate created by the performance candidate list creation unit such that the delay time of this inter-register path satisfies the timing constraint and the increase in the area of the integrated circuit in the hierarchy is minimized. A performance candidate selecting unit for estimating an area in the hierarchy of the integrated circuit and a delay time of each inter-register path when each of the performance candidates is selected from the list and the selected performance candidate is set as the performance of each component. An apparatus for estimating the performance of an integrated circuit, comprising: 8. A method for estimating the performance of an integrated circuit at a register transfer level design stage, comprising: an estimation model for estimating the performance of each component expressing the integrated circuit at a register transfer level; Using the driver model in which the relationship between the driving capability and the area of the driver to be driven is modeled, and applying the above estimation model to each component of the integrated circuit at the register transfer level represented by the connection relationship of the components. And a trade-off estimation method for estimating a performance satisfying a predetermined constraint while changing the application of the driver model as necessary. 9. The integrated circuit performance estimation method according to claim 8, wherein said trade-off estimation is to estimate a minimum area of said integrated circuit satisfying a given timing constraint. A method for estimating the performance of an integrated circuit. 10. The method for estimating the performance of an integrated circuit according to claim 8, wherein, as a pre-process, an expression using a parse tree representing an integrated circuit at a register transfer level is obtained, and a component for which an estimation model is prepared is analyzed using a parse tree. A method for estimating the performance of an integrated circuit, characterized by converting the expression into an expression based on the connection relation of parts by allocating the expression to each node. 11. The method for estimating the performance of an integrated circuit according to claim 10, wherein a description in a hardware description language, which represents the integrated circuit at the register transfer level, is parsed as a preceding step, so that the description is represented by a parse tree. A method for estimating the performance of an integrated circuit, wherein the method comprises converting. 12. The method for estimating the performance of an integrated circuit according to claim 8, wherein in the trade-off estimation, the area of each component of the integrated circuit is obtained using the estimation model, and the area of each obtained component is determined based on the obtained area of each component. Calculating the area, and for the integrated circuit, calculating the internal delay time and the wiring delay time of each component using the estimation model and the driver model, and based on the determined internal delay time and the wiring delay time of each component. Determining the delay time of the inter-register path; and determining whether the delay times of all the inter-register paths satisfy the given timing constraint with respect to the integrated circuit. While the required area is estimated as the minimum area, if it is not satisfied, the delay time does not satisfy the timing constraint. While changing the application of the driver model, the inter-register path satisfies the timing constraint, and a performance candidate that minimizes the increase in the area of the integrated circuit is obtained, and the obtained performance candidate is used as the performance of each component. Obtaining the area of the integrated circuit and the delay time of each inter-register path when the setting is performed. 13. The method for estimating the performance of an integrated circuit according to claim 8, wherein an integrated circuit having a hierarchical structure is subjected to performance estimation. A floor plan step of determining a route of a wiring connecting the plurality of wiring lines, wherein the trade-off estimation is performed on the integrated circuit while considering a wiring delay time between modules estimated from a wiring route determined by the floor plan step. And a method for estimating a performance satisfying a predetermined constraint. 14. The method for estimating the performance of an integrated circuit according to claim 13, wherein in the trade-off estimation, an area of each component of the integrated circuit is obtained using the estimation model, and the area of each obtained component is determined based on the obtained area of each component. Determining the area for each layer; determining, for the integrated circuit, the internal delay time and the wiring delay time of each component using the estimation model and the driver model; and determining each area determined in the floor plan step. Determining the wiring delay time between the modules from the arrangement of the modules and the wiring route connecting the modules in the above, and obtaining the delay time of the register-to-register path for each hierarchy based on the obtained delay times; With respect to the timing constraints given to the integrated circuit and each of the timing constraints determined in the floorplanning process. Setting timing constraints for each layer based on the arrangement of the modules in the layer and the route of the wiring connecting the modules; and for the integrated circuit, for each layer, all the inter-register paths are It is determined whether or not the set timing constraint is satisfied. If so, the currently calculated area is estimated as the minimum area in the hierarchy. If not, the delay time does not satisfy the timing constraint. For each component on the inter-register path, while changing the application of the driver model, the inter-register path satisfies the timing constraint, and the performance candidate that minimizes the area increase in the hierarchy of the integrated circuit is determined. The area of the integrated circuit in the hierarchy when the determined performance candidate is set as the performance of each component, and Performance estimation method for an integrated circuit, which comprises carrying out by the step of determining the delay time of the register-to-register path.