JP2925005B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to an electrically erasable nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, a semiconductor memory device called a flash memory, which is non-volatile and capable of batch erasing, in particular, has been adopted in a wide range of fields. Development for low voltage is being actively conducted. The rewriting speed of this flash memory depends on the voltage applied to the tunnel gate insulating film below the floating gate. To increase the rewriting speed, it is necessary to increase the voltage applied to the tunnel gate insulating film. However, applying a large voltage at the time of rewriting in order to apply a high voltage to the tunnel gate insulating film, even if this is preferable in terms of speeding up, is against the trend of lowering the voltage. I will. Therefore, the capacitance ratio (the ratio C _CG-FG / C _FG of the coupling capacitance C _CG-FG between the control gate and the floating gate and the total coupling capacitance C _FG of the floating gate and the source / drain, channel and control gate) is increased. Therefore, it is required to increase the voltage applied to the tunnel gate insulating film without increasing the voltage used at the time of rewriting.

In addition, a contact hole for electrically contacting a drain and a source with a wiring made of, for example, aluminum is difficult to reduce in size and needs to have a margin for misalignment. It is one obstacle in aiming at. As a method of reducing the trouble due to the contact hole, a cell array structure called a contactless method has been proposed. FIG. 7 is a plan view showing an example of a contactless flash memory cell array proposed in Japanese Patent Application Laid-Open No. 61-222159. As shown in FIG. 7, a long source / drain diffusion layer 3 is formed so as to be orthogonal to the control gate 9 also serving as a word line. Are formed, and the source / drain diffusion layer is connected to a bit line (not shown) via this (hereinafter, this is referred to as a first conventional example). In this type of memory, the source / drain diffusion layers are shared by a plurality of memory cells in this way, and the bit line and the source / drain diffusion layers are contacted only at one location for every plural memory cells. Thus, the size of the unit memory cell is reduced to achieve high integration.

FIG. 8 is a sectional view taken along line XX of FIG. A p-type impurity region 2 is provided on an n-type silicon substrate 1, and an n-type source / drain diffusion layer 3 is formed in a surface region of the p-type impurity region 2. A first gate insulating film 6 and a thick silicon oxide film 12 are formed on a semiconductor substrate, a floating gate 7 is formed on the first gate insulating film, and a second gate insulating film 8 is formed thereon.
, A control gate 9 is formed.

FIGS. 9 to 11 are cross-sectional views in the order of steps for explaining a first conventional manufacturing method. First, as shown in FIG. 9, a p-type impurity region 2 is formed on the surface of an n-type silicon substrate 1, an element isolation region (not shown) is formed by a known method, and a tunnel is formed on the p-type impurity region 2. A first gate insulating film 6 serving as a gate insulating film is formed, and a first conductive film layer 7a for forming a floating gate is formed thereon using, for example, polysilicon.

Next, as shown in FIG. 10, a resist film 10 is formed by photolithography, and the first conductive film layer 7a is patterned using the resist film 10 as a mask to be processed into a long conductive film layer. Next, an n-type impurity is ion-implanted using the resist film 10 as a mask to form the source / drain diffusion layers 3. Next, as shown in FIG. 11, the resist film 10 is removed, a second gate insulating film 8 is formed on the first conductive film layer 7a by thermal oxidation, and at the same time, the source / drain diffusion layers 3 are formed.
A thick silicon oxide film 12 is formed thereon. The source / drain diffusion layer 3 is oxidized by the implanted impurity at a speed, for example, five times that of the first conductive film layer 7a. Therefore, for example, when the second gate insulating film 8 is formed to a thickness of 20 nm, the thick silicon oxide film 12 is formed to a thickness of about 100 nm. During this oxidation, a bird's beak enters below the first conductive film layer 7a (floating gate 7).

Thereafter, a second conductive film layer for forming a control gate is formed, a resist film (not shown) is formed by photolithography, and the second conductive film layer and a strip-shaped If the control gate 9 and the floating gate 7 are formed by etching the one conductive film layer 7a, the first conventional nonvolatile semiconductor memory device shown in FIG. 8 is obtained.

Here, the reason why the thick silicon oxide film 12 needs to be formed on the source / drain diffusion layer 3 will be described. In the contactless cell, instead of taking a contact in each memory cell, a source / drain diffusion layer is shared by a plurality of adjacent cells, and a contact is taken at one place for each of a plurality of cells. Therefore, the source / drain diffusion layers 3 must be formed continuously between adjacent cells. Thus, in the etching step for forming the control gate 9 and the floating gate 7, the conductive film layer on the source / drain diffusion layer 3 only has the second conductive film layer for forming the control gate. Therefore, if the thick silicon oxide film does not exist on the source / drain diffusion layer 3, the source / drain diffusion layer 3 is exposed when the second conductive film layer is etched. When the next first conductive film layer is etched, the substrate is etched,
There is a possibility that the drain diffusion layer is disconnected. This thick silicon oxide film 12 functions as an etching stopper film at the time of this etching and prevents disconnection of the source / drain diffusion layers.

In the first conventional example, since the side surface of the floating gate 7 is also covered with the control gate, the coupling capacitance between the floating gate and the control gate 9 can be increased. However, in this structure, a bird's beak of the thick silicon oxide film 12 enters below the floating gate 7. In such a structure in which bird's beaks bite under the floating gate, the characteristic fluctuation due to the repetition of the write / erase operation becomes large.
-169, pp. 41-46.

FIG. 12 is a cross-sectional view of a nonvolatile semiconductor memory device proposed in Japanese Patent Laid-Open Publication No. HEI 5-15251 (hereinafter, this conventional example is referred to as a second conventional example). This second
The plan view of the conventional example is the same as the plan view of the first conventional example shown in FIG. 7, and FIG. 12 is a cross-sectional view taken along the line XX in FIG. In this conventional example, a thick silicon oxide film 12 formed by thermal oxidation in the first conventional example is used.
Instead, the silicon oxide film deposited by the CVD method is etched back to form a thick silicon oxide film 12a having a flat surface. According to this conventional example, disconnection of the source / drain diffusion layer 3 which is a problem at the time of etching when forming the control gate and the floating gate can be more reliably prevented. Also, the problem of bird's beak biting under the floating gate, which is a problem in the first conventional example, is solved.

Although not of the contactless type, a nonvolatile memory having the structure shown in FIGS. 13 and 14 has also been proposed. FIG. 14 is a plan view of the memory cell array, and FIG. 13 is a cross-sectional view along the II direction. 13 and 14, parts corresponding to parts in FIGS. 7 and 8 are denoted by the same reference numerals. In this conventional example, the substrate is etched by being self-aligned with the floating gate 7 to form a groove, and an element isolation oxide film 13 is buried in the groove so that the surface thereof is lower than the substrate surface. Is formed so as to be in contact with the side surface of the floating gate via the second gate insulating film 8. By doing so, it is possible to reduce the cell size while increasing the capacity ratio. However, since it is not contactless, the reduction in cell size is not sufficient.

[0012]

In the above-mentioned first conventional example, there is a problem that the characteristics become unstable due to bird's beaks penetrating under the floating gate. On the other hand, in the second conventional example, the control gate 9 has a problem. Does not exist on the side surface of the floating gate 7, the coupling capacitance between the control gate 9 and the floating gate 7 is reduced accordingly, which is disadvantageous for low voltage driving. Therefore, the problem to be solved by the present invention is to reduce the cell size by adopting a contactless cell system, prevent bird's beaks, and increase the coupling capacitance between the floating gate and the control gate. .

[0013]

SUMMARY OF THE INVENTION The object of the present invention is to form a self-aligned groove on one side of a floating gate and form source / drain diffusion layers on the bottom and side of the groove. The insulation film is
Embedded below the bottom of the operating gate ,
This can be solved by forming the control gate so as to be orthogonal to the groove.

[Operation] In the nonvolatile semiconductor memory device of the present invention, a source / drain diffusion layer is formed on the bottom and side surfaces of a groove formed by etching a substrate, and the inside of the groove is filled with an insulating film serving as an etching stopper. ing.
With this configuration, the bird's beak does not go under the floating gate, and the control gate is arranged so as to be in contact with the upper surface and the side surface of the floating gate via the gate insulating film. Therefore,
According to the present invention, it is possible to provide a nonvolatile semiconductor memory device that operates stably and has a large capacitance ratio related to the control gate.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile semiconductor memory device according to the present invention comprises a plurality of grooves formed in parallel on the surface of a semiconductor layer of a first conductivity type, and second grooves formed on the bottom and side surfaces of the grooves. A conductive impurity region, a buried insulating film buried in the trench, a plurality of control gates formed on the semiconductor substrate so as to be orthogonal to the trench, a mesa portion of the semiconductor layer, and the control gate A floating gate formed between the semiconductor layer and the control gate via a first gate insulating film and a second gate insulating film, respectively.

Further, a method of manufacturing a nonvolatile semiconductor memory device according to the present invention includes:
A first gate insulating film on the conductive type semiconductor layer,
(2) forming a first resist film on the first conductive film layer and performing etching using the first resist film as a mask to reach the inside of the semiconductor layer; Processing the conductive film layer into a strip shape and forming a plurality of grooves in parallel with the semiconductor layer; and (3) introducing a second conductivity type impurity into the surface of the semiconductor layer to form a bottom surface of the groove and Forming a second conductivity type impurity region on the side surface; and (4) filling the trench with an insulating film.
(5) forming a second gate insulating film on the surface of the first conductive film layer and forming a second conductive film layer on the entire surface;
(6) A second resist film is formed on the second conductive film layer, and the second and first conductive film layers are selectively etched using the second resist film as a mask to form a plurality of elongated films orthogonal to the grooves. Forming a plurality of control gates and a plurality of floating gates.

[0017]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line AA of FIG. As shown in FIG. 2, p-type impurity region 2 is formed on the main surface of n-type silicon substrate 1, and a first gate insulating film 6 made of, for example, silicon dioxide is formed on p-type impurity region 2 via the same. Thus, a floating gate 7 made of, for example, polysilicon is formed. A groove 4 is formed in the p-type impurity region 2 so as to be self-aligned with the floating gate 7, and a source / drain diffusion layer 3 is formed on the bottom and side surfaces of the groove 4.

It is desirable that the groove 4 has the same depth as the insulating film thickness of an etching stopper formed in a later step. This etching stopper is used for patterning the control gate, the second gate insulating film and the floating gate. In addition, the thickness needs to be such that the source / drain diffusion layers between adjacent cells are not etched. The buried insulating film serving as the etching stopper is made of, for example, silicon dioxide. On the buried insulating film and on the upper surface and the side surface of the floating gate 7, for example, a second film made of three layers sandwiching silicon nitride with silicon dioxide is used. A control gate 9 is formed via a gate insulating film 8.

Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described in detail with reference to FIGS. First, n
After a p-type impurity region 2 is formed on the main surface of the silicon substrate 1 and an element isolation region (not shown) is formed by a known method, a first region is formed on the p-type impurity region 2 as shown in FIG. After a gate insulating film 6 is formed and a first conductive film layer 7a made of, for example, polysilicon is formed thereon, a resist film 10 having a predetermined pattern is formed by photolithography. The thickness of the first gate insulating film 6 is, for example, 10 nm, and the thickness of the first conductive film layer 7a is, for example, 150 n.
m.

Next, as shown in FIG.
Is used as a mask, the first conductive film layer 7a, the first gate insulating film 6, and the p-type impurity region 2 are etched to form the trench 4 self-aligned with the floating gate. The depth of the groove 4 is, for example, 150 nm. Next, the resist film 10
Is removed, and ions such as arsenic are removed from the first conductive film layer 7.
Is used as a mask for implantation. At this time, the entire semiconductor substrate is tilted so that the angle of implantation with respect to the semiconductor substrate is, for example, 30 degrees, and the implantation is further performed while rotating the semiconductor substrate. As a result, ions can be implanted into the side surfaces on both sides of the groove 4, and the source / drain diffusion layers 3 are formed on the side surfaces and the bottom surface of the groove 4. The reason that the resist film 10 is removed before the ion implantation is that the oblique ion implantation is performed, so that if the resist film 10 is present, the resist film 10 is shaded and ions are not implanted into a desired region.

Next, as shown in FIG. 5, a silicon oxide film 5a that completely fills the trench is formed by, eg, CVD. Thereafter, as shown in FIG. 6, the oxide film 5 is etched back by anisotropic etching to bury the oxide film 5 in the groove.
So that it remains. At this time, the etching is performed so that the surface of the buried oxide film 5 is slightly lower than the lower surface of the first conductive film layer 7a. Next, a second gate insulating film 8 is formed, and a second conductive film layer for forming a control gate is formed thereon. The second gate insulating film is a film having a three-layer structure of, for example, silicon dioxide, silicon nitride, and silicon dioxide.
m thickness. The second conductive film layer is, for example,
It is composed of two layers of polysilicon having a thickness of 150 nm and tungsten silicide having a thickness of 150 nm. The second conductive film layer, the second gate insulating film 8 and the first conductive film layer 7a
Are etched using a resist film extending in a direction orthogonal to the groove 4 as a mask, so that the control gate 9
By forming the floating gate 7, a memory cell having the structure shown in FIG. 2 is obtained. After that, an interlayer insulating film is deposited,
After opening a contact hole, a wiring is formed using Al or the like, whereby a nonvolatile semiconductor memory device is manufactured.

In the nonvolatile semiconductor memory device thus formed, the region where the floating gate 7 and the control gate 9 oppose each other with the second gate insulating film 8 interposed therebetween is formed not only on the upper surface but also on the side surface of the floating gate 7. Therefore, the coupling capacitance between the floating gate 7 and the control gate 9 increases accordingly. As an example,
The channel length is 0.3 μm, and the channel width (the length of the floating gate in the direction perpendicular to the plane of FIG. 2) is 0.3 μm.
m, the thickness of the floating gate is 150 nm, the equivalent oxide thickness of the first gate insulating film is 7 nm, and the equivalent oxide thickness of the second gate insulating film is 14 nm. Is compared between the second conventional example and the embodiment of the present invention.

The area of the upper surface of the floating gate is A
= 0.3 × 0.3 = 0.09 μm ² , and the area of the side surface of the floating gate is B = 0.3 × 0.15 =
0.045 μm ² . Capacity ratio of the second conventional example = (A / 0.014) / (A /
0.014 + A / 0.007) = 0.33 The capacity ratio of the cell of the embodiment of the present invention = (A / 0.014 + 2)
B / 0.014) / (A / 0.014 + A / 0.007
+ 2B / 0.014) = 0.5, and a capacity ratio 1.5 times higher than that of the second conventional example can be obtained by the present invention. Here, the equivalent oxide film thickness of the second gate insulating film on the side surface of the floating gate was assumed to be equal to the equivalent oxide film thickness of the second gate insulating film on the upper surface of the floating gate.

[0024]

As described above, in the nonvolatile semiconductor memory device of the present invention, trenches are dug on both sides of the floating gate, source / drain diffusion layers are formed on the bottom and side surfaces thereof, and an insulating stopper serving as an etching stopper is formed. Since the film is buried in the groove, the advantage of the contactless method is utilized to reduce the size of the cell array, prevent bird's beaks from digging under the floating gate, and increase the coupling capacitance of the floating gate. be able to. Therefore, according to the present invention, it is possible to provide a nonvolatile semiconductor memory device having high operation stability, high writing speed, and high density integration.

[Brief description of the drawings]

FIG. 1 is a plan view showing a cell array according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a cross-sectional view illustrating a manufacturing method according to an embodiment of the present invention at an intermediate stage of the process.

FIG. 4 is a cross-sectional view illustrating a manufacturing method according to an embodiment of the present invention at an intermediate stage of the process.

FIG. 5 is a cross-sectional view illustrating a manufacturing method according to an embodiment of the present invention at an intermediate stage of the process.

FIG. 6 is a cross-sectional view illustrating a manufacturing method according to an embodiment of the present invention at an intermediate stage of the process.

FIG. 7 is a plan view of a first conventional cell array.

FIG. 8 is a sectional view taken along line XX of FIG. 7;

FIG. 9 is a cross-sectional view illustrating a manufacturing method of the first conventional example at an intermediate stage of a process.

FIG. 10 is a cross-sectional view illustrating a manufacturing method of the first conventional example at an intermediate stage of the process.

FIG. 11 is a cross-sectional view illustrating a manufacturing method of the first conventional example at an intermediate stage of the process.

FIG. 12 is a sectional view of a second conventional example.

FIG. 13 is a sectional view of another conventional example.

FIG. 14 is a plan view of another conventional example.

[Explanation of symbols]

 Reference Signs List 1 n-type silicon substrate 2 p-type impurity region 3 source / drain diffusion layer 4 trench 5 buried oxide film 5 a silicon oxide film 6 first gate insulating film 7 floating gate 7 a first conductive film layer 8 second gate insulating film 9 control gate Reference Signs List 10 resist film 11 contact 12, 12a thick silicon oxide film 13 element isolation oxide film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (5)

(57) [Claims] 1. A plurality of grooves formed in parallel on the surface of a semiconductor region of a first conductivity type, an impurity region of a second conductivity type formed on the bottom and side surfaces of the groove, and embedded in the groove. a buried insulating film, a plurality of control gates formed on said semiconductor region so as to be perpendicular to the grooves, the intersection of the mesa portion and the control gate of said semiconductor region, said control and said semiconductor region A non-volatile semiconductor memory device having a floating gate formed between a first gate insulating film and a second gate insulating film between the gate and the gate;
The side of the loading gate parallel to the groove is the side of the groove
And the side parallel to the control gate
In front of the roll gate
The upper surface of the buried insulating film is
A nonvolatile semiconductor memory device characterized by being lower than a lower surface . 2. The nonvolatile semiconductor memory device according to claim 1, wherein said control gate is formed so as to cover a side surface of said floating gate parallel to said groove . 3. The method according to claim 1, wherein: (1) forming a first conductive type semiconductor region on the semiconductor region ;
Forming a first conductive film layer with the gate insulating film interposed therebetween; and (2) forming a first conductive film layer and the semiconductor region with respect to the first conductive film layer and the semiconductor region.
Etching is carried out continuously Te, the semiconductor regions with processing the first conductive film layer into strips, and forming a plurality of grooves in parallel, (3) a second conductive on the surface of the semiconductor region by introducing the type of impurity, and forming an impurity region of a second conductivity type on the bottom and side surfaces of the groove, (4) the surface height of the insulating film in the trench is the first guide
Burying to be lower than the lower surface of the conductive layer, and forming a (5) a second conductive film layer on the entire surface to form a second gate insulating film on the surface on the first conductive film layer, (6) continuously and selectively etching the second and first conductive film layers to form a plurality of control gates and a plurality of floating gates orthogonal to the groove. Manufacturing method of a nonvolatile semiconductor memory device. 4. The method according to claim 3, wherein, in the step (3), impurity ions are implanted into the substrate obliquely while rotating the substrate. 5. The method according to claim 4, wherein in the step (4), an insulating film is deposited on the entire surface and etched back so that the surface thereof is lower than the lower surface of the first conductive film layer. A method for manufacturing a nonvolatile semiconductor memory device according to claim 3.