JP2924281B2 - Address pointer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address pointer for a fixed-point arithmetic processor, and more particularly to a method for generating a designated address.

[0002]

2. Description of the Related Art An address pointer of a conventional fixed-point arithmetic processor will be described with reference to the drawings.

FIG. 3 is a block diagram of an address pointer of a conventional fixed-point arithmetic processor and its periphery.

A data bus 301 is used for data transfer between registers. Reference numeral 302 denotes a logic operation circuit unit (ALU) for fixed-point data.
The contents of the register are compared with 306 and 307 described later in the binary operation.
Performs the operation specified by the program with the contents of the register as input. Reference numeral 303 denotes a flag register that holds the state of the operation result in the ALU 302. 304 and 305 are operation result output registers for holding the operation results in the ALU 302. Reference numeral 306 denotes an input register for holding input data to the ALU 302, and its input is data output to the data bus 301. 307 is ALU3
02 is an input register for holding input data to the input 02, and the input is data held in the operation result output register 304 or 305. Reference numeral 308 denotes a barrel shifter that performs a left / right shift process on the data in the input register 306 or 307 by a shift amount specified in 309 described later. Reference numeral 309 denotes a shift amount setting register for specifying the shift amount of the barrel shifter 308, which is connected to the data bus 301. Numeral 310 designates the data held in either one of the input registers 306 and 307 as a barrel shifter 308.
Is a multiplexer for selecting whether to input the data. 311
Is a normalization shift amount detection circuit for the data held in the input register 307, and the barrel shifter 308 shifts the data by the shift amount detected by this circuit to perform normalization processing. Reference numeral 312 denotes a dedicated bus for outputting the shift amount to the internal data bus. A memory 313 for storing various data is connected to the data bus 301. 314 is a data memory 313
Is connected to the data bus 301 by an address pointer designating the address of the data bus. Therefore, a change in the contents of the address pointer 314 is caused by data input via the data bus 301 or data which is incremented / decremented with respect to data already stored,
Done by one of

The value of the data held in the input register 307 and the value detected by the normalizing shift amount detection circuit 311 are as shown in Table 1 when the data length is n bits.

[0006]

[Table 1]

[0007]

In the above-described address pointer of the conventional fixed-point arithmetic processor, the contents of the address pointer are changed with respect to data input via the data bus or data already stored. However, there is only one method of the incremented / decremented data, and the following problem occurs.

FIG. 4 is a diagram showing the data format of the fixed-point arithmetic processor and the range of numerical values.
(A) is a data format of a fixed-point arithmetic processor. When the data length is n bits, the MSB (nth
Bit) indicates a sign bit, the (n−1) th bit is 2 ⁻¹ , the (n−2) th bit is 2 ⁻² , and the first bit is 2
Indicates the value ^of-(n-1) .

A decimal point exists between the n-th bit and the (n-1) -th bit. Therefore, the range of numerical values that can be handled is (b)
become that way. When the sign bit is 0 and the other bits are all 1, the maximum value is obtained, and the numerical value is 0.99999.
... is shown. Conversely, when the sign bit is 1 and the other bits are all 0, the minimum value is obtained, and the numerical value indicates -1.0.

Consider the execution of a root function by a fixed-point arithmetic processor. Since there is no hardware for executing this function, all the functions are realized by using an arithmetic unit by a program. An approximation formula is used to implement the root function. This approximation is generally applicable to input values between 0.5 and 1.0. In other words, if the input value is in the range of 0.5 to 1.0, the approximate expression can be applied as it is, but an input outside the range requires some contrivance. This equation is shown below.

The same applies to the implementation of most functions such as logs and exponents, not limited to the root.

Approximate route expression y = f (z) (where 0.
When 5 ≦ z <1.0), the input value x is 0.5 ≦ x
In the case of <1.0, equation (1) is obtained.

[0013]

When the input value x is 0.0 <x <0.5, the expression (2) is obtained.

[0015]

When the input value x is 0.0, equation (3) is obtained.

[0017]

Here, the processing of equation (2) is called normalization.

The processing procedure of the root function using the above-described method by the conventional fixed-point arithmetic processor will be described.

The data memory 313 stores data as shown in FIG. 2 in advance.

The processing is a flow chart as shown in FIG. 5, and can be roughly divided into five steps.

Step 1 It is determined whether the data x held in the register 304 is 0 or not. When x = 0, the program ends with y = 0.

Step 2 The data x held in the register 304 is supplied to the barrel x via the input register 307.
The data is input to the shifter 308. At this time, the input register 30
The value detected by the normalization shift amount detection circuit 311 with respect to the data held in 7 is given to the barrel shifter 308, and the barrel shifter 308 executes normalization processing.

The value of z is obtained in the output register 304 as the output of the barrel shifter 308.

The value detected by the normalizing shift amount detection circuit 311 is K.

Step 3 From the value of K output from the dedicated bus 312 and the data memory,
Get the value of ^{-K / 2} .

Step 4 f (z) is calculated from the value of z.

Step 5 2− ^{K / 2} · f (z) is calculated from the results of Step 3 and Step 4 to obtain a route x.

The value of the data held in the input register 307 in step 2 and the value detected by the normalizing shift amount detecting circuit 311 are as shown in Table 2 when the data length is n bits.

[0030]

[Table 2]

Here, attention is paid to the processing of step 3. Step 3 comprises the following processing.

The sqrt shown in FIG.
Transfer the address of tbl.

The value of K output from the dedicated bus 312 and the value sqrttbl of the register 305 are added, and
Output to 05.

The contents of register 305 are transferred to address register 314.

The contents of the data memory 313 indicated by the address register 314 are transferred to the register 305. As a result, ^{a value} of 2-K / 2 is obtained in the register 305.

According to this, four steps are required to obtain the value of 2 ^{−K / 2 in} the register 305, and this processing is redundant for an arithmetic processor that requires high speed.

As described above, in the fixed-point arithmetic processor having the conventional address pointer, there is a problem that the processing time becomes long in the function operation.

The present invention has been made in view of the above problems, and has as its object to provide an address pointer of a fixed-point arithmetic processor capable of reducing the processing time for a function operation.

[0039]

The address pointer of the fixed-point arithmetic processor according to the present invention includes an adder for adding the output value of the normalizing shift amount detecting circuit to the value of the address pointer of the data memory. .

[0040]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an address pointer and its periphery of a fixed-point arithmetic processor according to an embodiment of the present invention.

The description of the same parts in FIG. 1 as those in FIG. 3 will be omitted.

The difference between this system and the conventional one is that
A dedicated bus 113 for using the value detected by the normalizing shift amount detection circuit 111 as a value specifying the address of the data memory 112, and the value output from the 113 and the value of the original address pointer 114 are added. Adder 115, the address of data memory 112 is 113,
The point is that a multiplexer 116 for selecting which of the outputs 114 and 115 is designated is provided.

The processing of the root function using the above-described method in the fixed-point arithmetic processor having the address pointer according to the present invention will be described.

The data memory 112 previously stores data as shown in FIG. This is the same as the prior art.

The processing becomes a flow chart as shown in FIG. 6, and can be roughly divided into five steps as in the prior art.

Step 1 It is determined whether or not the data x held in the register 104 is 0. When x = 0, the program ends with y = 0.

Step 2 The data x held in the register 104 is transferred to the barrel x via the input register 107.
The data is input to the shifter 108. At this time, the input register 10
The value detected by the shift amount detection circuit for normalization 111 for the data held in 7 is given to the barrel shifter 108, and the barrel shifter 108 executes normalization processing. Z is output to the output register 104 as the output of the barrel shifter 108.
Get the value of

The value detected by the normalizing shift amount detection circuit 111 is K.

Step 3 From the value of K output from the dedicated bus 113 and the data memory,
Get the value of ^{-K / 2} .

Step 4 f (z) is calculated from the value of z.

Step 5 2− ^{K / 2} · f (z) is calculated from the results of Step 3 and Step 4 to obtain a route x.

Here, attention is paid to the processing in step 3. Step 3 comprises the following processing.

Sqrtt is stored in the address register 114.
The address of bl is transferred.

The value K detected by the normalizing shift amount detection circuit 111 in step 2 has already been output to the dedicated bus 113.

The value sqrt of the address register 114
The contents of the data memory 112 are transferred to the register 105 using the value obtained by adding tbl and the output value K of the dedicated bus 113 as an address pointer. Thereby, the register 105
To obtain a value of 2- ^{K / 2} .

According to this, two steps are required to obtain the value of 2 ^{−K / 2 in} the register 105, and the processing time can be reduced to １ ／ compared with the conventional case.

That is, with regard to the function operation, redundant processing can be reduced and processing time can be reduced.

Still referring to FIG. 1, a data bus 101 is used for data transfer between registers. Reference numeral 102 denotes a fixed-point data logical operation circuit (AL
U), the contents of the 107 register described later are
In the binary operation, an operation specified by a program is performed using the contents of registers 106 and 107 described later as input. 103 is A
A flag for holding the state of the operation result in the LU 102
It is a register. Numerals 104 and 105 are operation result output registers for holding the operation results in the ALU 102.
Reference numeral 106 denotes an input register for holding input data to the ALU 102, the input of which is data output to the data bus 101. Reference numeral 107 denotes an input register for holding input data to the ALU 102, and the input is data held in the operation result output register 104 or 105. Reference numeral 108 denotes a barrel shifter, which is an input register 1
A left / right shift process is performed on the data 06 or 107 by the shift amount specified in 109 described later. Reference numeral 109 denotes a shift amount setting register for specifying a shift amount in the barrel shifter 108, which is connected to the data bus 101. Reference numeral 110 denotes a multiplexer for selecting which of the input registers 106 and 107 is to be input to the barrel shifter 108. 111 is an input register 10
7 is a shift amount detecting circuit for normalizing the data held in 7, and the barrel shifter 108 shifts the data by the shift amount detected by this circuit to execute the normalization processing. A memory 112 for storing various data is connected to the data bus 101. An address pointer 114 designates an address of the data memory 112. Reference numeral 113 denotes a dedicated bus 113 for using a value detected by the normalization shift amount detection circuit 111 as a value for specifying an address of the data memory 112. 115 is 1
13 and the original address pointer 11
4 is an addition circuit for adding the value of 4;
This is a multiplexer for selecting which of the outputs 113, 114 and 115 specifies the 12 addresses.

FIG. 4 is a diagram showing the data format of the fixed-point arithmetic processor and the range of numerical values.
(A) is a data format of a fixed-point arithmetic processor. (B) shows the range of numerical values.

[0061]

As described above, the address pointer of the fixed-point arithmetic processor according to the present invention has an adder for adding the output value of the normalizing shift amount detecting circuit and the value of the address pointer of the data memory. Accordingly, there is an effect that redundant processing can be reduced and the processing time can be reduced as compared with the related art regarding the function operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a memory map diagram.

FIG. 3 is a diagram of a conventional example.

FIG. 4 is a data format diagram.

FIG. 5 is a flowchart of a conventional example.

FIG. 6 is a flowchart of the embodiment of the present invention.

Claims (1)

(57) [Claims] An internal data bus, a logical operation unit (ALU) for fixed-point data, an input register to the ALU, a register for outputting an operation result in the ALU, and an ALU.
Shifter for the data held in the input register to the ALU, a shift amount setting register for specifying the shift amount in the barrel shifter, and a shift amount for normalization for the data held in the input register to the ALU A fixed-point arithmetic processor having a circuit, a data memory, and an address pointer of the data memory, comprising a circuit for adding the output value of the normalization shift amount detection circuit and the value of the address pointer of the data memory. An address pointer characterized in that: