JP2923950B2 - Print control device for thermal printer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal printer, and more particularly, to a control circuit for controlling heat generation of a heat generating element.

[Conventional technology]

Conventionally, in a thermal printer, various methods have been used in order to prevent deterioration of print quality due to heat accumulation during continuous use time of a thermal head. Among them, a method of storing the previous data for each dot and determining the energization time, such as Japanese Patent Publication No. 55-48631, and a method of changing the energization time depending on the drive cycle, such as Japanese Patent Publication No. 57-18507, are used. Have been. These are generally called a history control method.

[Problems to be solved by the invention]

In these conventional examples, generally, a method of sequentially transmitting data to a drive IC of a thermal head while performing data processing by a CPU was generally used. In such a method, even when an attempt was made to operate a thermal printer at high speed, processing was not performed. Unable to keep up, it was an obstacle to speeding up the thermal printer.

An object of the present invention is to eliminate such a conventional problem,
It is an object of the present invention to provide a printing control device for a serial type thermal printer which is high speed and has excellent printing quality.

[Means for solving the problem]

In order to achieve the above object, a print control device of a thermal printer according to the present invention includes a processing device that outputs thermal drive data at predetermined timings, and a head control circuit disposed between the processing device and the thermal head. Wherein the head control circuit is composed of at least two or more unit circuits, and the unit circuits are configured to store past and present thermal head drive data and to input drive data. A data input terminal, an address input terminal connected to an address bus of the processing device, a data latch timing input terminal for obtaining a synchronization signal at the time of inputting drive data, and a main and sub terminals for enabling access to a head control circuit. Two chip select terminals using either the main or sub chip select terminal. Characterized in that simultaneously accessible to configure a unit circuit of the above.

Also, the head control circuit has at least two
It consists of more than one unit circuit, and the unit circuit is
A storage circuit holding at least one past drive data of the thermal head and current drive data, a data input terminal connected to a data bus of the processing device, and at least 3 bits of an address bus of the processing device. Address input terminal, a data latch timing input terminal connected to the data strobe terminal of the processing device, a plurality of main and sub chip select input terminals corresponding to predetermined address information of the address bus, and a power supply time of the heating element. An energizing pulse determining circuit for determining, a gate circuit for mixing an input signal of the storage circuit and an input signal from the energizing pulse determining circuit, and a head drive output terminal connected to the gate circuit and outputting a drive signal to the heating element. A control signal for controlling a plurality of unit circuits in common has a plurality of units simultaneously by the same address signal. Characterized by being configured to be set in the circuit.

〔Example〕

FIG. 1 is a schematic diagram showing the configuration of an embodiment of a terminal printer using a print control device of a thermal printer according to the present invention.

1 is a thermal head having a plurality of heating elements 1a, 2 is a head drive circuit for driving the thermal head, and 3a and 3b are heat generation amounts of the thermal head inserted between the CPU 4 of a processing device and the thermal head. A head control circuit (hereinafter abbreviated as HCU) for controlling each dot, 15 converts the potential at a voltage dividing point of a series circuit of a thermistor 14 and a resistor 14a for detecting the ambient temperature or substrate temperature of the thermal head 1 into a digital quantity. A / D converter, 12 is ROM, 13
Denotes a RAM, 17 denotes a data bus, 18 denotes an address bus, 19 denotes an interface for inputting sealing data, and 20 denotes a power input terminal.

The CPU 4 is, for example, an 8-bit CPU, and has a ▲ ▼ terminal of a data strobe terminal, an I / O port (not shown), a timer (not shown), and the like.

The HCUs 3a and 3b function as a kind of peripheral of the CPU as a unit circuit, and are assigned to specific addresses on a memory map, like the ROM 12 and the RAM 13. The address decoder 16 is connected to the (1) terminal 7 and the (2) terminal 8 which are chip select terminals for accessing this unit circuit. 9 uses the WR of the CPU as the synchronization signal for data input.
The data latch timing input terminal received from the terminal is shown. Reference numeral 5 denotes a data input terminal connected to the data bus 17, and reference numeral 6 denotes an address input terminal for inputting lower three bits or more of the address bus.

FIG. 2 is a head control circuit of a print control device according to the present invention.
FIG. 3 is a detailed circuit diagram of HCU3a and HCU3b.

Data input terminal 5 is 8-bit data D ₀ to D ₇ can be input in parallel.

The signals from the chip select terminals 1 and 2 are mixed with the output from the address decoder 30 by the gate circuit, and processing according to each address information such as data input is executed inside the HCU.

21 to 29 shows a data latch circuit to hold 8-bit data, respectively, 21 to 23 of the head drive signals H ₀ to H ₇
Data holds, 24-26 data H ₈ to H _15, from 27 to 2
9 is latching data of H ₁₆ to H _23, respectively.

The head drive output has, for example, 24 output terminals H _{0 to} H ₂₃ for driving a 24-dot thermal head.

Reference numeral 31 denotes a latch circuit group for holding one dot row of the current head data, 32 denotes one dot row of the previous data of one time before, and 33 denotes one dot row of the past data of two times before. Are shown in FIG.

Reference numeral 34 denotes an energization section signal generation circuit which is a kind of energization pulse determination circuit.

Reference numeral 30 denotes an address decoder, which can select storage of head drive data, reset of data of a data latch circuit, access of the conduction section signal generation circuit 34, and the like.

The terminal 7 of the chip select terminal 7 and the outputs 6a, 6b, 6c of the address decoder are mixed by AND gate, and the head drive data is data latch circuits 21, 24,
Stored separately in 27. {Circle around (2)} The AND output between the terminal 8 and the output 6d of the address decoder enables all the data of the data latch circuits 21 to 29 to be reset simultaneously. Similarly, the AND output of the terminal 2 and the outputs 6e and 6f of the address decoder can access the conduction section signal generation circuit 34.

At the same time as the head drive data is output from the CPU 4 to the data bus, the ▲ ▼ signal is output.
One terminal is accessed, and data is transferred to each of the data latch circuits 21, 24, 27 according to the lower three bits of information on the address bus. Then, the already stored data is shifted rightward in FIG. 2, for example, the data of the data latch circuit 21 is shifted to the data latch circuit 22 and sequentially stored as past data.

The lower two bits of information can access up to four data latch circuits, but the number of address input terminals and the number of data latch circuits may be increased according to the number of heating elements.

After the data is set, the terminal is accessed, and a predetermined pulse is input to the energization signal input terminals 34a and 34b based on predetermined lower three bits of address information, thereby energizing the heating element.

The energizing pulse determination circuit 34 is an energizing section signal generating circuit for demodulating the energizing signal modulated into a periodic signal from the CPU 4 as an energizing section signal, and includes a binary counter 35 and an inverter 34.
a, and an AND circuit 35b. 34a functions as a clock input terminal of the binary counter 35, and 34b functions as a reset input terminal. The clock input is a signal that is transferred with a variable cycle, and the energization section signal generation circuit 34 selectively extracts the cycle to generate a section signal.

FIG. 5 is an explanatory diagram showing the relationship between the above address information and functions.

According to the information of the lower three bits A2, A1, and A0 of the address bus, when these are (000), all of the data latch circuits 21 to 29 are reset, and when (001), (010), and (011), the respective data latches are reset. Address information for inputting drive data for the thermal head to the circuit.

At (100), a reset signal to the energization section signal generation circuit is input, and at (101), a clock signal of the energization section signal generation circuit is input. When outputting the address information of (100) and (101), the data on the data bus has no relation.

Data reset of the latch circuit and access to the energization section signal generation circuit are possible only when the terminal (2) is accessed, and data input is possible only when the terminal (1) is accessed.

With this configuration, when two or more unit circuits are provided side by side as shown in FIG. 1, when all data in the latch circuit is reset, and when the energized section signal generation circuit is accessed, etc. By installing an address decoder for giving a common control code and connecting it to the terminal ▲ ▼ 2, it is possible to control all the unit circuits provided together.

In the present embodiment, the energization pulse determination circuit is shown using the previous section signal generation circuit. However, it is also possible to install an energization section signal generation circuit outside the unit circuit. A plurality of energization section signal input terminals may be used.

FIG. 3 shows the input / output waveforms of the pass-through pulse determination circuit. 41 shows a reset input waveform, and 42 shows a clock input waveform. The cycle of the clock input signal changes sequentially. After the binary counter 35 receives a reset input,
When this clock is received, it is converted into a 4-bit code.
This is converted into output waveforms of 43 to 46 by the inverter 35a and the AND circuit 35b. 43 is the output waveform of the 36a terminal, 44 is 3
The 6b terminal, 45 indicates the output waveform of the 36c terminal, and 46 indicates the output waveform of the 36d terminal, and the pulse widths thereof are t ₃ , t ₂ , t ₁ , t _{0, respectively.}
It is. These pulse widths are the energizing time of the heating element, and are given to the heating element as an energizing section corresponding to the past drive history.

The gater circuit 37 (GO) shown in FIG.
34, and outputs a head drive signal to the heating element by mixing the output signal of 34 with the drive data of the storage circuit. The first gate circuit 38 corresponding to the past drive data and the first gate circuit 38 corresponding to the current drive data are output. A second gate circuit 40 and a third gate circuit 39 for applying a preheating pulse according to the past driving history. The energizing sections t ₃ , t ₂ , and t ₁ are sub-energizing sections corresponding to past drive data and are input to the first gate circuit,
Energization interval t ₀ is input to the second gate circuit is a main current interval corresponding to the current drive data. Of the sub-current section
t ₂ is also input to the third gate circuit for the preheating pulse.

〔motion〕

The temperature of the thermal head is read by a digital quantity by the A / D converter 15 in FIG. Next, the respective pulse widths of the main energizing section and the sub energizing section to the heat generating element are subjected to arithmetic processing by the CPU 4, and the predetermined address information is transferred from the address terminals to the HCUs 3a, 3 using an internal timer or the like.
Write to b and output as periodic signal. The CPU 4 also serves as the energization signal output means.

FIG. 4 is an explanatory view showing a method of energizing the thermal head of the printing control device according to the present invention.
The data in 31, 32, and 33 are shown, respectively, 1 indicates ON data, 0 indicates OFF data, 51 indicates the current data, 52 indicates the previous data, and 53 indicates the data of the previous data. ing. 54-58 is shows the output waveforms of the head driving signal, the H ₀ terminal 54, 55 of the H ₂ terminal, 56 a H ₅ terminal, 57 is the H ₇ terminals, 58
Respectively show the output waveform of the H ₁₀ terminals.

In FIG. 4, reference numeral 53 denotes data at the start of printing. Dot energization on the current first time between all energization of all the current section is energized is applied, the dot energizing off t ₁ interval is given as a preheating Palace. This preheating pulse only raises the substrate temperature of the thermal head and does not form dots.

Drive data of the own heating element previous timing When it is turned on t ₃ period indicated by hatched portion is reduced (shown in the output waveform 54), when there is drive data in two previous timing t ₂ section is reduced (shown in the output waveform 57), when it is continuous (as shown in the output waveform 54) t ₃ + t ₂ interval is reduced. T ₁ interval is reduced when both dots adjacent in the previous driving result is energized on (shown by the output waveform 56). And when its current data is on the data to be compared in an attempt to all reduction be on data, only t ₀ interval is energized on. Conversely, when the data to be reduced is the off data and the current data is off, a preheating pulse is given. The gate circuit 37 performs such comparison of the drive data and selection of the energized section.

By forming the head control circuit as a gate array and forming one chip, a thermal printer having a very simple configuration can be realized. This is a very important factor when incorporating not only a terminal printer using a thermal printer but also a miniaturized device such as a portable word processor.

In the present embodiment, as an example, an example in which the past data is stored up to twice before is shown. However, the number of sub energization sections can be increased by four or five times as three times or four times. By doing so, more detailed history control can be realized.

In addition, the CPU 4 outputs the energization signal according to the type of the ink ribbon and the type of paper, and changes the width of the energization interval and the energization interval for convenience. Are stored in the ROM 12, and are converted into readout cycle signals corresponding to the print mode and output.

〔The invention's effect〕

According to the present invention, data processing based on past driving history is performed.
Since there is no need to perform the processing in the CPU, high-speed processing of the CPU becomes possible, and the printing speed of the thermal printer can be increased.

In addition, by unitizing the head control circuit with a gate array, etc., it is allocated on the memory map of the CPU, it is directly connected to the data bus and address bus, and it is only necessary to write data directly from the CPU. Complex processing was enabled.

Further, when the unitized head control circuit is increased according to the number of heat generating elements of the thermal head,
The contents that can be controlled in common by installing a plurality of chip select terminals can be controlled simultaneously, which is extremely advantageous for increasing the processing speed, reducing the load on the CPU, and increasing the speed of the thermal printer.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a configuration of an embodiment of a terminal printer using a print control device of a thermal printer according to the present invention. FIG. 2 is a detailed circuit diagram of a head control circuit HCU3 of the print control device of the present invention. FIG. 3 is an explanatory diagram showing input / output waveforms of an energizing pulse determination circuit of the print control device of the present invention. FIG. 4 is an explanatory diagram showing a method for energizing the thermal head of the print control device of the present invention. FIG. 5 is an explanatory diagram showing a relationship between address information and functions of a head control circuit of the print control device of the present invention. 1 thermal head 2 head drive circuit 31, 32, 33 storage circuit 4 energizing signal output means, CPU 34 energizing section signal generating circuit 37 gate circuit 7, 8 chip select terminal

Claims (2)

(57) [Claims] 1. A processing device having a thermal head having a plurality of heat generating elements and outputting drive data of the thermal head at predetermined timings, and a head disposed between the processing device and the thermal head. A print control device for a thermal printer having a control circuit, wherein the head control circuit is composed of at least two or more unit circuits, and the unit circuits store past and present drive data of the thermal head. A data input terminal for inputting drive data; an address input terminal connected to an address bus of the processing device; a data latch timing input terminal for obtaining a synchronization signal when the drive data is input; And a main and sub chip select terminal for enabling access to the main and sub chips. Printing control device of the thermal printer being characterized in that simultaneously accessible configured the two or more unit circuits via the use of an Puserekuto terminal. 2. The head control circuit is composed of at least two or more unit circuits formed into chips, and the unit circuit stores at least one past drive data of the thermal head and current drive data. A storage circuit, a data input terminal connected to a data bus of the processing device, an address input terminal connected to at least 3 bits of an address bus of the processing device, and a data strobe terminal of the processing device. A data latch timing input terminal, a plurality of main and sub chip select input terminals corresponding to predetermined address information of the address bus, an energizing pulse determining circuit for determining an energizing time of the heating element, and an input of the storage circuit. A gate circuit for mixing the signal and the input signal from the energizing pulse determination circuit; A head drive output terminal for outputting a drive signal to the heat generating element, wherein a control signal for commonly controlling the plurality of unit circuits is set to a plurality of unit circuits simultaneously by the same address signal. The print control device for a thermal printer according to claim 1.