JP2923506B1 - Single electronic device integrated circuit device - Google Patents

Abstract

A single electronic device can be used as a component of a logic circuit. The logic tree includes a plurality of single electronic elements and performs a predetermined logic operation and performs a predetermined logic operation. A potential difference between a high power supply potential and a low power supply potential supplied to the logic tree is determined by the logic tree. It is characterized in that it is configured to be smaller than the difference between the maximum value and the minimum value of the voltage input to the single electronic element as an input.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-electron element integrated circuit device utilizing a one-electron charging effect.

[0002]

2. Description of the Related Art In the semiconductor industry at present, high speed and high performance are achieved by miniaturizing a MOSFET which is a basic element. However, the miniaturization of MOSFETs has already been extremely advanced, and it is becoming difficult to promote high performance even if miniaturization is advanced as it is.

[0003] On the other hand, with the progress of such fine processing technology, physical effects that have not been seen or are not important conventionally become apparent. Attempts to produce new devices different from conventional electronic devices by actively utilizing such effects have been widely made. In recent years, elements called so-called single-electron elements utilizing the charging effect of electrons have attracted particular attention because their operating principles can be applied to the atomic level.

A single electronic device has at least one island serving as a localized region of electrons (hereinafter referred to as a conductive island), at least one tunnel junction connected to the conductive island, and capacitively coupled to the conductive island. An electronic device that has at least one external electrode, such as an electron trap that stores electrons while controlling them one by one, a switching element that can control the on / off of current flow by charging one electron, and one electron. It is possible to make a so-called turn-style element or a pump element that transmits while controlling one piece. These elements are described in, for example, “Single Charge T
unneling ", Plenum Press, 19
92, ISBN 0-306-44229-9.

[0005] Among such single-electron elements, a single-electron transistor (IEEE Transactions on), which is the most basic element as a switching element, is used.
Magnetics, Vol. MAG-23, No.
2, 1987, p1142) as a representative example.

FIG. 15 shows the basic structure of a single electron transistor.
Shown in As shown in FIG.
One conductive island 1, electrodes 2 and 3, this conductive island 2 and electrode 2,
3. An element having two tunnel junctions 5, 6 sandwiched by 3 and one external electrode 4 capacitively coupled to the conductive island 1, and a current flowing between the electrodes 2, 3 due to the potential of the external electrode 4. Is a device that can control According to a custom, the external electrode 4 is formed of the gate electrode and the electrodes 2 and 3,
The electrode 3 with the lower bias potential is called the source electrode, and the electrode 2 with the higher bias potential is called the drain electrode. FIG. 16 shows an equivalent circuit of this single electron transistor. As shown in the equivalent circuit of FIG. 16, capacitors between each of the electrodes 2, 3, 4 and the conductive island 1 are called a drain capacitor 7, a source capacitor 8, and a gate capacitor 9.

The characteristics of a single-electron transistor are described, for example, in the above-mentioned document “Single Charge Tunnel”.
ing ", Plenum Press, 1992 IS
Since it is described in detail in BN0-306-44229-9, etc., only the essential part will be briefly described here. First, the source of the single electron transistor
17, 18 and 19 show the results of computer simulation of the dependence of the drain-to-drain current I _{DS on} the source-to-gate voltage V _GS (for the method of simulation, see, eg, Kuwamura et al., IEICE C-II V
ol. J77-C-II No. 5pp. 221-228
See). These properties, single-electron electrostatic capacitance of the gate capacitor is a characteristic parameter of the transistor C _g, in the case of the total capacity C _sigma (now viewed from the conduction island,
The following description is based on the capacitance of the source capacitor, the sum of the capacitance of the drain capacitor and the capacitance of the gate capacitor), and the operating temperature T.

FIG. 17 shows the gate voltage dependence of the source-drain current I _DS when the drain voltage V _DS of the single-electron transistor is sufficiently smaller than the so-called blockade voltage V _B (V _DS = 5 mV). FIG. The operating temperature T is 77K. Figure 18 is a graph showing the gate voltage dependence of the source-drain current I _DS when changing the drain voltage V _DS of the single-electron transistor as a parameter, the drain voltage V _DS
Is 54 mV (V _DS ０．１0.1 V _B ) and 270 mV (V _DS ０．１
0.5V _B), shown in the graph k _1, k _2, k ₃ a characteristic graph when a 540mV (V _DS ~V _B). In this case, the operating temperature T is 77K. FIG. 19 is a graph showing the gate voltage dependence of the source-drain current I _DS when the operating temperature T of the single-electron transistor is changed as a parameter.
The characteristic graph in the case of 2K and 244K is represented by a graph k ₄ ,
shown in k _5, k _6.

As shown in FIG. 17, the source-drain current I _DS of the single-electron transistor periodically repeats an ON state (state where I _DS is high) and an OFF state (state where I _DS is low) in accordance with the gate voltage. . This is generally called Coulomb oscillation. To completely switch the oscillation between the ON state and the OFF state, the amplitude of the input voltage (gate voltage) is e.
Only / (2C _g ) is required. On the other hand, as shown in FIGS. 18 and 19, when the drain voltage V _DS increases or the operating temperature T increases, the minimum current of the Coulomb oscillation increases exponentially, and finally the switching operation is not performed.
Become its index, with respect to the drain voltage V _DS is a blockade voltage V _B = e / C _Σ, for the temperature at which charging energy ^{_{E c = e 2 / (2C}} Σ). That is, when the Boltzmann constant and k _B, the following conditions _{V DS <e / C Σ k} B T <e 2 / (2C Σ) is requested, the basic performance and is ON / OFF ratio as a switching element ( the ratio between the maximum and minimum values of I _DS)
Changes the source-drain voltage V _DS to the blockade voltage V
_B, which is sufficiently smaller than the operating temperature T and the charging energy E
It is improved by making _c sufficiently smaller than a value obtained by dividing _c by Boltzmann's constant k _B. From the viewpoint of the total capacitance C _が of the single-electron transistor, when the total capacitance C _{大 き く} increases, the ON / OFF ratio deteriorates under the same operating temperature T and the source-drain voltage V _DS. Become.

In a conventional logic circuit using a CMOS or the like, the amplitude of the input voltage (difference between the maximum voltage and the minimum voltage of the input voltage) and the amplitude of the output voltage are equal for each element element. Requested. This is natural considering that an integrated circuit is composed of a large number of element circuits, and the output of each element circuit becomes the input of another element circuit. Therefore, in order to replace the field-effect transistor of the conventional logic circuit with a single-electron transistor, it is necessary that the amplitude of the input voltage and the amplitude of the output voltage of the single-electron transistor be substantially the same.

As described above, the amplitude of the input voltage (gate voltage) needs to be e / (2 C _g ) to completely switch the ON state and the OFF state of the single electron transistor. In order to obtain an output voltage equivalent to this input voltage, that is, e / (2C _g ), the power supply voltage to the single-electron transistor is required to be equal to or more than e / (2C _g ). A voltage of e / (2C _g ) or more is applied between the source and the drain of the transistor depending on the operation state. Here, since there is a relationship of C _g <C _Σ , this means that the power supply voltage becomes larger than e / (2C _すな_{わ ち} ) (that is, V _DS > 0.5 V _B ), and the minimum value of the Coulomb oscillation current , And consequently the ON / OFF ratio is remarkably deteriorated. According to computer simulation, the operating temperature is k _B T = 0.01e ² /
At ( _2CΣ ), the ON / OFF ratio deteriorates by about 2 × 10 ⁻¹⁷ when V _D = 0.5 V _B as compared with the case where V _D = 0.1 V _B.

Also, as shown in FIG.
_{As DS} is increased, the gate voltage dependence is in the same direction and in the same direction as the polarity of the drain voltage.
5V _DS ). This makes the source-drain current I _DS larger when the gate voltage V _GS is zero volts. This makes it almost impossible to use single-electron transistors simply as replacements for field-effect transistors.

Therefore, as shown in FIG. 20, by connecting another control electrode 4a to the conduction island 1 of the single electron transistor shown in FIG. 16 via the capacitor 9a, the gate voltage dependency due to the drain voltage is reduced. The idea of canceling the shift and thus using a single electron transistor as a replacement for a field effect transistor has been proposed by Tucker (Journal).
of Applied Physics, vol. 7
2, 1992, p4399). However, by increasing the control gate, the total capacitance C _sigma rises, blockade voltage V _B becomes smaller, resulting in further deterioration of the ON / OFF ratio. According to Tucker's proposal, the source-drain voltage V _DS is 0.75 V _B , and the ON / OFF ratio is significantly deteriorated. This ON / OF
It is considered that due to the deterioration of the F ratio, the amplitude of the output potential gradually decreases, and eventually, it becomes impossible to drive the next-stage logic gate.

[0014]

SUMMARY OF THE INVENTION As has been seen above,
If the amplitude of the input voltage is made equal to the amplitude of the output voltage in order to apply a single-electron transistor to a conventional logic circuit, the ON / OFF ratio is significantly deteriorated. Further, since the gate voltage dependence characteristic is shifted by the application of the drain voltage, there is a problem that it is almost impossible to use a single electron transistor as a complete replacement of a field effect transistor. To eliminate this problem, a single electron transistor with a second
Has been proposed, but according to this method, the total capacity increases and the ON / OFF ratio further deteriorates.

Another problem is that the single-electron transistor is turned on only in a limited region of the gate voltage V _GS as shown in FIG. 17, so that the potential of the drain is transmitted to the source. There was a problem that was difficult. In other words, transmitting the potential of the drain to the source causes an increase in the source potential and, consequently, a decrease in the potential between the gate and the source. Therefore, when a single-electron transistor is used as a transmission gate, there is a problem that it is more difficult to transmit a drain potential to a source than to transmit a source potential to a drain. For this reason, Complementary Pass Transistor Logic (IEEE)
Journal of Solid-State C
ircuits, vol. 25, no. 2, 1990,
(see p. 308) is difficult to apply to CMOS transmission transistor logic, and it is also difficult to construct large-scale integrated circuits similar to CMOS using only single-electron transistors.

The present invention has been made in view of the above circumstances, and has as its object to provide an integrated circuit device of a single electronic device that can use a single electronic device as a component of a logic circuit. .

[0017]

SUMMARY OF THE INVENTION A single-electronic-element integrated circuit device according to the present invention comprises a logic tree, comprising a plurality of single-electronic elements, performing a predetermined logical operation. The potential difference between the power supply potential and the low power supply potential is configured to be smaller than the difference between the maximum value and the minimum value of the voltage input to the single electronic element as the input of the logic tree. I do.

Further, it is preferable that an amplifier for receiving the output of the logic tree be provided.

The potential difference between the high power supply potential and the low power supply potential supplied to the logic tree may be smaller than the potential difference between the high power supply potential and the low power supply potential supplied to the amplifier. preferable.

Further, it is preferable that the potential of the high power supply and the potential of the low power supply supplied to the amplifier are equal to the maximum value and the minimum value of the voltage input to the single electronic device.

Further, a charge / discharge circuit comprising a single electronic element and charging / discharging the logic tree based on a control clock may be provided.

[0022]

FIG. 1 shows the structure of a first embodiment of an integrated circuit device having a single electronic device according to the present invention. The integrated circuit device of this embodiment includes two cascade-connected single electron transistors 10 and 20 and a load capacitor 33.
And In the single electron transistor 10, the drain electrode 12 is the source electrode 23 of the single electron transistor 20.
, The source electrode 13 is grounded, and the gate electrode 1
4 is configured to receive a first input signal. In the single electron transistor 20, the drain electrode 22 is connected to one end of the load capacitor 33, and the gate electrode 24
To the second input signal. The other end of the load capacitor 33 is configured to be grounded. A floating capacitor 31 is formed at a common connection point between the single electron transistor 10 and the single electron transistor 20. In FIG. 1, reference numerals 11 and 21 indicate conductive islands of the single electron transistors 10 and 20, respectively.

As can be seen from the configuration shown in FIG. 1, the integrated circuit device according to the present embodiment has a two-input circuit that discharges the charge of the load capacitor 33 by a logic tree including two single electron transistors 10 and 20. It is a NAND circuit. This discharge is performed based on the first and second input signals input to the gate electrodes 14 and 24 of the single electron transistors 10 and 20, respectively. The output signal of the integrated circuit device of the above embodiment is
3 between the drain electrode 22 and the load capacitor 33
5 is output.

In the integrated circuit device of this embodiment,
Logic input signal "0" is zero volts, the logic of the input signal "1" is represented by e / (2C _g) volts, the logic of the output signal "0" at 0 volts, the logic of the output signal "1" Is represented by the ratio of the initial accumulated charge of the load capacitance 33 to the total capacitance of the output node 35.

Here, e indicates the elementary charge amount, and C _g indicates the capacitance of each gate capacitor of the single electron transistors 10 and 20.

In this embodiment, in order to operate the single electron transistors 10 and 20 as components of a logic circuit (NAND circuit), the amplitude of an output signal (that is, two cascade-connected single electron transistors) is used. 10,2
The configuration is such that the power supply voltage of a logical tree consisting of 0) is smaller than the amplitude of the input signal. This will be described with reference to simulation results shown in FIGS.

FIG. 2 shows an output node when the same input signal (graph g _{1 in} FIG. 2) is input to the gate electrodes 14 and 24 of the single electron transistors 10 and 20 of the integrated circuit device according to the present embodiment. The output signal (graph g _{2 in} FIG. ₂ ) output from 35 is obtained by simulation. In this simulation, the tunnel junctions 15, 16, 25, 2 of the single electron transistors 10, 20
6, the resistance of each of the source capacitors 18 and 500 kΩ.
28 each have a capacitance of 0.1 aF and a drain capacitor 1
The calculations were performed on the assumption that the capacitance of each of the gate capacitors 7 and 27 was 0.1 aF and the capacitance of each of the gate capacitors 19 and 29 was 0.1 aF. The capacity of the load capacitor 33 is 1 fF, the capacity of the floating capacitor 31 is 5 aF, the operating temperature T is 77 k, and the initial charge amount stored in the load capacitor 33 is 500 e.
And

Note that these values are one of typical values, and it goes without saying that the operation of the present embodiment is not limited to these parameters. With the above parameters, the input signal voltage is 0V at logic "0", a logic "1" at e / (2C _g) ~0.8V and the output signal voltage is 0V at logic "0", a logic "1" About 500e
/ (C _F ) to 0.08V. That is, the amplitude of the output signal voltage (or the power supply voltage) is set to 1/10 of the amplitude of the input signal voltage. At this time, as shown in FIG. 2, while the inputs of all the single electron transistors 10 and 20 are logic "0", the output keeps the logic "1" and the input becomes the logic "1". after the output has been discharged to a logic "0" (see graph g _1, g ₂ in FIG. 2) on the other hand, except that the 5000e initial amount of charge accumulated in the load capacitor 33, identical to the above-described simulation FIG. 3 shows a simulation result in the case where the above parameters are used, that is, when the input amplitude and the output amplitude are both set to 0.8V. G ₁ represents an input waveform in FIG. 3, g ₃ shows the output waveform.

As can be seen from FIG. 3, while the inputs of all the single electron transistors 10, 20 are at logic "0", the outputs gradually decrease and do not maintain the state of logic "1". That is, the integrated circuit device shown in FIG. 1 does not operate as a logic circuit. This is because the OFF leak current of the single electron transistors 10 and 20 increases due to the increase in the drain voltage.

When the source-drain capacitance is reduced, the total capacitance _CΣ is reduced, so that the OFF leak current is reduced and the characteristics can be slightly improved, but this makes the fabrication of a single-electron transistor more difficult. In addition, there is a possibility that the driving force of the single-electron transistor is impaired.

As described above, the voltage of the driving power supply (the potential difference between the high power supply potential and the low power supply potential supplied to the logic tree) of the logic tree composed of single electron transistors is determined by the maximum value and the minimum value of the input signal voltage. If the difference is greater than or equal to, the logical tree will not perform a normal logical operation.

The control electrode 1 is connected to the conductive islands 11 and 21 of the single electron transistors 10 and 20 of the integrated circuit device shown in FIG. 1 via the capacitors 19a and 29a.
The same applies to the integrated circuit device having the configuration shown in FIG. 4 provided with 4a and 24a. In the integrated circuit device shown in FIG. 4, the output signal voltage output from output node 35 is set to the same value (0.8 V) as the input signal voltage input to control electrodes 14 and 24 of single electron transistors 10 and 20. FIG. 5 shows a simulation result in the case of performing the above. In this simulation, the capacitances 19a and 29a of the control electrodes 14a and 24a were each set to 0.1 aF, and the other parameters were the same as those in the simulation of FIG.

The graph g ₁ in FIG. 5 is a waveform of an input signal input to the gate electrodes 14 and 24 of the single-electron transistor 10 and 20, the graph g ₂ is the waveform of the output signal outputted from the output node 35 is there. As can be seen from FIG. 5, while the inputs of the single electron transistors 10 and 20 are at logic "0", the output voltage drops and the state of logic "1" cannot be maintained. This is because the OFF leak current of the single electron transistors 10 and 20 increased due to the increase in the drain voltage, and the gate electrodes 14a and 24
This is because the addition of a increased the total capacitance C _Σ .

In the integrated circuit device having a single electronic element according to the first embodiment shown in FIG. 1, the logic tree (logic circuit) composed of single electron transistors is a NAND circuit. However, even in a NOR circuit in which the single-electron transistors 10 and 20 are connected in parallel as shown in FIG. 6, the amplitude of the output signal voltage output from the output node 35 is limited by the gate electrodes of the single-electron transistors 10 and 20. 14,24
It is needless to say that the single-electron transistor integrated circuit device shown in FIG. 6 also has the same effect as that of the first embodiment if it is configured to be smaller than the amplitude of the input signal voltage inputted to the first embodiment. No.

Next, the configuration of a second embodiment of the integrated circuit device having a single electronic device according to the present invention is shown in FIG. This second
The integrated circuit device according to the second embodiment has a configuration in which a CMOS inverter 40 is connected as an amplifier to the output node 35 according to the first embodiment shown in FIG. The CMOS inverter 40 includes a P-type MOS field effect transistor 41 and an n-type MOS field effect transistor 42. The source of the transistor 41 is connected to the drive power supply 45, and the source of the transistor 42 is grounded. The input terminal of the CMOS inverter 40 is connected to the output node 35 of the logic tree composed of the single electron transistors 10 and 20, and the output terminal 43 of the CMOS inverter 40 is grounded via the capacitor 47. In the integrated circuit device of this embodiment, the final output is CMOS.
Since the signal is output via the inverter, an AND operation is performed.

In the second embodiment, as in the first embodiment, the amplitude of the output signal voltage output from the output node 35 of the logic tree is the same as that of the single electron transistors 10 and 10 constituting the logic tree. 20 gate electrodes 14, 2
4 is configured to be smaller than the amplitude of the input signal voltage. For example, the initial charge amount of the load capacitor 33 is set to 500e, and the amplitude of the output signal voltage is configured to be 1/10 of the input signal voltage.

FIG. 8 shows a simulation result of the operation of the integrated circuit device according to the second embodiment. The parameters of each element used in this simulation are as follows. The resistance of each of the tunnel junctions 15, 16, 25, 26 of the single electron transistors 10, 20 is 500 kΩ, the capacitance of the source capacitors 18, 28 is 0.1 aF, the capacitance of the drain capacitors 17, 27 is 0.1 aF, and the gate capacitor The capacitance of the load capacitor 33 at the output node 35 of the logic tree is 1 fF,
The capacity of the load capacitor 47 of the output node (output node of the logical output) 43 of the MOS inverter 40 was set to 10 fF. The capacitance of the floating capacitor 31 at the contact connecting the single-electron transistors 10 and 20 is 5 aF, the operating temperature T is 300 k, and the voltage of the output capacitor 43 at the output node 43 is about 80 mV. It is assumed that such initial charges are stored.

The graph g ₁ shown in FIG. 8 is a waveform diagram of an input signal input to the gate electrodes 14 and 24 of the single-electron transistor 10 and 20, the graph g ₂ is output from the output node 35 of the logic tree it is a waveform diagram of the output signal, the graph g ₅ is a waveform diagram of an output signal output from the output node 43 of the CMOS inverter 40. As can be seen from FIG. 18, in the present embodiment, the amplitude of the input signal (graph g ₁ ) and the amplitude of the output signal (graph g ₅ ) are the same as 0.8V.

As described above, in the integrated circuit device of the present embodiment, the amplitude of the input signal and the amplitude of the output signal are the same, so that when a logic circuit such as a similar logic tree is connected to the next stage, The logic circuit can be completely driven. Thus, the device of this embodiment can be used as a logic circuit in an integrated circuit. Further, in the present embodiment, since the output is made from CMOS inverter 40,
The high output impedance, which is a drawback of the single-electron transistor, is converted into the low output impedance of the CMOS, and it is possible to drive a heavy load (large capacitive load) at a higher speed.

In the second embodiment, the amplifier is C
Although the MOS inverter 40 is used, instead of the CMOS inverter, it is possible to use a circuit for performing another amplifying operation such as an operational amplifier or a latch. Also, MOS
Of course, an amplifier circuit using a junction field effect transistor, a bipolar transistor, or the like instead of the field effect transistor can be used instead of the CMOS inverter 40. Further, a circuit such as a so-called operational amplifier in which a junction field-effect transistor and a bipolar transistor are mixed can be used for the amplifier circuit.

FIG. 9 shows the configuration of a third embodiment of the integrated circuit device having a single electronic device according to the present invention. This third
The integrated circuit device according to the second embodiment has a configuration in which a single electron transistor 50 for charging and a single electron transistor 60 for discharging are provided in the integrated circuit device according to the second embodiment shown in FIG. ing.

The single electron transistor 50 for charging is provided between the power supply 37 and the node 35, and an inverted signal of a control clock input from the outside is input to the gate electrode 54 of the single electron transistor 50. You. The single electron transistor 60 for discharging is the single electron transistor 10.
The control clock is input to the gate electrode 64 of the single-electron transistor 60. The single electron transistor 10
A floating capacitor 31a is formed at a common connection point between the floating capacitor 31a and the single electron transistor 60.

The single electron transistors 50 and 60 for charging / discharging are cascaded single electron transistors 1
The logic tree composed of 0 and 20 is charged and discharged. It is desirable that the voltage of the power supply 37 of this logic tree be set lower than the voltage of the power supply 45 of the CMOS inverter 40 as an amplifier. In the third embodiment, the power supply 37
Was set to 1/10 of the voltage of the power supply 45.

In the third embodiment,
Gate electrodes 14 and 2 of single electron transistors 10 and 20
It is desirable to set the amplitude of the input voltage to 4 to be equal to the voltage of the power supply 45 of the CMOS inverter 40.

The single electron transistors 10 and 20
The gate capacitance, the voltage potential difference i.e. power source 45 is applied between the CMOS inverter and V _CMOS, e /
(2V _CMOS ). This is because by setting the gate capacitances of the single electron transistors 10 and 20 in this manner, the CMOS inverter 40
Is equal to e / (2Cg), and the single electron transistors 10 and 20 can be operated while being completely switched between the ON state and the OFF state.

FIG. 10 shows a simulation result of the operation of the integrated circuit device according to the third embodiment. In FIG. 10, a graph g ₁ shows a waveform of an input voltage to the gate electrodes 14 and 24 of the single electron transistors 10 and 20, a graph g ₂ shows a voltage waveform of an output node 35 of the logic tree, and a graph g ₅ shows the output of the CMOS inverter 40, that shows the voltage waveform of the output of the integrated circuit device of this embodiment, the graph g ₆ shows the voltage waveform of the control clock inputted to the gate electrode 64 of the single-electron transistor 60.

As shown in FIG. 10, in the integrated circuit device of the present embodiment, when the control clock is "0", the output node 35 of the logic tree is precharged (graph g _2). CMOS inverter 40)
Are set to "0". If an input voltage is applied to the gate electrodes 14 and 24 of the single electron transistors 10 and 20 after activating the control clock, that is, setting it to "1", a logic output of the integrated circuit device of the present embodiment can be obtained. (see graph g _5).

As described above, according to the present embodiment, the amplitude of the input signal and the amplitude of the output signal can be configured to be the same, so that a single electronic element can be used as a component of the logic circuit.

FIG. 11 shows the structure of a fourth embodiment of the integrated circuit device having a single electronic device according to the present invention. The fourth embodiment of the integrated circuit device, comprising a plurality of single-electron transistor 71 _{1-71 14,} the logical tree 70 for exclusive operation of the four-input, single-electron transistor for charging 72 ₁ and 72 ₂ , a single electron transistor 73 for discharging, and CMOS inverters 40 a and 40 _b . The exclusive OR circuit 70 is configured to output one kind of complementary output Q, Q bar based on four kinds of complementary inputs A, A bar, B, B bar, C, C bar, D, D bar. ing. And CMOS inverters 40a, 40
b is used as the complementary output amplifier. Note that φ,
φ bar indicates the control clock. The C _f, C _F indicates the stray capacitor of the common connection point.

The exclusive OR circuit 70 is a clocked cascode voltage switch logic (LG Heller et. Al., One of the family of logics using complementary field effect transistors).
ISSCC Dig. Tech. Papers, 198
4, p16), so that all logical operations can be performed. However, MOSFET
Instead of using a single electron transistor in the logic tree section, higher integration is possible.
Further, simply replacing the logic tree portion of the clocked cascode voltage switch logic with a single-electron transistor does not operate normally. Therefore, the voltage of the power supply 37 of the logic tree 70 is reduced by the CMOS inverter 40.
It is characterized in that the voltage is lower than the voltage of the power supply 45 of the a and b. Conversely, single-electron transistors and field-effect transistors have different operating principles and, consequently, different operating characteristics. Therefore, simply replacing a field-effect transistor in a circuit with a field-effect transistor with a single-electron transistor generally works normally. Although it does not work, replacing the logic tree of clocked cascode voltage switch logic with single-electron transistors and reducing the power supply voltage of the logic tree to determine the logic circuit is a logic circuit using single-electron transistors It provides a guide for the design of

FIGS. 12A to 12D show simulation results of the operation of the integrated circuit device according to this embodiment. The waveform of the control clock φ is shown in FIG. 12A, and the input waveform of the gate electrode of the single electron transistor is shown in FIG.
FIG. 12B shows the voltage waveform at the output node 35 of the logic tree, and FIG. 12C shows the logic outputs Q and Q bar of the integrated circuit device according to the present embodiment.

As can be seen from FIGS. 12A to 12D, after the control clock φ becomes "1", the logic tree 7
A logical operation is performed based on input signals A, B, C, and D input to 0. Then, the amplitudes of the input signals A, B, C, D and the output signals Q, Q coincide with each other.

In the first to fourth embodiments, a single-electron transistor has been described as an example. However, a single-electron element utilizing a single-electron charging effect is used instead of the single-electron transistor. Needless to say, the same effect can be obtained.

FIG. 13 shows the structure of a fifth embodiment of the integrated circuit device having a single electronic device according to the present invention. The integrated circuit device according to the fifth embodiment is configured so that the output of the circuit block 80 is used as the input of the circuit block 90. At this time, as in the case of the fourth embodiment, the circuit block 80 includes a logic tree 81 composed of a single electronic element and a single electron for discharge provided between the logic tree 81 and the ground power supply. A single electronic element 8 for charging provided between the element 82 and the logic tree 81 and the driving power supply 84
3a and 83b, and an amplifying unit 85 including amplifiers 85a and 85b that receive and amplify the output of the logic tree 81.

Similarly, the circuit block 90 includes a logic tree 91 composed of a single electronic element and a single electronic element 9 for discharging.
2, single electronic elements 93a and 39b for charging, and amplifiers 95a and 95b for receiving and amplifying the output of the logic tree 91
And an amplifying section 95 comprising:

The voltage of the drive power supply 84 of the logic tree 81 is set to be lower than the voltage of the power supply 87 of the amplifier 85 composed of conventional elements. Here, the conventional element means a field-effect transistor, a bipolar transistor, or the like. For this reason, similarly to the fourth embodiment, the input (logical tree 9) of the circuit block 90 is performed.
1) and the output of the circuit block 80 (the output of the amplifying unit 85) can be made the same, and the output of the circuit block 80 can be used as the input of the circuit block 90. Also in the circuit block 90, it goes without saying that the voltage of the power supply 94 of the logic tree 91 is set to be lower than the voltage of the power supply 97 of the amplification unit 95.

As described above, in the circuit block 80 including the logic tree 81 composed of a single electronic element and the amplification unit 85 composed of a conventional element that amplifies the output of the logic tree 81, the logic tree having a high logic tree If the difference between the power supply voltage and the low power supply voltage is configured to be smaller than the difference between the high power supply voltage and the low power supply voltage of the amplifier unit 85, the input amplitude and the output amplitude of the circuit block 80 can be made the same. This enables the circuit block 80 to be used for an integrated circuit.

Thus, for example, the input of the circuit block 80 according to the fifth embodiment can be the output of a circuit composed of conventional elements or a single electronic element and an amplifier as in the sixth embodiment shown in FIG. Can be configured to receive the output of the circuit consisting of Further, as in the sixth embodiment shown in FIG. 14, the output of the circuit block 80 can be used as an input to a conventional device or an input to a single electronic device.

[0059]

As described above, according to the present invention, a single electronic device can be used as a component of a logic circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of an integrated circuit device having a single electronic element of the present invention.

FIG. 2 is a graph showing a simulation result of an operation of the first embodiment when the output amplitude is set to 1/10 of the input amplitude.

FIG. 3 is a graph showing a simulation result of an operation when the input amplitude of the integrated circuit device shown in FIG. 1 is made equal to the output amplitude;

FIG. 4 is a configuration diagram of a circuit device in which a control gate is further provided in the single electronic element according to the first embodiment.

5 is a graph showing a simulation result of an operation when the input amplitude of the circuit device shown in FIG. 4 is made equal to the output amplitude;

FIG. 6 is a configuration diagram of an integrated circuit device of a single electronic element showing a modification of the first embodiment.

FIG. 7 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 8 is a graph showing a simulation result of the operation of the second embodiment.

FIG. 9 is a circuit diagram showing a configuration according to a third embodiment of the present invention.

FIG. 10 is a graph showing a simulation result of the operation of the third embodiment.

FIG. 11 is a circuit diagram showing a configuration according to a fourth embodiment of the present invention.

FIG. 12 is a graph showing a simulation result of the operation of the fourth embodiment.

FIG. 13 is a configuration diagram of a fifth embodiment of the present invention.

FIG. 14 is a configuration diagram according to a sixth embodiment of the present invention.

FIG. 15 is a schematic view illustrating a configuration of a single-electron transistor.

FIG. 16 is an equivalent circuit diagram of a single-electron transistor.

FIG. 17 is a graph showing the gate voltage dependence of the source / drain current of a single-electron transistor.

FIG. 18 is a graph showing the gate voltage dependence of the source / drain current of a single-electron transistor.

FIG. 19 is a graph showing the gate voltage dependence of the source / drain current of a single-electron transistor.

FIG. 20 is a circuit diagram of an element in which a control gate is provided in a single-electron transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Conducting island 2 Drain electrode 3 Source electrode 4 Gate electrode 5,6 Tunnel junction 7 Drain capacitor 8 Source capacitor 9 Gate capacitor 10 Single electron transistor 11 Conducting island 12 Drain electrode 13 Source electrode 14 Gate electrode 15,16 Tunnel junction 17 Drain Capacitor 18 Source capacitor 19 Gate capacitor 20 Single electron transistor 21 Conducting island 22 Drain electrode 23 Source electrode 24 Gate electrode 25, 26 Tunnel junction 27 Drain capacitor 28 Source capacitor 29 Gate capacitor 33 Load capacitor 35 Output node 40 CMOS inverter (amplifier) 43 output node 45 drive power supply 47 load capacitor

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Claims (2)

(57) [Claims] 1. A logic tree comprising a plurality of single electronic elements and performing a predetermined logic operation, wherein a potential difference between a high power supply potential and a low power supply potential supplied to the logic tree is inputted to the logic tree. Wherein the difference between the maximum value and the minimum value of the voltage input to the single electronic element is smaller than that of the single electronic element. 2. The integrated circuit device according to claim 1, further comprising a charging / discharging circuit comprising a single electronic element and charging / discharging the logical tree based on a control clock.