JP2922691B2 - Digital data compensation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for compensating digital data, and more particularly, to a method for compensating for a bit lacking in digital data when converting the digital data into analog gradation.

[0002]

2. Description of the Related Art In a case where digital data as an instruction output from a computer as an input signal source has only two bits, for example, and an instruction receiving apparatus has, for example, three bits, the instruction receiving apparatus has three bits. A digital data compensation circuit has been conventionally used as an interface. FIG. 7 is a circuit diagram showing such a conventional digital data compensating circuit together with a digital / analog (D / A) converter such as a digital data / analog gradation converter and a load such as a liquid crystal display (LCD). In the figure, 1 is a conventional digital data compensation circuit,
It has three input terminals ROin, R1in and R2in, three output terminals R0out, R1out and R2out, and a switch 2 connected between the input terminal R0in and the output terminal R0out, for example, an analog switch, and has input terminals R1in and R2in. Are the output terminals R1ou, respectively.
t, R2out. Switch 2
A movable contact 2a connected to the output terminal R0out, a fixed contact 2b to which digital data of the normally 1 is input,
Fixed contact 2 to which digital data of normally 0 is input
c, and a fixed contact 2 directly connected to the input terminal R0in
d. Furthermore, output terminals R0out, R1out
The above-mentioned D / A converter 3 is connected to t and R2out, and the above-mentioned load 4 is connected to its output side.

In the conventional digital data compensating circuit 1 configured as described above, when 2-bit digital data D1 and D2 output from a computer (not shown) are input to input terminals R1in and R2in, respectively. , The lowest digital data input to the input terminal R0in is insufficient. Therefore, in order to compensate for the lack of digital data, the movable contact 2a of the switch 2 is moved to come into contact with the fixed contact 2b or 2c, so that the digital data D0 is obtained at the output terminal R0out.

When digital data D0 is fixed to normally 1 at fixed contact 2b, output terminals R0out to R2o
3-bit digital data D0 to D2 obtained in ut
Is as shown in Table 1 (a) below, and is converted into four gradations of 1/7, 3/7, 5/7 and 1 by the D / A converter 3, but gradation 0 is obtained. I can't.

Table 1 (a) D2 D1 D0 Gradation 0 0 1 1/7 0 1 1 1 3 7 1 0 1 1 5 1 7 1 1 1 1

When digital data D0 is fixed to normally 0, digital data D0-D2 and gradation are as follows:
As shown in Table 1 (b) below, gradation 1 cannot be obtained.

Table 1 (b) D2 D1 D0 Gradation 0 0 0 0 0 0 1 0 0 0 7 0 0 4/7 1 1 10 6/7

[0008]

Therefore, when a conventional digital compensation circuit is used to drive a load, for example, an LCD, it is not possible to obtain gradations 0 and 1 which greatly affect the contrast ratio of the LCD. was there. Therefore, in order to display optimal white and black on the LCD, the analog voltage value must be changed according to the number of bits of the input signal source. As an example, the digital data D0 is fixed to the normally 0, and the LC in the normally black mode is set.
Consider the case where D is driven. In this case, since the gradation 1 cannot be obtained as described above, it is necessary to change the analog voltage value in order to optimize the white display at the gradation 6/7. Therefore, it is necessary to newly add an adjustment function and a power supply, which leads to an increase in the system and an increase in cost.

Further, in a color LCD, the voltage-transmittance characteristic has wavelength dependence as shown in FIG. For this reason,
When all of the missing digital data D0 of red, green, and blue (hereinafter referred to as R, G, and B) are fixed to the same value of 1 or 0, the analog gradation of each of the R, G, and B colors becomes the same, and the color balance is reduced. Misalignment occurs. Therefore, in order to obtain a good color balance, a pedestal adjustment function is added and R,
The pedestal level is adjusted for each of the G and B colors, or a multi-gap structure panel in which the thickness of the liquid crystal layer of each of the R, G and B pixels is changed. However, when adjusting the pedestal level, it is necessary to newly add a pedestal adjustment function for each of R, G, and B colors. In the case of a multi-gap structure, it is necessary to control the thickness of the liquid crystal layer including the thickness of the color filter layer with extremely high precision. As described above, in the conventional example, there is also a problem that an increase in the system and an increase in cost are caused due to the addition of the adjustment function and the complexity of the manufacturing process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the invention according to claim 1 is a compensation method for compensating digital data so that gradations 0 and 1 are always reproduced. Claim 2
An object of the present invention is to provide a method for compensating digital data that can obtain a good color balance when the compensation method described in claim 1 is applied to a plurality of systems of a color LCD. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for compensating digital data that can use a conventional circuit.

[0011]

Means for Solving the Problems Claim 1 according to the present invention.
The described compensation method is such that when all of the input upper nk bits of data are 0, the logical operation result becomes 0 and n-
If all k-bit data is 1, the logical operation result is 1.
So that the input upper nk bits of the digital
Lower k bits obtained by performing logical operation on
In addition, the digital data of each bit is output as n bits together with the input digital data of the upper nk bits. A compensation method according to a second aspect of the present invention selects digital data to be selected for each system when the compensation method according to the first aspect is applied to a plurality of systems. In the compensation method according to the third aspect of the present invention, when the lower k-bit digital data is selected, the digital data of normally 1 and normally 0 are added to the selected digital data.

[0012]

According to the present invention, the gradations 0 and 1 are always reproduced according to the input high-order nk bit digital data by selecting the low-order k bit digital data as described above. According to the second aspect of the present invention, a good color balance can be obtained by selecting digital data to be selected for each system. In the invention according to claim 3,
A conventional circuit can be used, and it is only necessary to connect a desired logic element and an input terminal to the conventional circuit.

[0013]

【Example】

Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a digital data compensating circuit implementing a digital data compensating method according to the present invention together with a D / A converter. Digital data compensation circuit 1A
Includes a switch 2A, a logic element such as a two-input AND element 5 and a two-input OR element 6, in addition to the input terminals R0in to R2in and the output terminals R0out to R2out described above. The switch 2A includes a fixed contact 2 directly connected to the input terminal R1in, in addition to the movable contact 2a and the fixed contact 2d.
e, fixed contact 2f directly connected to input terminal R2in, AN
Fixed contact 2g directly connected to the output terminal of D element 5;
It has a fixed contact 2h directly connected to the output terminal of the R element 6. The input terminals of the AND element 5 and the OR element 6 are both connected to the input terminals R1in and R2in.

In the digital data compensating circuit 1A constructed as described above, by switching the movable contact 2a of the switch 2A to the fixed contact 2g, 2h, 2e or 2f, the logical product and the logical product of the input digital data D1 and D2 are obtained. The sum and one digital data selected from the input digital data D1 and D2 itself are supplied to the output terminal R0out as digital data D0. The input digital data D1 and D2 are supplied to output terminals R1out and R2out, respectively. Then, the digital data D0 to D2 supplied to the output terminals R0out to R2out are converted by the subsequent D / A converter 3A into analog gray scale described in detail below.

Now, assuming that the fixed contact 2g and therefore the AND element 5 are selected, the digital data D0 obtained at the output terminal R0out is given by the logical operation D0 = D1 · D2, and the obtained gradation is shown in Table 2 below. 0, as shown in a)
There are four gradations of 2/7, 4/7 and 1, and gradations 0 and 1 are reproduced according to the input 2-bit digital data.
Further, the same halftone gradation 2/7 and 4/7 can be obtained as in the conventional example in which the digital data D0 is fixed to normally 0.

Table 2 (a) D2 D1 D1 · D2 Gradation 0 0 0 0 0 0 1 0 2/7 10 0 4/4/7 11 1 1 1

Next, if the OR element 6 is selected,
The digital data D0 obtained at the output terminal R0out is given by a logical operation D0 = D1 + D2, and the obtained gradations are 0, 3/7, 5/7 and 1 as shown in Table 2 (b) below.
, And the gradations 0 and 1 are reproduced according to the input 2-bit digital data. Furthermore, at <br/> same halftone gradation 3/7 and in the case of fixing the digital data D0 to normally 1 Te 5/7 the conventional example can be obtained.

Table 2 (b) D2 D1 D1 + D2 Gradation 0 0 0 0 0 1 1 3/7 1 0 1 5/7 1 1 1 1

When the digital data D1 is used as the digital data D0 without using the AND element 5 and the OR element 6, that is, when the fixed contact 2e directly connected to the input terminal R1in is selected, the following table is used. As shown in FIG. 2 (c), not only gray levels 0 and 1 are reproduced according to the input 2-bit digital data, but also gray levels 3/7 and 4
/ 7 is obtained, and a combination of halftone gradations different from the case where the digital data D0 is fixed to normally 1 or normally 0 as in the conventional example can be obtained.

Table 2 (c) D2 D1 D1 Gradation 0 0 0 0 0 1 1 1 3 7 1 0 0 4/7 1 1 1 1 1

Similarly, when the digital data D2 is used as the digital data D0, the gradations 0 and 1 are reproduced according to the input 2-bit digital data as shown in Table 2 (d) below. Not only halftone gradations 2/7 and 5/7 can be obtained, but the digital data D0 is
It is possible to obtain a combination of halftone gradations different from the case where it is fixed to normally 1 or normally 0.

Table 2 (d) D2 D1 D2 Gradation 0 0 0 0 0 0 10 2/7 10 15 5/7 11 1 1 1

In any case, with the 3-bit digital data obtained by the above-described compensation method, gradations 0 and 1 can be reproduced according to the input 2-bit digital data.
Therefore, using this embodiment, for example, when driving an LCD, even when the number of input digital data is insufficient, the optimal white display and black display can be performed without changing the analog voltage value. A good contrast ratio can be obtained. Furthermore, the same or a new combination of displays can be obtained for the halftone gradation, and a total of 2 ² = 4 combinations of halftone gradations are possible, and an appropriate halftone display is obtained.

Embodiment 2 FIG. FIG. 2 is a circuit diagram showing a digital data compensating circuit for a second embodiment of the present invention. The digital data compensating circuit 1B is connected to the input terminal R0in
To R2in and output terminals R0out to R2out, an input terminal R3in and an output terminal R3out, and a switch 2B. In addition to the above-described AND element 5, a three-input AND element 5A and a three-input OR element 6A and 2
An input OR element 7 is provided. The switch 2B has an AN in addition to the movable contact 2a and the fixed contacts 2d to 2g described above.
Fixed contact 2i directly connected to the output terminal of D element 5A, OR
It has a fixed contact 2j directly connected to the output terminal of the element 6A, a fixed contact 2k directly connected to the output terminal of the OR element 7, and a fixed contact 2m directly connected to the input terminal R3in. The input terminals of the AND element 5A and the OR element 6A are both connected to the input terminals R1in to R3in, and the input terminal of the OR element 7 is connected to the output terminal and the input terminal R3in of the AND element 5.

In the digital data compensating circuit 1B configured as described above, by switching the movable contact 2a of the switch 2B to any one of the fixed contacts 2d to 2g, 2i to 2k, and 2m, the input digital data D1-D
3 and the logical sum of 3 and the input digital data D1
AND D2 and the logical sum of the logical product and the input digital data D3, and the input digital data D3
One digital data selected from 1 to D3 itself is supplied to the output terminal R0out as digital data D0. The input digital data D1 to D3 are supplied to output terminals R1out to R3out, respectively.

If digital data D0 is created using AND element 5A, digital data D0 is given by logical operation D0 = D1, D2, D3, and the obtained gradation is as shown in Table 3 (a). 0, 2/15, 4/15, ...
, 12/15 and 1 and are reproduced in gradations 0 and 1 according to the input 3-bit digital data.
Further, new halftone gradations 2/15,.
Is also obtained.

Table 3 (a) D3 D2 D1 D1.D2.D3 Gradation 0 0 0 0 0 0 0 0 1 0 2/15 0 1 1 0 0 4/15 0 1 1 1 0 6/15 1 0 0 0 8 / 15 1 0 10 0 10/15 1 11 0 0 12/15 1 1 1 1 1 1

Next, if the digital data D0 is produced using the OR element 6A, the digital data D0 is given by a logical operation D0 = D1 + D2 + D3, and the obtained gradation is as shown in Table 3 (b) below. 0, 3/15, 5/1
5,..., 13/15, and 1 are reproduced in 8 gradations according to the input 3-bit digital data. Further, a new halftone gradation 3/15,.
3/15 is also obtained.

Table 3 (b) D3 D2 D1 D1.D2.D3 Gradation 0 0 0 0 0 0 0 1 1 3/15 0 1 0 1 5/15 0 1 1 1 1 7/15 1 0 0 1 1 9 / 15 1 0 1 1 11/15 1 11 0 1 13/15 1 1 1 1 1 1

If digital data D0 is produced by using the AND element 5 , the digital data D0 is given by a logical operation D0 = D1 · D2, and the obtained gradation is as shown in Table 3 (c) below. 8 gradations including 0 and 1 are obtained.

Table 3 (c) D3 D2 D1 D1.D2 Gradation 0 0 0 0 0 0 0 0 0 0 1 0 2/15 0 1 0 0 4/1 5 0 1 1 1 1 7/15 1 0 0 0 8/15 1 0 1 0 10/15 1 1 0 0 12/15 1 1 1 1 1 1

Further, if digital data D0 is produced using the above-described AND element 5 and OR element 7, this digital data D0 is given by a logical operation D0 = D1, D2 + D3, and the obtained gradation is shown in Table 3 below. As shown in (d), eight gradations including gradations 0 and 1 are obtained.

Table 3 (d) D3 D2 D1 D1.D2 + D3 Gradation 0 0 0 0 0 0 0 1 0 2/15 0 1 1 0 0 4/15 0 1 1 1 1 7/15 1 0 0 1 9/15 1 0 1 1 11/15 1 1 0 1 13/15 1 1 1 1 1 1

In order to output digital data D1 of D1, D2 and D3 as digital data D0 to the output terminal R0out without using the AND elements 5 and 5A and the OR elements 6A and 7 as follows: Table 3
As shown in (e), gradations 0 and 1 are reproduced according to the input 3-bit digital data, and six halftone gradations are obtained. The same can be said for the case where digital data D2 or D3 is used instead of digital data D1.

Table 3 (e) D3 D2 D1 D1 Gradation 0 0 0 0 0 0 0 0 1 1 1 3 3 1 5 0 1 0 0 4/15 0 1 1 1 1 5/15 1 0 0 0 8/15 1 0 1 1 11/15 1 110 0 12/15 1 1 1 1 1 1

With the 4-bit digital data obtained by the above-described compensation method, in any case, gradations 0 and 1 are reproduced according to the input 3-bit digital data. Further, for the halftone gradation, a total of 2 ⁶ = 64 combinations of halftone gradations are possible, and an appropriate halftone display can be obtained.

Embodiment 3 FIG. FIG. 3 is a circuit diagram showing a digital data compensating circuit for a third embodiment of the present invention. The digital data compensating circuit 1C uses a switch 2C having two movable contacts 2a1 and 2a2 instead of the switch 2B in the digital data compensating circuit 1B shown in FIG. Here is an example of data shortage. The details of the third embodiment will be omitted because they are apparent from the description of the second embodiment.

As described above, the low-order 1 bit that is insufficient when 2-bit digital data is input is compensated to be 3 bits, or the low-order 1 bit that is insufficient when 3-bit or 2-bit digital data is input. Bit or lower 2 bits are compensated to be 4 bits, and the subsequent D / A
The method of compensation output to the converter has been described. However, in general, when the insufficient low-order k-bit digital data is created from the input high-order nk (n> k) -bit digital data and is output as n-bit digital data in total, the lacking digital It is easily presumed that a similar effect can be obtained by compensating the data by the above-described compensation method.

Further, in the above description of the embodiment, only one system, for example, the R system of the LCD has been described. However, the present invention can be applied not only to the R system but also to the G system and the B system. Further, the digital data compensating method of the present invention can be applied to a digital-analog converter other than the LCD.

In a color LCD, since the voltage-transmittance characteristic has wavelength dependence as shown in FIG. 8, when the same voltage is applied to each of the R, G, and B pixels, a color balance shift occurs. Therefore, it is possible to correct the color balance deviation in each of the R, G, and B colors by using the digital data compensation method of the present invention. That is, the analog gradation input to each of the R, G, and B pixels is converted into an appropriate value,
The wavelength dependency of the voltage-transmittance characteristic of the color LCD can be corrected.

Embodiment 4 FIG. FIG. 4 is a circuit diagram showing a digital data compensating circuit for a fourth embodiment of the present invention. This digital data compensating circuit basically uses the digital data compensating circuit 1B shown in FIG. 2 for a total of three R1B, G1B, and B1B for each of the R, G, and B systems. The difference is that when the 3-bit digital data D1, D2, and D3 are input, the second embodiment will be described. When compensating for the insufficient bits of digital data D0 by the compensation method described in
That is, the method of compensating the digital data D0 for each of the R, G, and B systems is changed. For example, in both the R and G systems, digital data created using the AND elements R5A and G5A is D0 (D0 = D1, D2, D3), and in the B system, digital data created using the OR element B6A is D0 ( D0 = D1 + D2 + D3)
The tones obtained in each of the R, G and B systems are given in Tables 4 (a), (b) and (c) below. And
As shown in FIG. 5, the analog gradation of the B system is larger than that of the R and G systems for the 3-bit digital data D1 to D3 of the R, G, and B systems. From the same digital data D1 to D3 input by such a compensation method, an appropriate analog gradation can be obtained for each of the R, G, and B systems.

Table 4 (a) D3 D2 D1 D1.D2.D3 Gradation 0 0 0 0 0 0 0 1 0 2/15 0 10 0 0 4/15 0 1 1 1 0 6/15 1 0 0 0 8 / 15 1 0 10 0 10/15 1 11 0 0 12/15 1 1 1 1 1 1

Table 4 (b) D3 D2 D1 D1.D2.D3 Gradation 0 0 0 0 0 0 0 1 0 2/15 0 10 0 4/15 0 1 1 1 1 0 6/15 1 0 0 8 / 15 1 0 10 0 10/15 1 11 0 0 12/15 1 1 1 1 1 1

Table 4 (c) D3 D2 D1 D1 + D2 + D3 Gradation 0 0 0 0 0 0 0 1 1 3/15 0 1 0 1 5/15 0 1 1 1 1 7/15 1 0 0 1 9/15 1 0 1 1 11/15 1 110 1 13/15 1 1 1 1 1 1

The compensation method for compensating the inputted 3-bit digital data and outputting the compensated 3-bit digital data to the 4-bit D / A converter has been described in connection with the case where the input is one system and three systems in parallel. The same applies to m parallel inputs.
By using the digital data compensating circuits, when compensating for the missing bits of each system, when selecting the digital data of the missing bits with the switch in the compensation method of the present invention, it is possible to select for each system. it can. That is, each system can be the same or different. In this way, when the contents of digital data input to each system are the same, the analog gradation obtained for each system can be the same or different, or the digital gray scale input to each system can be different. When the contents of the data are different, it is possible to obtain the same or different analog gradations for each system.

Embodiment 5 FIG. FIG. 6 shows the conventional digital data compensation circuit 1 of FIG. 7 and the digital data compensation circuit 1B of FIG.
FIG. 9 is a circuit diagram showing a digital data compensating circuit 1D obtained by combining the above. In this digital data compensating circuit 1D, when the movable contact 2a of the switch 2D is moved to contact the fixed contacts 2b and 2c as in the conventional example, the following Table 5 is used.
(A), digital data D0 to D3 and gradations shown in Table 5 (b) are obtained.

Table 5 (a) D3 D2 D1 D0 Gradation 0 0 0 1 1/15 0 0 1 1 1 3 1/15 0 1 0 1 5/15 0 1 1 1 1 7/15 1 0 0 1 9/15 1 0 1 1 11/15 1 1 0 1 13/15 1 1 1 1 1 1

Table 5 (b) D3 D2 D1 D0 Gradation 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 6/15 1 0 0 0 8/15 1 0 1 0 1 0 10/15 1 11 0 0 12/15 1 1 1 0 14/15

Naturally, when normally 1 or normally 0 is selected as the digital data D0, the gradation 0 or 1 cannot be reproduced, but the logic element (5
A, 6A, 5, 7, etc.), the digital data compensation method according to the present invention can be obtained.

[0050]

As described in detail above, the compensation method according to the first aspect of the present invention is obtained by performing a logical operation on at least a part of the input upper nk bit digital data. Selecting lower-order k-bit digital data from at least one digital data and the input higher-order nk-bit digital data, and selecting the selected digital data together with the input higher-order nk-bit digital data; Since the output is made with n bits in total, gradations 0 and 1 are always reproduced. Also, for the halftone gradation, a combination of the conventional halftone gradation and a new combination can be realized by appropriately combining the AND element and the OR element. Therefore, the present invention is used to drive an LCD, for example. In this case, the optimal white display and black display and several types of halftone display can be performed without changing the voltage value of the analog gradation depending on the number of bits of the input signal source. There is an effect that a medium tone display can be obtained. Further, in the compensation method according to the second aspect of the present invention, when the compensation method according to the first aspect is applied to a plurality of systems, the digital data to be selected can be selected for each system. Correction can be made, eliminating the need for a new analog voltage adjustment function or precise liquid crystal layer thickness control. Therefore, there is no need for an extra adjustment function, an increase in the number of power supplies, a complicated manufacturing process, and the like, and there is an effect that the size and cost of the system can be reduced. Furthermore, the compensation method of claim 3 of the present invention, when selecting the digital data of the lower k bits, the digital data normally 1 and normally 0. Because added to the selected digital data, conventional times
Supports multiple gradations by increasing the number of gradations compared to roads
There is also an effect that a method of compensating for the digital data can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing Embodiment 2 of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a relationship between digital data and analog gradation when the embodiment 4 shown in FIG. 4 is used.

FIG. 6 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a conventional digital data compensation method.

FIG. 8 is a diagram showing a voltage-transmittance characteristic of a color LCD.

[Explanation of symbols]

1A, 1B, 1C, R1B, G1B, B1B, 1D
Digital Data Compensation Circuit 2A, 2B, 2C, R2B, G2B, B2B Switch 2a, 2a1, 2a2 Movable Contact 5, 5A, R5A, G5A, B5A AND Element 6, 6A, R6A, G6A, B6A, 7 OR Element R0in, R1in , R2in, R3in input terminals G0in, G1in, G2in, G3in input terminals B0in, B1in, B2in, B3in input terminals R0out, R1out, R2out, R3out
Output terminal G0out, G1out, G2out, G3out
Output terminals B0out, B1out, B2out, B3out
Output terminal

──────────────────────────────────────────────────の Continuation of front page (51) Int.Cl. ⁶ Identification code FI G09G 3/20 641 G09G 3/20 641P 642 642J 650 650M (56) References JP-A-55-976 (JP, A) JP-A-59-216351 (JP, A) JP-A-61-257077 (JP, A) JP-A-2-271389 (JP, A) JP-A-3-94324 (JP, A) JP-A-4-287090 (JP) , A) JP-A-4-304495 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G09G 5/36 520 G06F 3/05 321 G06F 5/00 G06F 12/04 510 G06F 12/06 521 G09G 3/20 641 G09G 3/20 642 G09G 3/20 650

Claims (3)

(57) [Claims] 1. A method for compensating digital data in which insufficient low-order k-bit digital data is generated from input high-order nk (n> k) -bit digital data and output as n-bit digital data in total. , The input upper nk bits of digital data are all 0s.
In this case, the logical operation result becomes 0 and the data of nk bits
If all data are 1, the logical operation result will be 1.
Discuss the inputted upper nk bits of digital data.
Digital data of lower k bits obtained by performing a logical operation together with the input digital data of upper nk bits, and outputting the digital data. 2. A method for compensating digital data, wherein when the compensation method according to claim 1 is applied to a plurality of systems, digital data to be selected is selected for each system. 3. A method for compensating digital data in which insufficient low-order k-bit digital data is generated from input high-order nk (n> k) -bit digital data and output as n-bit digital data in total. , The input upper nk bits of digital data are all 0s.
In this case, the logical operation result becomes 0 and the data of nk bits
If all data are 1, the logical operation result is set to 1 before
Logic of the input upper nk bits of digital data
The lower k-bit digital data is selected from the digital data obtained by the calculation and the normally 1 and normally 0 digital data, and the selected digital data is input to the inputted upper nk-bit digital data. And compensating for digital data.