JP2921873B2 - Wiring capacity calculator - Google Patents
Wiring capacity calculatorInfo
- Publication number
- JP2921873B2 JP2921873B2 JP1225871A JP22587189A JP2921873B2 JP 2921873 B2 JP2921873 B2 JP 2921873B2 JP 1225871 A JP1225871 A JP 1225871A JP 22587189 A JP22587189 A JP 22587189A JP 2921873 B2 JP2921873 B2 JP 2921873B2
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- Japan
- Prior art keywords
- wiring
- layer
- capacitance
- power supply
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Design And Manufacture Of Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】 〔目次〕 概要 産業上の利用分野 従来の技術 発明が解決しようとする課題 課題を解決するための手段 作用 実施例 本発明の一実施例 （第１〜４図） 発明の効果 〔概要〕 配線容量を精度良く算出可能な配線容量算出装置に関
し、 配線容量を精度良く算出することができ、計算と実際
の製品との配線容量の誤差をなくすることができる配線
容量算出装置を提供することを目的とし、 LSIチップ上の配線線分が電源領域、セル領域、配線
に重なるときの重なり状態に対応した容量算出係数を記
憶する容量算出係数記憶手段と、前記電源領域、セル領
域、配線との重なり状態を設定する重なり状態設定手段
と、前記重なり状態設定手段の出力に基づいて配線容量
を算出しようとする配線線分の電源領域、セル領域、配
線との重なり状態毎の線長を算出する線長算出手段と、
前記配線線分の配線長のみによる容量に、前記重なり状
態に対応した容量算出係数と前記重なり状態毎の線長と
を掛け合わせ算出した容量の総和を加えて前記配線線分
の配線容量を算出する配線容量算出手段と、を備えて構
成する。DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial application Field of the Invention Prior Art Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment One Embodiment of the Present Invention (FIGS. 1 to 4) [Overview] Regarding a wiring capacitance calculating device capable of calculating wiring capacitance with high accuracy, a wiring capacitance can be calculated with high accuracy, and an error in the wiring capacitance between the calculation and the actual product can be eliminated. A capacity calculation coefficient storage unit for storing a capacity calculation coefficient corresponding to an overlapping state when a wiring line segment on an LSI chip overlaps a power supply area, a cell area, and a wiring; An overlap state setting means for setting an overlap state with the cell area and the wiring; and a power supply area, a cell area, and a wiring for a wiring line whose wiring capacity is to be calculated based on the output of the overlap state setting means. And line length calculating means for calculating a line length of each state becomes,
Calculate the wiring capacity of the wiring line by adding the sum of the capacitances calculated by multiplying the capacitance by only the wiring length of the wiring line by the capacitance calculation coefficient corresponding to the overlapping state and the line length of each overlapping state. And a wiring capacitance calculating means.
本発明は、配線容量算出装置に係り、詳しくは、LSI
チップ上で配線線分が電源領域、セル領域、配線等とそ
れぞれ重なり合う状態にあっても配線容量を精度良く算
出可能な配線容量算出装置に関する。The present invention relates to a wiring capacitance calculation device, and more particularly, to an LSI
The present invention relates to a wiring capacitance calculating device capable of accurately calculating a wiring capacitance even when a wiring line segment overlaps a power supply region, a cell region, a wiring, and the like on a chip.
トランジスタの微細化が進みその入力容量が小さくな
るに従って配線容量が増大し、配線容量がデバイスの動
作速度を律する大きな要因である寄生容量の大半を占め
るようになる。As the transistor becomes finer and its input capacitance decreases, the wiring capacitance increases, and the wiring capacitance occupies most of the parasitic capacitance, which is a major factor that determines the operation speed of the device.
したがって、LSIの設計において、配線容量が正確に
算出されないと、実際に製品を製作した場合、ゲートの
遅延時間等に計算結果との誤差が現れ、動作不良の原因
となる。このため、それぞれの重なり状態を認識して詳
細に配線容量を計算する必要がある。Therefore, if the wiring capacitance is not accurately calculated in the LSI design, when a product is actually manufactured, an error from the calculation result appears in a gate delay time or the like, which causes an operation failure. For this reason, it is necessary to calculate the wiring capacitance in detail by recognizing the respective overlapping states.
従来では、ゲートの遅延時間がさほどシビアに要求さ
れていなかったために、単に配線長より容量を求めて電
源領域、セル領域、配線との重なりにより影響される容
量を平均化して求めていた。すなわち、設計者が配線長
をもとに電源領域、セル領域等の重なり具合を勘案して
経験的に算出していた。In the related art, since the delay time of the gate is not required to be so severe, the capacitance affected by the overlap with the power supply region, the cell region, and the wiring is simply obtained by simply obtaining the capacitance from the wiring length. That is, the designer has empirically calculated the wiring length based on the degree of overlap of the power supply region, the cell region, and the like.
しかしながら、このような従来の配線容量算出装置に
あっては、年々ゲートのスイッチング時間の高速化が図
られる現状では計算上で得られた配線容量と実際のチッ
プ上の配線容量との誤差が大きくなる。したがって、上
記誤差を無視して製品を製作した場合に所望した特性の
ものが得られない、あるいは正常動作ができず動作不良
を生じるといった問題点が生じる。However, in such a conventional wiring capacitance calculation device, the error between the calculated wiring capacitance and the actual wiring capacitance on the chip is large under the current situation where the switching time of the gate is shortened year by year. Become. Therefore, when a product is manufactured ignoring the above error, a product having desired characteristics cannot be obtained, or a normal operation cannot be performed and an operation failure occurs.
そこで本発明は、配線容量を精度良く算出することが
でき、計算上と実際の製品との配線容量の誤差をなくす
ることができる配線容量算出装置を提供することを目的
としている。Therefore, an object of the present invention is to provide a wiring capacitance calculating device capable of calculating a wiring capacitance with high accuracy and eliminating an error in the wiring capacitance between the calculation and the actual product.
本発明による配線容量算出装置は上記目的達成のた
め、LSIチップ上の配線線分が電源領域、セル領域、配
線に重なるときの重なり状態に対応した容量算出係数を
記憶する容量算出係数記憶手段と、前記電源領域、セル
領域、配線との重なり状態を設定する重なり状態設定手
段と、前記重なり状態設定手段の出力に基づいて配線容
量を算出しようとする配線線分の電源領域、セル領域、
配線との重なり状態毎の線長を算出する線長算出手段
と、前記配線線分の配線長のみによる容量に、前記重な
り状態に対応した容量算出係数と前記重なり状態毎の線
長とを掛け合わせ算出した容量の総和を加えて前記配線
線分の配線容量を算出する配線容量算出手段と、を備え
ている。In order to achieve the above object, a wiring capacity calculation device according to the present invention includes a capacity calculation coefficient storage unit that stores a capacity calculation coefficient corresponding to an overlapping state when a wiring line segment on an LSI chip overlaps a power supply area, a cell area, and a wiring. An overlapping state setting means for setting an overlapping state of the power supply area, the cell area, and the wiring; and a power supply area, a cell area for a wiring line whose wiring capacitance is to be calculated based on an output of the overlapping state setting means.
A line length calculating means for calculating a line length for each overlapping state with the wiring, and a capacitance based only on the wiring length of the wiring line, multiplied by a capacitance calculation coefficient corresponding to the overlapping state and a line length for each overlapping state. Wiring capacitance calculating means for calculating the wiring capacitance of the wiring line by adding the sum of the calculated capacitances.
本発明では、配線線分の電源領域、セル領域、配線等
との重なり状態に応じて配線線分の配線容量が算出され
る。According to the present invention, the wiring capacitance of the wiring line is calculated according to the overlapping state of the wiring line with the power supply region, the cell region, the wiring, and the like.
したがって、配線容量算出の影響を与える電源領域、
セル領域、配線等の重なり状態を認識して配線容量が算
出される。その結果、計算上で得られた配線容量と実際
の製品の配線容量との誤差が減少し、チップ性能が向上
する。Therefore, the power supply area which affects the wiring capacity calculation,
The wiring capacity is calculated by recognizing the overlapping state of the cell region, the wiring and the like. As a result, the error between the calculated wiring capacitance and the wiring capacitance of the actual product is reduced, and the chip performance is improved.
最初に、本発明の原理から説明する。 First, the principle of the present invention will be described.
本発明は、配線層毎に示される単位容量および配線層
毎に示される電源領域、セル領域、配線との重なりによ
る容量算出係数により配線容量を算出するものである。
以下、「容量の算出方法」と「容量算出式」に分けて具
体的に説明する。According to the present invention, a wiring capacitance is calculated based on a unit capacitance indicated for each wiring layer and a capacitance calculation coefficient based on an overlap with a power supply region, a cell region, and a wiring indicated for each wiring layer.
Hereinafter, a specific description will be given separately for the “capacity calculation method” and the “capacity calculation formula”.
容量の算出 1.まず、電源データを層コード識別可能な電源パターン
として設定する。Calculation of capacity 1. First, set the power supply data as a power supply pattern that can identify the layer code.
2.次いで、配線データを層別にラインデータパターンと
して設定する。2. Next, the wiring data is set as a line data pattern for each layer.
3.層別のラインデータパターンに対して、電源パターン
の重なりを設定する。3. Set overlapping power supply patterns for line data patterns for each layer.
4.最後に、重なり状態に応じた容量算出数を用いて配線
容量を算出する。4. Finally, calculate the wiring capacitance using the calculated capacitance number according to the overlapping state.
容量算出式 a.配線長のみによる容量 CL＝Ｌ×CG …… b.配線長と層間重なりによる容量 TCL＝CL＋Σ（L0×CG×Ｋ） …… 但し、CL :配線長のみによる容量 L :配線長 CG :層別の単位容量（単位はグリッド） TCL:層間重なりによる容量 K :配線層毎の層間重なりによる容量算出係数 L0 :重なった層の線長 したがって、第式に示すように配線線分の重なり状
態を認識して配線容量を算出するため、配線容量算出時
の誤差が大幅に減少する。.. Capacity calculating equation a wiring length capacitance only by C L = L × C G ...... b capacitance TC L = C L + Σ ( L 0 × C G × K) by overlapping the wiring length and the interlayer ...... However, C L: Capacitance based only on wiring length L: Wiring length C G : Unit capacitance per layer (unit is grid) TC L : Capacitance due to interlayer overlap K: Capacitance calculation coefficient due to interlayer overlap for each wiring layer L 0 : Line length of overlapping layers Therefore, as shown in the equation, the wiring capacitance is calculated by recognizing the overlapping state of the wiring lines, so that the error in calculating the wiring capacitance is greatly reduced.
〔実施例〕 以下、本発明を図面に基づいて説明する。EXAMPLES Hereinafter, the present invention will be described with reference to the drawings.
第１〜４図は本発明に係る配線容量算出装置の一実施
例を示す図であり、本実施例は電源３層、配線２層のLS
Iチップの配線容量を算出する例である。FIGS. 1 to 4 are diagrams showing an embodiment of a wiring capacitance calculating apparatus according to the present invention.
This is an example of calculating the wiring capacitance of the I chip.
まず、構成を説明する。第１図はシステム構成を示す
図である。第１図において、１はシステムバスであり、
システムバス１を介して中央処理装置（CPU）２、メモ
リ３、マウスを有するキーボード４、プリンタ５および
CRT等の表示器６が接続されている。中央処理装置（CP
U）２は後述する所定のプログラムに基づいて配線容量
を算出する機能（線長算出手段および配線容量算出手
段）を有し、メモリ３には中央処理装置（CPU）２が行
う処理を規定したプログラムとその処理を実行するのに
必要な情報（容量算出係数記憶手段）が予め記憶されて
おり、また、配線容量算出結果が格納される。キーボー
ド４は設計者がプログラムおよび配線容量算出に必要な
データ（重なり状態設定手段）を入力したり、中央処理
装置（CPU）２に対して各プログラムの実行開始を指示
あるいは配線容量算出結果をプリンタ５または表示器６
に出力させるためのものである。上記システムバス１、
中央処理装置２、メモリ３、キーボード４、プリンタ５
および表示器６は全体として配線容量算出装置７を構成
している。First, the configuration will be described. FIG. 1 is a diagram showing a system configuration. In FIG. 1, 1 is a system bus,
A central processing unit (CPU) 2, a memory 3, a keyboard 4 having a mouse, a printer 5,
A display 6 such as a CRT is connected. Central processing unit (CP
U) 2 has a function of calculating a wiring capacity based on a predetermined program described later (line length calculating means and wiring capacity calculating means), and the memory 3 defines processing performed by the central processing unit (CPU) 2. A program and information (capacity calculation coefficient storage means) necessary for executing the processing are stored in advance, and a wiring capacity calculation result is stored. The keyboard 4 allows the designer to input a program and data (overlapping state setting means) necessary for calculating the wiring capacity, instruct the central processing unit (CPU) 2 to start execution of each program, or print the wiring capacity calculation result to the printer. 5 or display 6
Is to be output. The above system bus 1,
Central processing unit 2, memory 3, keyboard 4, printer 5
The display 6 constitutes a wiring capacitance calculating device 7 as a whole.
第２図はLSIチップの断面を概略的に示す図であり、
この図において、L1は１層配線、L2は２層配線、V2は２
層電源領域、V3は３層電源領域を表している。このLSI
チップを配線容量算出方法を以下に述べる作用で説明す
る。FIG. 2 is a diagram schematically showing a cross section of an LSI chip,
In this figure, L1 is a one-layer wiring, L2 is a two-layer wiring, and V2 is a two-layer wiring.
The layer power region, V3, represents a three-layer power region. This LSI
The method of calculating the wiring capacitance of the chip will be described with the operation described below.
次に、作用を説明するが、まず、第３図に示す処理フ
ローを用いて配線容量算出がどの工程で必要になるかを
述べる。図中Pn（ｎ＝1,2,……）はフローの各ステップ
を示している。この図において、P1で論理回路図を読み
取り、P2で前処理を行う。次いで、P3で自動配置、P4で
自動配線をし、P5で配線容量を算出する。次いで、P6で
P5で算出した配線容量を用いてパス又はネットの容量を
チェックし、P7でレイアウト結果がもとの論理シュミレ
ーションと合っているかを実容量シュミレーションす
る。次いで、P8でマスクデータを作成し、P9でこのマス
クデータに基づいてマスクを作成する。上述したよう
に、配線容量算出は配置・配線の後に行われ（ステップ
P5）、ここで算出された配線容量に従ってパス又は配線
ネットの容量チェックおよび実容量シュミレーションが
行われる。したがって、配線容量が精度よく求められな
いと、十分な配線遅延対策がとれないことからチップ性
能の向上が図れないことになる。Next, the operation will be described. First, in which step the wiring capacitance calculation is required will be described using the processing flow shown in FIG. In the figure, Pn (n = 1, 2,...) Indicates each step of the flow. In this figure, reading the logic circuit diagram in P 1, preprocessing is performed by P 2. Then, automatic placement at P 3, and the automatic routing in P 4, calculates the wiring capacity at P 5. Then, in a P 6
Check the capacity of the path or the net by using a wiring capacity calculated by the P 5, or the the actual capacity simulation layout result in the P 7 is correct as the original logic simulation. Then, to create a mask data at P 8, to create a mask based on the mask data at P 9. As described above, the calculation of the wiring capacity is performed after the placement and wiring (step
P 5), capacity checking and actual capacity simulation paths or nets is carried out in accordance with the calculated wiring capacitance here. Therefore, unless the wiring capacitance is required with high accuracy, it is not possible to take sufficient measures against the wiring delay, so that the chip performance cannot be improved.
第４図は配線容量算出のプログラムを示すフローチャ
ートである。FIG. 4 is a flowchart showing a program for calculating the wiring capacitance.
プログラムが開始すると、まず、P11で配線層毎のそ
れぞれの重なり状態による容量算出係数Ｋ（L2−V3）、
Ｋ（V2）、Ｋ（V3）を読み込み、P12でチップ上の電源
領域（V2）、（V3）およびセル領域を読み込む。次い
で、P13で１層ラインパターン、２層ラインパターン、
３層でラインパターンにそれぞれ電源パターン、ライン
パターンの重なりを設定し、P14でステップP13で設定し
たデータから注目している配線層の電源、セル、配線と
の重なり状態別の長さL0（L2−V3）、L0（V2）、L0（V
3）を算出する。次いで、P15で線長のみによる容量CLを
算出し、P16で次式、で示される算出式をもとに重
なり状態別の長さの重なり状態による容量算出係数から
重なりによって影響される第２図の１層配線L1の配線容
量を算出し、線長のみによる容量CLに足し込んで今回の
処理を終了する。When the program starts, first, the capacity calculation coefficient K by each of the overlapping state of each wiring layer in P 11 (L2-V3),
K (V2), reads the K (V3), the power supply area on the chip at P 12 (V2), read (V3) and the cell area. Then, one layer line pattern P 13, 2-layer line pattern,
Each power supply pattern to the line pattern of three layers, overlapping sets of line patterns, the power supply wiring layer of interest from the data set in step P 13 in P 14, a cell, a specific overlap state between the wiring length L 0 (L2-V3), L 0 (V2), L 0 (V
Calculate 3). Then, to calculate the capacitance C L by at P 15 line length only, is affected by the overlap with P 16 using the following equation, in the capacity calculation coefficient by overlapping state by state length overlap on the basis of the calculation formula shown the second view of calculating the wiring capacity of the one-layer wiring L1, the current processing is terminated crowded adds to the capacitance C L by line length only.
CL＝Ｌ×CG …… TCL＝CL＋L0（L2−V3）×CG ×Ｋ（L2−V3）＋L0（V2） ×CG×Ｋ（V2）＋L0（V3） ×CG×Ｋ（V3） …… 但し、 L:1層配線の線長 10〔グリッド〕 CG:1層配線の単位容量 20〔Lu（ローディングユニッ
ト）〕 CL:1層配線の線長×１層配線の単位容量＝10×20＝200
〔Lu〕 L0（L2−V3） :2層配線、３層電源との重なった線長 ５〔グリッ
ド〕 L0（V2）:2層電源との重なった線長 ３〔グリッド〕 L0（V3）:3層電源との重なった線長 １〔グリッド〕 Ｋ（L2−V3） :2層配線、３層電源との重なりによる容量算出係数 1.5 Ｋ（V2）:2層電源との重なりによる容量算出係数 1.2 Ｋ（V3）:3層電源との重なりによる容量算出係数 1.1 TCL:層間重なりを考慮した総配線容量 第式に各係数を代入して計算した計算式が第式で
示される。 C L = L × C G ...... TC L = C L + L 0 (L2-V3) × C G × K (L2-V3) + L 0 (V2) × C G × K (V2) + L 0 (V3) × C G × K (V3) …… However, L: line length of 1 layer wiring 10 [grid] C G : unit capacity of 1 layer wiring 20 [Lu (loading unit)] C L : line length of 1 layer wiring x Unit capacitance of single-layer wiring = 10 x 20 = 200
[Lu] L 0 (L2−V3): 2-layer wiring, line length overlapping with 3-layer power supply 5 [grid] L 0 (V2): Line length overlapping with 2-layer power supply 3 [grid] L 0 ( V3): Line length overlapped with 3-layer power supply 1 [Grid] K (L2-V3): Capacity calculation coefficient due to overlap with 2-layer wiring and 3-layer power supply 1.5 K (V2): Due to overlap with 2-layer power supply capacity calculation coefficient 1.2 K (V3): the overlap capacitance calculation coefficient by 1.1 TC L of the three-layer power supply: the equation calculated by substituting the coefficients in the total wiring capacitance the equation considering the overlapping layers represented by the formula .
TCL＝200＋５×20×1.5＋３×20×1.2＋１×20×1.1＝365〔Lu〕 …… ここで、第式のL0（V3）が６〔グリッド〕ではなく
１〔グリッド〕になっているのは２層配線L2と重なり合
った部分の線長による容量は無視し得ること考えられる
からである。TC L = 200 + 5 × 20 × 1.5 + 3 × 20 × 1.2 + 1 × 20 × 1.1 = 365 [Lu] Here, L 0 (V3) in the expression becomes 1 [grid] instead of 6 [grid]. This is because the capacitance due to the line length of the portion overlapping with the two-layer wiring L2 can be ignored.
以上は、第２図の概略断面図示すように電源３層、配
線２層チップの配線容量を算出した例であるが、第、
を用いることにより同様の算出方法で配線容量を算出
することができる。例えば、電源４層、配線３層のチッ
プの各層の電源、は配線との重なり状態は以下のように
示される。但し、L1は１層配線、L2は層配線、L3は３層
配線、C1は１層セル領域、V1は１層電源領域、V2は２層
電源領域、V3は３層電源領域、V4は４層電源領域を表す
ものとする。The above is an example of calculating the wiring capacitance of a three-layer power supply and a two-layer wiring chip as shown in the schematic sectional view of FIG.
Is used, the wiring capacitance can be calculated by the same calculation method. For example, the power supply of each layer of a chip having four layers of power supply and three layers of wiring, and the state of overlap with the wiring are shown as follows. However, L1 is a one-layer wiring, L2 is a layer wiring, L3 is a three-layer wiring, C1 is a one-layer cell region, V1 is a one-layer power region, V2 is a two-layer power region, V3 is a three-layer power region, and V4 is four. It represents a layer power supply region.
１層配線時の電源、配線との重なり状態 （１） ４層電源との重なり係数 L1−V4 （２） ２層、４層電源との重なり係数 L1−V2,V4 （３） ３層、４層電源との重なり係数 L1−V3,V4 （４） ２層、３層、４層電源との重なり係数L1−V2,V
3,V4 （５） ２層LINE、４層電源との重なり係数 L1−L2,V4 （６） ２層LINE、３層、４層電源との重なり係数Ｌ−
1L−2,V3,V4 （７） ３層LINE、２層、４層電源との重なり係数L1−
L3,V4 （８） ３層LINE、２層、４層電源との重なり係数L1−
L3,V2,V4 （９） ２層、３層LINE、４層電源との重なり係数L1−
L2,V3,V4 ２層配線時の電源、セル、配線との重なり状態 （１） ４層電源との重なり係数 L2−V4 （２） １層、４層電源との重なり係数 L2−V1,V4 （３） ３層、４層電源との重なり係数 L2−V3,V4 （４） １層、３層、４層電源との重なり係数L2−V1,V
3,V4 （５） １層セル領域、４層電源との重なり係数 L2−C
1,V4 （６） １層セル領域、３層電源、４層電源との重なり
係数 L2−C1,V3,V4 （７） １層LINE、４層電源との重なり係数 L2−L1,V4 （８） １層LINE、３層、４層電源との重なり係数L2−
L1,V3,V4 （９） ３層LINE、４層電源との重なり係数 L2−L3,V4 （10） ３層LINE、１層、４層電源との重なり係数L2−
L3,V1,V4 （11） １層セル領域、３層LINE、４層電源との重なり
係数 L2−C1,L3,V4 （12） １層、３層LINE、４層電源との重なり係数L2−
L1,L3,V4 ３層配線時の電源、セル、配線との重なり状態 （１） ４層電源との重なり係数 L3−V4 （２） １層、４層電源との重なり係数 L3−V1,V4 （３） ２層、４層電源との重なり係数 L3−V2,V4 （４） １層、２層、４層電源との重なり係数L3−V1,V
2,V4 （５） １層セル領域、４層電源との重なり係数 L3−C
1,V4 （６） １層セル領域、２層電源、４層電源との重なり
係数 L3−C1,V2,V4 （７） １層LINE、４層電源との重なり係数 L3−L1,V4 （８） １層LINE、２層、４層電源との重なり係数L3−
L1,V2,V4 （９） ２層LINE、４層電源との重なり係数 L3−L2,V4 （10） ２層LINE、１層、４層電源との重なり係数L3−
L2,V1,V4 （11） １層セル領域、２層LINE、４層電源との重なり
係数 L3−C1,L2,V4 （12） １層、２層LINE、４層電源との重なり係数L3−
L1,L2,V4 以上述べたように本実施例では、配線長による単位容
量CLに加えて、各層電源領域・配線と重なった線長およ
びその重なり状態に応じた容量算出係数を基に算出され
た重なり状態を示す配線容量を用いて配線容量を算出し
ている。したがって、電源領域、セル領域、配線などの
層間重なりによる配線容量の変化から計算誤差を抑える
効果を奏し、チップ性能の向上に寄与するところが大き
い。Power supply in single-layer wiring, overlapping state with wiring (1) Overlap coefficient with 4-layer power supply L1-V4 (2) Overlap coefficient with 2-layer, 4-layer power supply L1-V2, V4 (3) 3-layer, 4 Overlap coefficient L1-V3, V4 with layer power supply (4) Overlap coefficient L1-V2, V with 2-layer, 3-layer, 4-layer power supply
3, V4 (5) 2-layer LINE, overlap coefficient with 4-layer power supply L1−L2, V4 (6) 2-layer LINE, 3-layer, overlap coefficient with 4-layer power supply L−
1L−2, V3, V4 (7) Overlap coefficient L1− with 3 layer LINE, 2 layer, 4 layer power supply
L3, V4 (8) 3-layer LINE, 2-layer, 4-layer overlap coefficient L1-
L3, V2, V4 (9) Overlap coefficient L1−
L2, V3, V4 Overlapping state with power supply, cell, and wiring in 2-layer wiring (1) Overlap coefficient with 4-layer power supply L2-V4 (2) Overlap coefficient with 1-layer, 4-layer power supply L2-V1, V4 (3) Overlap coefficient L2-V3, V4 with three-layer, four-layer power supply (4) Overlap coefficient L2-V1, V with one-layer, three-layer, four-layer power supply
3, V4 (5) 1-layer cell area, overlap coefficient with 4-layer power supply L2-C
1, V4 (6) One-layer cell area, three-layer power supply, overlap coefficient with four-layer power supply L2-C1, V3, V4 (7) One-layer LINE, four-layer power supply overlap coefficient L2-L1, V4 (8 ) 1-layer LINE, 3-layer, 4-layer overlap coefficient L2-
L1, V3, V4 (9) 3-layer LINE, overlap coefficient with 4-layer power supply L2- L3, V4 (10) 3-layer LINE, 1-layer, overlap coefficient with 4-layer power supply L2-
L3, V1, V4 (11) Overlap coefficient with 1-layer cell area, 3-layer LINE, 4-layer power supply L2-C1, L3, V4 (12) Overlap coefficient L2- with 1-layer, 3-layer LINE, 4-layer power supply
L1, L3, V4 Overlap state with power supply, cell, and wiring in three-layer wiring (1) Overlap coefficient with four-layer power supply L3-V4 (2) Overlap coefficient with one-layer, four-layer power supply L3-V1, V4 (3) Overlap coefficient L3-V2, V4 with two-layer, four-layer power supply (4) Overlap coefficient L3-V1, V with one-layer, two-layer, four-layer power supply
2, V4 (5) 1-layer cell area, overlap coefficient with 4-layer power supply L3-C
1, V4 (6) Overlap coefficient with single-layer cell area, two-layer power supply, four-layer power supply L3-C1, V2, V4 (7) Overlap coefficient with one-layer LINE, four-layer power supply L3-L1, V4 (8 ) 1-layer LINE, 2-layer, 4-layer overlap coefficient L3-
L1, V2, V4 (9) Overlap coefficient with 2-layer LINE, 4-layer power supply L3−L2, V4 (10) Overlap coefficient L3- with 2-layer LINE, 1-layer, 4-layer power supply
L2, V1, V4 (11) Overlap coefficient with 1-layer cell area, 2-layer LINE, 4-layer power supply L3-C1, L2, V4 (12) Overlap coefficient L3- with 1-layer, 2-layer LINE, 4-layer power supply
L1, L2, V4 As described above, in this embodiment, in addition to the unit capacitance C L based on the wiring length, calculation is performed based on the line length overlapping each power supply region / wiring in each layer and the capacitance calculation coefficient according to the overlapping state. The wiring capacitance is calculated using the wiring capacitance indicating the overlapped state. Therefore, there is an effect of suppressing a calculation error due to a change in wiring capacitance due to an interlayer overlap of a power supply region, a cell region, a wiring, and the like, which greatly contributes to an improvement in chip performance.
本発明によれば、配線容量を精度良く算出することが
でき、計算上と実際の製品との配線容量の誤差をなくす
ことができる。According to the present invention, the wiring capacitance can be calculated with high accuracy, and the error in the wiring capacitance between the calculation and the actual product can be eliminated.
第１〜４図は本発明に係る配線容量算出装置の一実施例
を示す図であり、 第１図はそのシステム構成図、 第２図はそのLSIチップの概略断面図、 第３図はその半導体製造の処理フロー、 第４図はその配線容量算出のプログラムを示すフローチ
ャートである。 １……システムバス、 ２……中央処理装置（線長算出手段、配線容量算出手
段）、 ３……メモリ（容量算出係数記憶手段）、 ４……キーボード（重なり状態設定手段）、 ５……プリンタ、 ６……表示器、 ７……配線容量算出装置、 CL:配線長のみによる容量、 L:配線長、 CG:層別単位容量、 TCL:層間重なりによる容量、 K:配線層毎の層間重なりによる容量算出係数、 L0:重なった層の線長。1 to 4 are diagrams showing an embodiment of a wiring capacitance calculating apparatus according to the present invention. FIG. 1 is a system configuration diagram, FIG. 2 is a schematic sectional view of the LSI chip, and FIG. FIG. 4 is a flowchart showing a program for calculating the wiring capacitance. 1 ... system bus, 2 ... central processing unit (wire length calculation means, wiring capacity calculation means), 3 ... memory (capacity calculation coefficient storage means), 4 ... keyboard (overlapping state setting means), 5 ... printer, 6 ...... indicator, 7 ...... wiring capacity calculating apparatus, C L: capacity due only the wiring length, L: line length, C G: stratification unit capacity, TC L: capacitance due to overlapping layers, K: interconnection layer Capacitance calculation coefficient for each interlayer overlap, L 0 : line length of overlapped layers.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/82 G06F 17/50 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/82 G06F 17/50
Claims (1)
領域、配線に重なるときの重なり状態に対応した容量算
出係数を記憶する容量算出係数記憶手段と、 前記電源領域、セル領域、配線との重なり状態を設定す
る重なり状態設定手段と、 前記重なり状態設定手段の出力に基づいて配線容量を算
出しようとする配線線分の電源領域、セル領域、配線と
の重なり状態毎の線長を算出する線長算出手段と、 前記配線線分の配線長のみによる容量に、前記重なり状
態に対応した容量算出係数と前記重なり状態毎の線長と
を掛け合わせ算出した容量の総和を加えて前記配線線分
の配線容量を算出する配線容量算出手段と、を備えたこ
とを特徴とする配線容量算出装置。1. A capacity calculation coefficient storage means for storing a capacity calculation coefficient corresponding to an overlapping state when a wiring line segment on an LSI chip overlaps a power supply area, a cell area, and a wiring, the power supply area, the cell area, and the wiring An overlapping state setting means for setting an overlapping state with the power supply area, a cell area, and a wire length of each wiring state for which a wiring capacity is to be calculated based on the output of the overlapping state setting means. A line length calculating means to calculate, and adding a total sum of capacitances calculated by multiplying a capacitance based only on the wiring length of the wiring line by a capacitance calculation coefficient corresponding to the overlapping state and a line length for each overlapping state. A wiring capacitance calculating device, comprising: wiring capacitance calculating means for calculating the wiring capacitance of the wiring lines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1225871A JP2921873B2 (en) | 1989-08-31 | 1989-08-31 | Wiring capacity calculator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1225871A JP2921873B2 (en) | 1989-08-31 | 1989-08-31 | Wiring capacity calculator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0389531A JPH0389531A (en) | 1991-04-15 |
| JP2921873B2 true JP2921873B2 (en) | 1999-07-19 |
Family
ID=16836159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1225871A Expired - Fee Related JP2921873B2 (en) | 1989-08-31 | 1989-08-31 | Wiring capacity calculator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2921873B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11353338A (en) | 1998-06-04 | 1999-12-24 | Mitsubishi Electric Corp | Method for simulating integrated circuit, and recording medium |
-
1989
- 1989-08-31 JP JP1225871A patent/JP2921873B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0389531A (en) | 1991-04-15 |
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