JP2919155B2 - Policing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for asynchronous transfer mode packet communication. In particular, VP (Virtual P
ass) Number management technology.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIGS. FIG. 3 is a block diagram of a conventional DB circuit. FIG. 4 is a diagram showing the state of the FIFO in the DB circuit.

As shown in FIG. 3, a conventional policing circuit has memories 21, 22, and 25 and a FIFO 28.
, A selector unit 20, a logic processing unit 24, a count memory 26, and a discard unit 3. This is DB (D
An angle bridge (polishing circuit) is referred to as a polishing circuit.

The input ATM (asynchronous transfer mode) cell V
PI (Virtual PassIdentify)
r) The number is input to the memory 21 and the FIFO 28.
The memory 21 inputs a VPI number and outputs an item type number. The memory 25 inputs the item type number and outputs the upper limit of the number of cells in the T time of the item. The VPI number and the item type number are stored in the FIFO indicated in the write address 27.
28 are written. At this time, the write address 27 is selected by the selector 20. The memory 22
The serial number output from the counter 23 is input as the item type number, and the address of the corresponding FIFO 28 is output. The VPI number and the item type number of the address of the FIFO 28 are output from the DATA output of the FIFO 28.
The count memory 26 stores the VP output from the logic processing unit 24.
The I number is input, and the upper limit value count information corresponding to the VPI number is transmitted / received to / from the logic processing unit 24. Logical processing unit 24
Is the count value output from the counter 23, the VPI number,
Based on the item type number and the upper limit value, the upper limit value count of the VP indicated by the VPI number of the DATA output of the FIFO 28 is incremented or decremented and stored in the count memory 26. Also,
The discard of the input ATM cell is determined, and a discard instruction signal is output to the discard unit 3. The discard unit 3 discards the input cell based on the discard instruction signal.

[0005] Next, referring to FIG.
The state of O will be described.

The individual VPI information 30 is stored in a state as shown in FIG. The size 31 of the VPI information is Log
₂ (VPI) bits. VP of FIFO28
The number of I information 32 is the maximum length T of the target VP item.
At least for each value. Input VP at a certain point
The write address 33 and read address 34 of I are as shown in FIG. The number of items 35 is determined by the nature of the traffic, and increases as the type of VPI increases.

The FIFO 28 has a VPI arriving at one cell time.
It is necessary to write the number and read the address of only 35 items. Therefore, it cannot be applied to a high-speed transmission line. FIFO to avoid access timeneck
28 parallelization, but requires a significant increase in hardware.

[0008]

In such a system,
It is necessary to access the FIFO several times within one cell time, and there is a problem that the access speed of the FIFO increases according to the number of items. In particular, this is a problem when the interface speed is high and when the number of items is large.

The present invention has been made under such a background, and has a separate processing circuit for each VPI number to reduce the load on the DB circuit to achieve high-speed operation and to suppress an increase in hardware scale. The purpose is to provide a policing circuit.

[0010]

SUMMARY OF THE INVENTION The present invention provides a TPI for each VPI.
There is a contract that the cell arriving at the input during the cell time does not exceed X cells, and in a policing circuit discarding input cells violating this contract, the VPI of the cell arriving at the input is
A means for identifying a number, an up / down counter for adding and calculating each time the number is identified by the identification means, and a shift register for providing a signal to a subtraction calculation input of the up / down counter after a T cell time identified by the identification means. Means for sending out a discard signal each time the count value of the up / down counter exceeds X, a plurality of VPI numbers at one input for each of a plurality of VPI numbers. A FIFO holding the VPI number along with the T cell time, a threshold table holding a threshold X corresponding to the VPI number,
, And a DB circuit having a logic processing unit that determines whether or not to discard by referring to the threshold value table.

[0011]

The individual processing circuits for the types of VPs are prepared, and the incoming VPs are distributed to the individual processing circuits by their VPI numbers. Each individual processing circuit is provided with a register for storing a VPI number assigned to the individual processing circuit.
When the number arrives, the input information is taken in, the up / down counter is added, and the number is input to the shift register. However, a VP smaller than the specified capacity is processed in the DB circuit.

The shift register of this individual processing circuit functions as if it were a "measuring cell". This shift register stores the input information of the time corresponding to the maximum cell time contracted for each VP. The VP overflowing there is discarded as exceeding the contract amount. The input information before the maximum cell time in the shift register is referred to, and the VP
If there is the input information, the up / down counter is decremented.
That is, if one VP comes out after the maximum cell time, the up / down counter is decremented by "1". Then, there is a space for one VP in the shift register, which is a “measuring cell”, and there is room for receiving a new VP. In this way, the number of VPs within the maximum cell time is managed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction of an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an overall configuration diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram of the individual processing circuit.

According to the present invention, there is a contract that the cell arriving at the input during the T cell time does not exceed the X cell for each VPI, and the policing circuit discarding the input cell violating this contract arrives at the input. A comparator 6 and a register 5 as means for identifying the VPI number of a cell, and an up / down counter 9 for adding and calculating each time the identification is made by the identification means
A shift register 10 for providing a signal to the subtraction calculation input of the up / down counter 9 after the T cell time identified by the identification means, and a means for sending a discard signal every time the count value of the up / down counter 9 exceeds X. , The individual processing circuit 2 including the comparator 8 and the register 7 is provided for each of a plurality of VPI numbers at one input.
A FIFO circuit for holding the cell arriving at the input together with its VPI number over a T cell time, a threshold table for holding a threshold value X corresponding to the VPI number,
A logic processing unit which receives the output of the IFO circuit as an input and refers to the threshold value table to determine the presence or absence of discard.
It is characterized by including the B circuit 1 together.

Next, the operation of the apparatus according to the embodiment of the present invention will be described.

As shown in FIG. 1, the discard instruction signals of the DB circuit 1 and the individual processing circuit 2 are input to a discard unit 3, and the discard unit 3 discards the input cells. FIG. 2 shows the configuration of each individual processing circuit 2 of FIG. The VPI number of the input ATM cell is input to a plurality of individual processing circuits 2. In each individual processing circuit 2, the VPI number of the processing target VP is set in the register 5 in advance, and the target VP in the T cell time is set.
Is set in the register 7 as the threshold value for discard determination. Similarly, the T value is set in the register 7.
The comparator 6 compares the input VPI with the processing target VPI.
When the VPIs match, a match signal is output to the up / down counter 9. The shift register 10 holds input information indicating whether or not the VP has been input for a maximum T cell time. The maximum T time is the T value of the maximum length of the target VP item. The selector 11 inputs the time series input information of the VP from the register 7, selects the information before the T cell time in the shift register 10, and outputs the subtraction signal 4 when there is the VP input before the T cell time. Output.

The up / down counter 9 is cleared to "0" at the time of initialization, and thereafter receives a coincidence signal from the comparator 6 and adds "+1" to the counter value when the VP to be processed is input, and increases the counter value by T cell time. Subtraction signal 4 indicating VP input to be processed
Subtracts "-1" from the counter value. The upper limit of the counter value is X, and “+1” addition is stopped while “counter value = X”. The value of the up / down counter 9 is compared with the register 7 of the X value by the comparator 8, and if they match, a discard instruction signal is output.

Items of policing range from high capacity to low capacity. V corresponding to items of a certain capacity or more
The number of P is particularly CBR (Conti) when the capacity is V.
Numeric Bit Rate), the number of VPs is approximated by the equation: interface speed 数 V + β. (Β is considered to be a margin for making this approximation a safe side.) By having the individual processing circuits 2 for the number of VPs, all the items having the capacity V or more are individually processed.
Can be realized. DB circuit 1 only for items smaller than capacity V
Process by Thereby, the number of items processed by the DB circuit 1 can be reduced.

[0019]

By realizing the processing of VP items having a certain capacity or more by the individual processing circuit, the access speed of the memory of the DB circuit is reduced, the load is reduced, and high-speed processing can be supported. At the same time, the increase in hardware scale can be suppressed.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of an individual processing circuit.

FIG. 3 is a block diagram of a conventional DB circuit.

FIG. 4 is a diagram showing a state of a FIFO in a DB circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 DB circuit 2 Individual processing circuit 3 Discard part 4 Subtraction signal 5 Register 6 Comparator 7 Register 8 Comparator 9 Up / down counter 10 Shift register 11 Selector 20 Selector 21, 22 Memory 23 Counter 24 Logical processing part 25 Memory 26 Count memory 27 Write address 28 FIFO 30 VPI information 31 VPI information size 32 Number of VPI information 33 Write address 34 Read address 35 Number of items

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoichi Sato 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-4-25255 (JP, A) JP-A-Hei 2-90834 (JP, A) JP-A-4-177942 (JP, A) JP-A-5-260069 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/28 H04L 12/56

Claims (1)

(57) [Claims] 1. A contract is made for each VPI that a cell arriving at the input during the T cell time does not exceed X cells. In a policing circuit for discarding an input cell violating this contract, a cell arriving at the input is discarded. Together with its VPI number
FIFO circuit and VPI number pair
A threshold value table for holding a threshold value X;
Using the output of the IFO circuit as an input,
DB including a logic processing unit that determines whether or not to discard by referring to
(Dangerous Bridge) Circuit (1) must not exceed a certain capacity V
It provided for have VPI number, means for identifying the VPI number of cells arriving at the input
(5, 6) and added each time it is identified by this identification means
An up / down counter (9) to be calculated and said identification
After the T cell time identified by the means,
Shift register (1
0) and the coefficient value of the up / down counter exceeds X
Means (7, 8) for sending a discard signal every time
Processing circuit (2) for a VPI number of a certain capacity V or more
A policing circuit provided separately .