JP2918777B2 - Repeater for serial transmission line - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial transmission repeater interposed in a transmission line for transmitting a digital signal composed of a plurality of pulse groups having different voltage levels.

[0002]

2. Description of the Related Art For example, in various industrial machines and robots, it is necessary to connect a large number of sensors and actuators to a controller and perform data transmission between them. At this time, as a data transmission method between the controller as the master unit and the sensors and actuators as the terminal units, it is general to adopt a serial transmission method that can reduce the number of cables and transmit digital signals. is there.

When the length of the transmission line connecting the master unit and each terminal becomes longer, the digital signal transmitted due to the line resistance and line capacity of the transmission line is attenuated halfway and cannot transmit data. I will.
In order to prevent this, a technique has been developed in which a repeater having an amplifier circuit is provided in the middle of a transmission line to amplify the attenuated digital signal again.

A repeater of this type is disclosed in Japanese Patent Laid-Open No. 55-5 / 55.
A repeater disclosed in Japanese Patent Publication No. 9521 is known, and a circuit configuration of the repeater is shown in FIG. In the repeater,
A first transmission line 1 for transmitting a digital signal from a first terminal connected to the left side in the figure to a second terminal connected to the right side in the figure, and a digital signal from the second terminal to the first terminal. Drive NAND gates 3 and 4 having an amplifying function are provided on the output side of the first transmission line 1 and the second transmission line 2. Furthermore, the invalidation constituted by the NAND gates 5 and 6 prevents the digital signals output from the driving NAND gates 3 and 4 from returning to the side where the digital signals are input via the other transmission path. The circuit 7 is provided, and the operation of the driving NAND gates 3 and 4 of the other transmission path can be invalidated.

In this configuration, when a digital signal is output from, for example, the first terminal on the left side, the signal is amplified by the driving NAND gate 3 provided on the first transmission line 1, and is amplified from the input / output terminal 9 to the second terminal on the right side. Output to the terminal.
At this time, since the driving NAND gate 4 provided in the second transmission path 2 has been invalidated by the invalidation circuit 7,
The signal output from the driving NAND gate 3 does not return to the left input / output terminal 8 via the second transmission path 2.

[0006]

By the way, in a serial transmission line, for example, a clock pulse group 10 and a data pulse group 11 are provided between terminals as shown in FIG. In some cases, a digital signal composed of three values of “high level” is transmitted. In this case, the repeater having the above configuration cannot amplify the attenuated digital signal composed of the three values and restore the digital signal to the original state. Because
The driving NAND gates 3 and 4, which are amplification circuits, perform a switching operation between the saturation region and the cutoff region of the transistor. Therefore, the output thereof has only two values, that is, low level and high level. This is because it cannot be restored and output.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital signal comprising a plurality of types of pulse groups having different voltage levels so as to be able to amplify without error and to transmit data reliably. It is an object of the present invention to provide a repeater for a serial transmission line that can perform the above.

[0008]

[0009]

In order to achieve the above object, a serial transmission repeater according to the present invention comprises a group of data pulses for transmitting information bidirectionally between terminals, and a group of data pulses for voltage transmission. A1 to A3 are provided on a line from one terminal to the other terminal side in the repeater, which is interposed in a bidirectional transmission line for transmitting a digital signal composed of different clock pulse groups. A characteristic feature is that the following B1 and B2 are provided on the line from the other terminal to the one terminal side, and the following C1 and C2 invalidating means are provided.

A1: A signal separation circuit provided on the one terminal side for separating a digital signal into a data pulse group and a clock pulse group based on a voltage level. A2: Data pulse separated by the signal separation circuit. A3: Amplifying circuit for amplifying the group and outputting it to the other terminal side of the transmission line A3: Amplifying circuit for amplifying the clock pulse group separated by the signal separating circuit and outputting it to the other terminal side of the transmission line B1: B2: an amplifier circuit that amplifies the data pulse group separated by the signal separation circuit and outputs the digital signal group to the transmission line. C1: A line from the one terminal to the other terminal is connected to a signal separating circuit of B1. Invalidating means for invalidating based on the separated data pulse C2: Invalidating for invalidating the line from the other terminal to the one terminal based on the data pulse separated by the signal separating circuit of A1. means

[0011]

[0012]

The operation of the repeater according to claim 1 will be described with reference to FIG. The serial transmission line in which this repeater is interposed performs bidirectional transmission. From the terminal connected to the left side of the figure, a data pulse group and a clock having a different voltage level from the data pulse group are output. A ternary digital signal including a pulse group is output, and only the data pulse group is output from the terminal connected to the right side to the left terminal in synchronization with the clock pulse.

When a ternary digital signal as shown in FIG. 5A is output from the terminal on the left side, first, a clock pulse group shown in FIG. ) Are separated into data pulse groups. The separated clock pulse group is amplified by the amplifier circuit A3 and output to the right terminal, and the data pulse group is amplified by the amplifier circuit A2 and output to the right terminal.

In the case where the right terminal receives the digital signal and outputs a data pulse group to the left terminal while synchronizing with the clock pulse group, the clock pulse is transmitted to the line from the right terminal to the left terminal. A ternary digital signal including a group and a data pulse group output from the right terminal is input. Then, only the data pulse group is separated by the signal separation circuit B1, and the separated data pulse group is amplified by the amplifier circuit B2 and output to the left terminal.

On the other hand, the invalidating means C2 comprises a signal separating circuit A
The function of the line from the right terminal to the left terminal is disabled based on the data pulse separated by 1. This prevents a data pulse group output from the amplifier circuit A2 to the right terminal from returning to the left terminal side via the line from the right terminal to the left terminal. Similarly, when a data pulse group is output from the amplifier circuit B2 to the left terminal, the data pulse group is prevented from returning to the right terminal side through the line from the left terminal to the right terminal. The line from the left terminal to the right terminal is invalidated by the invalidating means C1 based on the data pulse group.

[0016]

As described above, according to the present invention, while the digital signal is being output to the other terminal, the transmission path from the other terminal to the one terminal is invalidated,
While the digital signal is being output to one terminal, the invalidation means for invalidating the transmission path from one terminal to the other terminal is provided, so that the digital signal composed of a plurality of pulse groups is provided on the bidirectional transmission path. Even if the signal is transmitted, the output signal does not return along the other line, and even if the transmission line is long, it is possible to perform reliable serial transmission without attenuating the signal. Is obtained.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 3, the serial transmission line repeater 21 of the present embodiment is a serial transmission line connecting a master unit 22 which is a controller of an industrial machine and terminal units 23a to 23d which are sensors and actuators. 24, and amplifies the transmitted signal.

FIG. 1 shows a specific circuit configuration of this embodiment.
The first input / output terminal 25 located on the master unit side
The second input / output terminal 26 on the opposite side is connected to the transmission line 24 on the master unit 22 side, and is connected to the transmission line 24 on the terminal units 23c and 23d located far away. The first and second input / output terminals 25 and 26 are internally divided into a first line 27 and a second line 28,
The first line 27 is for transmitting digital signals to the terminal units 23c and 23d located far from the master unit 22, and the second line 28 is for transmitting the master signal from the terminal units 23c and 23d located far. This is for transmitting a digital signal to the unit 22 side.

The first line 27 further includes a clock line 2
9 and a data line 30, and a clock line 29 has a Zener diode 3 having a Zener voltage of 18 V.
1 is inserted with the cathode positioned on the first input / output terminal 25 side, and a Zener diode 32 with a Zener voltage of 6 V is also placed on the data line 30 with the cathode positioned on the first input / output terminal 25 side in the same manner as described above. Has been inserted. As a result, a signal separating circuit 33 is formed. When a voltage of 18 V or more is applied to the first input / output terminal 25, a reverse current flows through the Zener diodes 31 and 32, and between 6 V and 18 V, the Zener diode 32 The reverse current flows only through the zener diodes 31 and 32 if the voltage is 6 V or less.

The Zener diode 31 has an inverting gate 34
Is connected to the base of a transistor 35 corresponding to an amplifier circuit. The transistor 35 is of a PNP junction type, the emitter is connected to a 24 V power supply, and the collector is connected to the second input / output terminal 26. And
When the base current starts flowing, the transistor 35 switches from the cutoff state to the saturation state (turns on), and the collector current starts flowing, and the second input / output terminal 26 is set to 24V. When the base current does not flow, the transistor 35 is off.

On the other hand, the Zener diode 32 inserted in the data line 30 is connected to the base of the transistor 37 via the NOR gate 36. The transistor 37 has an NPN junction type, an emitter connected to the ground, and a collector connected to the second input / output terminal 26. Then, the transistor 37 switches (turns on) from the cutoff region to the saturation region due to the flow of the base current, and sets the second input / output terminal 26 to 0V. If no base current flows, the transistor 37 remains off.

Further, a constant current source 38 is connected to the second input / output terminal 26 side of the first line 27 via a diode 39, and a second input / output is supplied from a 12V power supply via the diode 39. A constant current flows through the terminal 26, and the second input / output terminal 26 is maintained at 12V when the transistors 35 and 37 are shut off.

On the other hand, the second line 28 is provided with a signal separating circuit 41 comprising a Zener diode 40 on the side of the second input / output terminal 26, and the Zener diode 40 has a cathode connected to the second input / output terminal 26. Is inserted into the second line 28 so as to be located on the side. The Zener diode 40 has a Zener voltage of 6 V. When a voltage of 6 V or more is applied to the second input / output terminal 26, a reverse current flows, and
If it is less than V, no reverse current flows.

The Zener diode 40 has a NOR gate 42
Is connected to the base of the transistor 43 via the.
The transistor 43 is an NPN junction type, the emitter is connected to the ground, and the collector is connected to the first input / output terminal 2.
When the base current flows, the switch operation (ON operation) is performed from the cutoff region to the saturation region, and the first input / output terminal 25 is set to 0V. If the base current does not flow, the transistor 43 remains off.

The output side of the NOR gate 36 is connected to one input side of a NOR gate 42 via an off-delay circuit 44, and the output side of the NOR gate 42 is connected to one side of the NOR gate 36 via an off-delay circuit 45. Connected to input side. As a result, an invalidating circuit 46 is formed, and when the output of the NOR gate 36 is at the high level, the output of the NOR gate 42 is forcibly set to the low level regardless of the other input, and the transistor 43 is turned off. NOR gate 36 at high level
Is forced to the low level regardless of the other input, and the transistor 37 is turned off.

The off-delay circuit 44 delays the time when one input side of the NOR gate 42 rises after the output of the NOR gate 36 rises from a low level to a high level. In other words, it is provided to release the forcibly cut off state of the transistor 43 after the transistor 37 in the output state is completely cut off. The off-delay circuit 45 also delays the rise time of one input side of the NOR gate 36 in order to release the forced shut-off state of the transistor 37 after the transistor 43 in the output state is completely shut off as described above. It is provided in.

Next, the operation of the present embodiment will be described.
From the master unit 22, each terminal unit 23a
To 23d, and a clock pulse group for synchronizing the data pulse group with a different voltage level from the data pulse group.
A digital signal of the value is output. This digital signal is composed of a low level, an intermediate level, and a high level, as shown in FIG. 5A. A high level pulse group functions as a clock pulse group, and a pulse group composed of the low level and the intermediate level is a data pulse group. Function as

Each of the terminal units 23a to 23a
d may also send information to the master unit 22.
In this case, the clock pulse group is received, and the data pulse group is output to the master unit 22 while synchronizing with the clock pulse group. In this case as well, FIG.
It becomes a ternary digital signal as shown in FIG. However, in the present embodiment, the circuit operation differs between the case where the signal is transmitted from the master unit 22 to the terminal units 23c and 23d on the downstream side of the repeater 21 and the case where the signal is transmitted on the contrary. Therefore, the case will be described separately.

<Transmission from Master Unit 22 to Terminal Units 23c and 23d> In this case, since the master unit 22 outputs a clock pulse group and a data pulse group, a ternary digital signal is output to the transmission line 24. Therefore, the voltage waveform of the first input / output terminal 25 of the repeater 21 is, for example, the X region (the left half side of the waveform diagram) in FIG.
It becomes as shown in. Then, in the repeater 21, 18 V or more is set to a high level by the signal separation circuit 33, and 6V to 1V.
A clock pulse group that sets a low level between 8V and 6V
It is separated into a data pulse group A in which .about.18 V is high level and 6 V or less is low level. When the clock pulse is at the high level, the transistor 35 is turned on to output 24 V to the second input / output terminal 26. When the data pulse is at the low level, the transistor 37 is turned on to output 0 V. When the data pulse is low and the data pulse is high, the constant current source 38
Output 2V. As a result, the attenuated ternary digital signal is amplified to a ternary digital signal having a low level of 0 V, an intermediate level of 12 V, and a high level of 24 V, and the terminal unit 23 c located far from the second input / output terminal 26. 23d.

Here, the transistor 4 is connected to the second line 28.
3, the signal supplied to the second input / output terminal 26 is amplified and returned to the first input / output terminal 25 side. However, when the transistor 37 is in the output state, the off-delay circuit 44
, The invalid signal A (high level) is input to one input side of the NOR gate 42, the output of which becomes low level, and the transistor 43 is forcibly cut off. The signal does not return to the first input / output terminal 25.

This circuit operation is performed by the master unit 2
2 outputs a clock pulse group and a data pulse group from the master unit 22 and outputs only the clock pulse group.
The same applies when the terminal units 23a and 23b located on the side output the data pulse group in synchronization with the clock pulse group.

<Transmission from Terminal Units 23c and 23d to Master Unit 22> In this case, the master unit 22 outputs only the clock pulse group to the transmission line 24, and the terminal unit located farther than the repeater 21 23c and 23d output the data pulse group to the transmission line 24 while synchronizing with the clock pulse group.

Then, the clock pulse group supplied from the master unit 22 to the first input / output terminal 25 is separated by the signal separation circuit 33 in the same manner as described above, and the transistor 3
5, the clock pulse group is output from the second input / output terminal 26 to the terminal units 23c and 23d far away. On the other hand, since each of the terminal units 23c and 23d outputs a data pulse group to the transmission line 24 in synchronization with the clock pulse group, the second
The potential of the input / output terminal 26 also becomes a ternary digital signal in which a clock pulse group and a data pulse group are mixed, as shown in, for example, the Y region (right half of the waveform diagram) in FIG.

The ternary digital signal is supplied to the second line 28
Is input to the signal separation circuit 41 provided in
The signal pulse separation circuit 41 discriminates 6 V or less as a low level and others as a high level, and separates the data pulse group B shown in FIG. When this data pulse is at the low level, the transistor 4 is connected via the NOR gate 42 on the condition that the output of the off-delay circuit 44 is at the low level.
3 is turned on, the first input / output terminal 25 becomes 0V, and when the data pulse is at a high level, the output side of the NOR gate 42 is at a low level and the transistor 43 is cut off.

Here also, the data line 30 of the first line 27
Is provided with the transistor 37, there is a disadvantage that a signal given to the first input / output terminal 25 is amplified and returned to the second input / output terminal 26 side. However, when the transistor 43 is in the output state, the invalid signal B (high level) is input to one input side of the NOR gate 36 via the off-delay circuit 45, and its output becomes low level, and the transistor 37 is forcibly forced. Since the signal is cut off, the signal does not return to the second input / output terminal 26 via the data line 30 of the first line 27.

According to the above configuration, a data pulse group and a clock pulse group having different voltage levels from the data pulse group are formed.
Even when a digital signal of a value is transmitted, the signal is separated into the original data pulse group and the clock pulse group by the signal separation circuit 33, and then amplified by the transistors 35 and 37, respectively. Also, the serial transmission line 24 through which the digital signal is transmitted can be used with the repeater of the present embodiment interposed. Therefore,
Even if the transmission line 24 for transmitting the ternary digital signal is long, the signal is not attenuated in the middle, and serial transmission can be reliably performed between the master unit 22 and each of the terminal units 23a to 23d.

Further, when a ternary digital signal is transmitted bidirectionally, a nullification circuit 46 is provided so that the digital signal is input to one of the lines, for example, the first line 27, while the second line is connected to the second line. Transistor 43 provided in 28
Is cut off, it is possible to prevent a data pulse group output from the first line 27 from returning to the first input / output terminal 25 via the second line 28. . Therefore, even when a digital signal is transmitted bidirectionally, the repeater of this embodiment can be used, and serial transmission can be reliably performed while preventing attenuation of the transmitted digital signal.

In the above embodiment, the signal separation circuit 33
Used to separate a ternary digital signal composed of a data pulse group and a clock pulse group. However, when a digital signal composed of three or more types of pulse groups having different voltage levels is transmitted, this is separated. For this purpose, for example, three or more Zener diodes may be provided and separated into individual pulse groups. As described above, even if various modifications are made to the present embodiment, it is needless to say that it is included in the concept of “signal separation circuit” in the claims of the present application.

[0040]

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an entire embodiment of the present invention.

FIG. 2 is a waveform chart showing a waveform in each circuit.

FIG. 3 Terminal connection diagram

FIG. 4 is a corresponding diagram showing the configuration of the invention described in claim 1;

FIG. 5 is a waveform diagram showing a ternary digital signal.

FIG. 6 is a circuit diagram showing a conventional repeater.

[Explanation of symbols]

22 Master unit 23a-23c Terminal unit 24 Serial transmission path 27 First transmission path 28 Second transmission path 33, 41 Signal separation circuit (A1, B1) 35, 37, 43 Transistor (amplification) Circuit A3, A
2, B2) 46 invalidating circuit (invalidating means C1, C2)

Continuation of the front page (56) References JP-A-1-93229 (JP, A) JP-A-57-143957 (JP, A) JP-A-64-89839 (JP, A) JP-A-56-157153 (JP, A) JP-A-1-93229 (JP, A) JP-A-56-96562 (JP, A) JP-A-53-21509 (JP, A) JP-A-2-306738 (JP, A) 62-3141 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 25/00-25/66 G08C 19/28 H04B 3/36 H04L 5/00-5/18 H04L 12 / 40

Claims (1)

(57) [Claims] 1. A repeater interposed in a bidirectional transmission line for transmitting a digital signal consisting of a data pulse group for transmitting information bidirectionally between terminals and a clock pulse group having different voltage levels. A1 to A3 are provided on a line from one terminal to the other terminal side in the repeater, and B1 and B2 below are provided on a line from the other terminal to the one terminal side. A repeater for a bidirectional serial transmission path, wherein the repeater is provided with the following C1 and C2 invalidating means. A1: A signal separation circuit provided on the one terminal side for separating the digital signal into a data pulse group and a clock pulse group based on a voltage level A2: The data pulse group separated by the signal separation circuit A3: an amplifier circuit that amplifies the clock pulse group and outputs the clock pulse group separated by the signal separation circuit to the other terminal side of the transmission line. A signal separation circuit provided on the other terminal side for separating the digital signal into a data pulse group based on a voltage level; and B2: amplifies the data pulse group separated by the signal separation circuit and amplifies the transmission line. C1: a line from the one terminal to the other terminal Invalidating means C2 for invalidating based on the data pulse separated by the signal separation circuit of B1; a line from the other terminal to the one terminal side is converted into a data pulse separated by the signal separation circuit of A1; Invalidation means to invalidate based on