JP2917901B2 - DCFL charge pump circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit for converting a digital signal into an analog output, and more particularly to a DCF constituted by a MESFET having a gate leak.
The present invention relates to a charge pump circuit suitable for application to an L circuit.

[0002]

2. Description of the Related Art GaAs (gallium arsenide) has a higher electron mobility than Si (silicon), is suitable for high-speed operation at low voltage, and has a frequency of GHz (gigahertz).
It is expected to be applied to systems that require order clocks.

At this time, since it is very difficult to configure a system by a method of distributing a high-speed clock between boards, a clock distributed from the board is usually multiplied in a chip to generate a clock on the order of GHz. Is generated.

As a clock multiplication method, a PLL (Ph
An ase-locked loop (phase-locked loop) circuit is generally used. The clock distributed from the board is input as a reference signal, and a voltage controlled oscillator (VC
O), the reference signal and the VCO output signal (or its divided signal) are converted into a digital signal obtained by comparing the frequency and phase to an analog voltage for controlling the oscillation frequency of the voltage controlled oscillator. A conversion circuit is included. As a circuit for converting this digital signal into an analog voltage signal, a charge pump circuit is usually used.

FIG. 6B shows a configuration of a charge pump circuit often used in a CMOS circuit. When a low-pass filter is connected to the output terminal OUT, the output terminal OU is output when the input IN1 is at a high level and the input IN2 is at a low level.
The power supply voltage appears at T and charges the filter. On the other hand, when the input IN1 is at a low level and the input IN2 is at a high level, the output terminal OUT is grounded and discharges the charge stored in the filter. For this reason, the amount of charge to the filter is determined by the time ratio of the high level and the low level of the inputs IN1 and IN2, and the smoothed signal is output as a voltage for controlling the voltage controlled oscillator. As described above, the charge pump circuit is used to convert a binary digital signal whose output is high level and low level into a continuous amount (analog signal).

[0006]

SUMMARY OF THE INVENTION A PLL circuit of GaAs
MESFET (Metal Semiconductor Field Effect Tra
nsistor), especially DCFL (Direct Coupled FET Logi)
In the case of the design in c), a charge pump circuit in which the enhancement mode FETs shown in FIG. 6A are vertically stacked is usually used.

This circuit is composed of a MOSFET (Metal Oxide
In the case of an FET having no gate leakage, such as a field effect transistor (MOS field effect transistor), there is no problem if the FET is used in a charge pump circuit of a PLL circuit. However, since the MESFET has a gate leak, if the power supply voltage is higher than the gate voltage of the MESFET at which the gate leaks, the PLL loop may be unstable.

As shown in FIG. 6C, a charge pump 63, a low-pass filter 64 to which the output (OUT) of the charge pump 63 is input, and a DCFL type output amplifier 65 to which the output of the low-pass filter 64 is input. FIG. 7 shows the result of charging and discharging the charge pump 63 with the power supply voltage set to 2 V for the conversion circuit. As shown in FIG. 7, the charging is completed faster than the discharging (the rising time at the time of charging is shorter than the falling time at the time of discharging).

[0009] This is because the start point of the input gate leakage of the output amplifier 65 is set to the voltage Vfamp = 1.2 V, and when charging is performed, the power supply voltage is 2 V and the charging is performed up to 1.2 V.
Rising fast. Conversely, when the battery is fully discharged, it falls at a CR time constant of the circuit, so it is slower than the charging.

As described above, when the charging time and the discharging time are significantly different, that is, when the asymmetry is large, the PLL
The transient response characteristics of the loop may become unstable. By using a power supply voltage smaller than the voltage Vfamp,
Although this problem can be avoided, the value of Vfamp is as low as about 1 V, and is not used much as a power supply voltage. In addition, in order to maintain consistency with the peripheral system, it is preferable to operate at the same power supply voltage as that of the peripheral system.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above circumstances, and has been made in consideration of the above circumstances, and has a charge pump circuit capable of reducing charge / discharge asymmetry in a charge pump output when the charge pump is driven by a power supply of a DCFL circuit. The purpose is to provide.

[0012]

In order to achieve the above object, the present invention relates to a method of connecting a high-potential power supply to a low-potential power supply in series, and connecting a gate electrode to first and second input terminals, respectively. In a charge pump circuit comprising first and second enhancement-type field-effect transistors and having a connection point between the first and second enhancement-type field-effect transistors as an output, a high-level potential of the output is clamped to a predetermined potential. means for, included in the first enhancement type field effect transistor side, to provide a charge pump circuit, characterized in that the charging and discharging characteristics of the output are set to be substantially symmetrical.

The present invention is characterized in that a clamp means is connected to the first input terminal.

Further, the present invention comprises a power supply voltage dividing means for dividing a voltage between a higher power supply and a lower power supply, and is connected in series to the lower power supply from an output of the power supply voltage dividing means. And a first and a second enhancement field-effect transistor having a gate electrode connected to the first and second input terminals, respectively, and a connection point between the first and second enhancement field-effect transistors is output. A charge pump circuit is provided.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the first embodiment of the present invention. As shown in FIG.
The charge pump circuit according to the embodiment
It is characterized in that a diode 4 is connected to 0. That is, referring to FIG. 1, the charge pump circuit has an enhancement-type field effect in which a drain electrode is connected to a power supply terminal, a gate electrode is connected to input terminal 10, and a source electrode is connected to output terminal (OUT) 8. A transistor (also referred to as “enhancement mode FET”) 1, an enhancement mode FET 2 having a drain electrode connected to the output terminal (OUT) 8, a gate electrode connected to the input terminal 11, and a source electrode connected to the ground terminal; A diode 4 whose anode electrode is connected to the input terminal 10 and whose cathode electrode is grounded. Thus, the high level of the input signal IN1 input to the input terminal 10 is fixed to the forward rising voltage Vf of the diode 4.

When the input signal IN1 is at a high level, the input terminal 1
Assuming that the input signal IN2 input to 1 goes low, the enhancement mode FET 1 is turned on,
The enhancement mode FET 2 is turned off. On this occasion,
A current flows into the low-pass filter (low-pass filter) 3 connected to the output terminal (OUT) 8 from the power supply terminal via the enhancement mode FET 1. It is almost determined by the resistance value of 6).

In the circuit shown in FIG. 1, when viewed from the enhancement mode FET 1, the source follower is in an operating state, and the voltage of the output terminal (OUT) 8 is
Are almost the same as the input signal voltage. That is, the enhancement mode FET 1 is driven at a high level whose gate voltage is clamped by the diode 4, and the low-pass filter 3 connected to the output terminal (OUT) 8
Since the input impedance is higher than that of the enhancement mode FET1, a clamped gate voltage appears at the output terminal (OUT) 8 instead of the voltage of the power supply terminal.

Therefore, if the voltage at the input terminal 10 is fixed at the forward voltage Vf of the diode, the output terminal (OU
T) 8 does not rise to the power supply voltage, and is fixed to a value of approximately Vf, and the output voltage appearing at the output terminal (FOUT) 9 of the filter 3 also rises only to Vf.

Note that the low-pass filter 3 shown in FIG. 1 shows an example of the configuration, and the charge pump circuit according to the present invention is of course not applied only to the low-pass filter having such a configuration.

FIG. 2 shows a circuit configuration according to a second embodiment of the present invention. Referring to FIG. 2, a power supply voltage dividing section 12 is provided which includes a DCFL high-level generating section and a source follower section for converting the DCFL into a low-impedance power supply. Is connected to the drain of the enhancement FET constituting the charge pump 13. The power supply voltage dividing section 12 includes a depletion mode FET 23 and an enhancement mode FE.
At T21, the power supply voltage is divided (to become a voltage Vf corresponding to the high level of DCFL), and this voltage (FET21, FET23)
The depletion mode FET 25 having a gate input of a common connection point potential of the gates of the gates has a source follower configuration.

More specifically, the power supply voltage dividing section 12 includes a depletion type field effect transistor ("depletion mode FET") having a drain electrode connected to a power supply terminal and a gate electrode and a source electrode connected to each other. 22) and the drain electrode is in the depletion mode F
An enhanced mode FET 21 having a source electrode connected to a ground terminal and a drain electrode connected to a power supply terminal;
Gate electrode and source electrode are enhanced mode FET21
A depletion mode FET 23 commonly connected to the gate electrode of the first mode, a depletion mode FET 25 having a drain electrode connected to the power supply terminal, and a gate electrode commonly connected to the gate electrode of the enhancement mode FET 21;
A drain electrode is connected to a source electrode of a depletion mode FET 25, and a gate electrode and a source electrode are each composed of a depletion mode FET 24 connected to a ground terminal. Are connected to the drain electrode of the enhancement mode FET 26 constituting

In this circuit, the charge pump 13
Are operated at a voltage Vf corresponding to the high level of DCFL.

In order to explain the embodiment of the present invention in more detail, as an embodiment of the present invention, a low-pass filter and an amplifier are added to the charge pump circuit according to the first embodiment described with reference to FIG. FIG. 3 shows the result of simulating the charge / discharge characteristics of the charge pump at a power supply voltage of 2 V with the connection (see FIG. 6C).

Unlike the simulation result of the conventional charge pump circuit shown in FIG. 7, the charging and discharging times are almost equal. This is because the drive voltage of the charge pump is not 2V, but Vf = 0.8V.

In this embodiment, the forward voltage V
Since f is used, even if the environmental temperature changes and the high level changes, the drive voltage of the charge pump also changes in accordance with this change, so that an effect of being stable against temperature changes (temperature compensation effect) can also be obtained. .

FIG. 4 shows another embodiment of the present invention.
1 is a block diagram showing a configuration of a PLL circuit using the charge pump circuit shown in FIG. This PLL circuit divides an output signal (fvco) of a voltage controlled oscillator (VCO) 39 whose oscillation frequency changes according to a control voltage by 64 by a 64 frequency divider 40, and outputs an output of the 64 frequency divider 40 and a reference signal (fvco). fref) is compared with the frequency-phase comparator 36, and the error signal from the frequency-phase comparator 36 is compared with the charge pump 1
3, a voltage signal is changed by the low-pass filter 3 and the amplifiers 37 and 38, and the voltage-controlled oscillator 39 is controlled so as to oscillate in synchronization with the reference signal (fref).

The PLL circuit shown in FIG.
FIG. 5B shows the result of a simulation in which a JFET (heterojunction field effect transistor) is used as an element and DCFL is used. FIG. 5 is a plot of the time response of the oscillation frequency.

FIG. 5A shows a time response characteristic of the oscillation frequency of a PLL circuit using a conventional charge pump circuit as a comparative example. In the conventional circuit, the frequency oscillates in a steady state and synchronization is not achieved.
As shown in (B), when the charge pump circuit according to the embodiment of the present invention is adopted, stable operation is performed at 2.56 GHz, which is 64 times the reference signal 40 MHz after about 1 μsec.

[0030]

As described above, according to the present invention,
The effect is obtained that the PLL circuit constituted by the DCFL circuit can be operated stably. This is because the charge and discharge times of the charge pump circuit that converts a digital signal, which is an error signal from the frequency phase comparator, into an analog signal are made substantially equal.

[Brief description of the drawings]

FIG. 1 is a diagram showing a charge pump circuit and a low-pass filter for smoothing a charge pump output according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a power supply voltage dividing circuit for a charge pump, a charge pump circuit, and a low-pass filter according to a second embodiment of the present invention.

FIG. 3 is a diagram for explaining an example of the present invention, and is a diagram showing a simulation result of charge / discharge characteristics when the charge pump circuit according to the first embodiment of the present invention is used.

FIG. 4 is a diagram for explaining an embodiment of the present invention, and a PLL configured using a charge pump circuit according to the present invention;
FIG. 2 is a block diagram of a circuit.

FIGS. 5A and 5B are diagrams for explaining an example of the present invention and a conventional example, wherein FIG. 5A is a PLL circuit using a conventional charge pump circuit, and FIG. 5B is an example of the present invention; Pertaining to P
The transient response of the LL circuit is calculated, and the voltage controlled oscillator (fvc) is calculated.
It is a figure showing the frequency response of o).

FIG. 6 is a diagram for explaining a conventional technique. (A) is a diagram showing an example in which a conventional charge pump circuit is configured by an enhancement mode FET. (B) is a diagram showing an example in which a conventional charge pump circuit is configured by CMOS.
(C) is a diagram showing a configuration example of a digital-analog conversion circuit including a low-pass filter and an amplifier for amplifying a filter output in the conventional charge pump circuit shown in (A).

FIG. 7 is a diagram showing a simulation result of charge / discharge characteristics of the conventional circuit of FIG. 6 (C).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1, 2 Enhancement mode FET 3 Low-pass filter 4 Diode 5, 6 Resistance 7 Capacitance 8 Output terminal (OUT) of charge-up circuit 9 Output terminal (FOUT) of low-pass filter 10, 11 Input terminal 12 Power supply voltage divider 13 Charge pump Circuit 21, 26 Enhanced mode FET 22, 23, 24, 25 Depletion mode FE
T 36 frequency phase comparator 37, 38 amplifier 39 voltage controlled oscillator 40 64 frequency divider

Claims (6)

(57) [Claims] A first enhancement-type field effect transistor which is connected in series from a high-order power supply to a low-order power supply and has a gate electrode connected to first and second input terminals, respectively; in the charge pump circuit to output the connection point of the first and second enhancement type field effect transistor, the means for clamping the high level potential of the output to a predetermined potential, the first enhancement type field effect transistor side A charge pump circuit, wherein the output has a substantially symmetric charge and discharge characteristic. 2. The input signal voltage is applied to the first input terminal.
2. A charge pump circuit according to claim 1, wherein a clamp means for clamping the level potential to a predetermined potential is connected. 3. A power supply voltage dividing means for dividing a voltage between a higher power supply and a lower power supply, wherein an output of the power supply voltage dividing means is connected to the lower power supply in series with the first power supply. And first and second enhancement-type field-effect transistors each having a gate electrode connected to a second input terminal and the first and second input terminals, respectively.
Wherein the connection point of the enhancement type field effect transistor is output. 4. An enhancement type field effect transistor having a drain electrode connected to a first power supply terminal, a gate electrode connected to a first input terminal, and a source electrode connected to an output terminal, and a drain electrode connected to the output terminal. An enhancement field-effect transistor having a gate electrode connected to the second input terminal, a source electrode connected to the second power supply terminal, an anode electrode connected to the first input terminal, and a cathode connected to the first input terminal. A charge pump circuit comprising: a diode connected to the second power supply terminal; 5. A first depletion type field effect transistor having a drain electrode connected to a first power supply terminal, a gate electrode and a source electrode connected to each other at a first node, and a drain electrode connected to the first power supply terminal. A first enhancement-type field effect transistor connected to the first node and a source electrode connected to a second power supply terminal; a drain electrode connected to the first power supply terminal; and a gate electrode and a source electrode connected to the first power supply terminal. A second depletion-type field-effect transistor commonly connected at a second node to a gate electrode of the first enhancement-type field-effect transistor; a drain electrode connected to the first power supply terminal; A third depletion type field effect transistor connected to the second node; and a drain electrode connected to the third depletion type electric field transistor. A third node connected to the source electrode of the field effect transistor;
A fourth depletion-type field-effect transistor having a gate electrode and a source electrode connected to a second power supply terminal; a drain electrode connected to the third node; and a gate electrode connected to the first input terminal. A second enhancement field effect transistor having a source electrode connected to the output terminal, a drain electrode connected to the output terminal, a gate electrode connected to the second input terminal, and a source electrode connected to the second power terminal. And a third enhancement type field effect transistor connected to the charge pump circuit. 6. A charge pump circuit according to claim 1, wherein the charge pump circuit converts a digital output signal of a phase frequency comparison circuit into an analog output, and the output of the charge pump circuit is a filter. Characterized in that the PLL circuit is supplied as a control voltage signal to a voltage control transmitter via the control circuit.