JP2916365B2 - CCD driving method and CCD driving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a device for driving a CCD in an image reading apparatus using a CCD such as an image scanner.

When the driving frequency of a CCD increases, the CCD
The timing margin between the drive pulse clock, reset pulse, and sample and hold pulse is reduced,
Due to the variation of D, the operating characteristics of the CCD sensor may be significantly reduced. According to the present invention, an optimal timing position of a reset pulse and a sample hold pulse with respect to a clock is automatically determined and operated for each CCD.

[0003]

2. Description of the Related Art FIG. 5 shows a configuration of a CCD driving device in a conventional image scanner.
Is a system clock source, 2 is a multi-stage delay circuit, 3 is a CCD
Drive clock control signal, 4 is a timing generator,
Reference numeral 5 denotes a CCD, 6 denotes an analog processing circuit, and 7 denotes an A / D converter.

A system clock source 1 generates a system clock used as a pixel clock (or a bit clock) and applies it to a multi-stage delay circuit 2 and a timing generator 4. Timing generator 4 is P
A clock φC for driving the CCD constituted by a ROM
K, patterns of timing signals of a reset pulse φRS and a sample hold pulse φSP are stored. These timing signals are exemplified in FIG. 6, for example. The multi-stage delay circuit 2 delays the system clock into a plurality of stages and outputs the delayed system clock. The delayed system clock and the original system clock are both applied to the PROM of the timing generator 4 as a scan address, and under the control of the CCD drive clock control signal 3, the stored timing signal pattern φC
K, φRS, and φSP are read out in parallel and continuously in time series, and are applied to the CCD 5. As a result, the CCD 5 operates, and an image signal is output and input to the analog processing circuit 6.

[0005] The analog processing circuit 6 has an AGC function for smoothing an input image signal for a relatively long period of time and automatically controlling the gain of the amplifier based on the level, and performs level correction of the image signal. The level-corrected image signal is input to the A / D converter 7, where it is converted into digital signal format multi-value data and output.

In the conventional device shown in FIG. 5, the pattern of each timing signal stored in the timing generator 4 is fixed, and the timing relationship between the signals is also fixed. FIG. 6A is a signal waveform diagram when the CCD drive frequency is low, and the margin between the signals indicated by A, B, and C in the figure does not change for all devices. FIG. 6B is a signal waveform diagram when the CCD drive frequency is doubled using the same timing generator 4. As compared with FIG. 6A, the time axis is compressed to 、, and the margins A ′, B ′, and C ′ are reduced to １ ／.

Since the timing signal varies in delay amount depending on environmental conditions such as the manufacturing lot of the element and the temperature, when the CCD driving frequency is increased as shown in FIG. It becomes more severe, making it difficult to obtain a sufficient CCD output level.

[0008] (a), (b), (c), (d) of FIG.
Shows an example of the sample hold output of the CCD at different inter-signal timings. (A) of FIG.
Shows a signal waveform in a standard state in which timing between signals is appropriately set. The output of the CCD based on the clock φCK falls slightly toward a potential determined according to the level of incident light. The sample and hold pulse φSP is terminated after the CCD output has almost reached the final level, and the reset pulse φRS is generated thereafter, so that a sample and hold output having a sufficient level can be obtained.

FIG. 7B shows a signal waveform in a state where φRS and φSP are shifted forward from the standard state in FIG. 7A. In this case, since φSP occurs before the CCD output is completely reduced, the CCD output level lower than the actual one is sampled and held. Also, φRS occurs while the CCD output reaches the final level and resets the CCD output. Therefore, even if φSP occurs a little further behind, it is not possible to sample and hold a sufficient CCD output level.

FIG. 7C shows a signal waveform when φRS is shifted backward beyond the period of φCK. in this case,
Since the next cycle is started before the CCD output is completely reset, and the first portion is reset, the CCD output level does not reflect the correct incident light level and becomes indefinite.

FIG. 7D shows a signal waveform in a state where φRS and φSP overlap each other. Since the CCD output exists only for a small portion of the sample hold period, almost no sample hold output is obtained. Although not shown in the figure, if the pulse width of φSP is too narrow, the reset cannot be performed sufficiently, and the CCD output level is saturated. If the pulse width of φSP is too narrow, the time required for the sample and hold operation is insufficient, and the hold capacitor cannot be charged to the CCD output level, so that the sample and hold output is hardly obtained.

As described above, in the conventional CCD driving method, when the driving frequency is increased, the operating characteristics of the sensor are likely to be deteriorated. Therefore, in many cases, timing adjustment is required. Therefore, there is a problem that the adjustment work load is large.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide means for automatically and optimally adjusting the timing of a CCD drive pulse.

[0014]

According to the present invention, the timing positions of the reset pulse and the sample hold pulse in the CCD drive pulse are made variable, and the timing positions of the reset pulse and the sample hold pulse with respect to the clock are variously changed. C for each pulse timing position
The multi-value data of the CD output is stored, and then the stored multi-value data is analyzed to determine a timing position that gives the best sensor operating characteristics.
A D drive pulse is generated to drive the CCD.

FIGS. 1A and 1B are diagrams showing the principle of the present invention. FIG. 1A shows the outline of a CCD driving method according to the present invention, and FIG. 1B shows the configuration of a CCD driving device according to the present invention. FIG. 1 (a)
In the CCD driving method of the present invention shown in
This is an optimal timing position detection stage executed at the time of device adjustment. The clock of the CCD drive pulse, the reset pulse,
For the sample hold pulse, the timing positions of the reset pulse and the sample hold pulse with respect to the clock are changed at a plurality of positions within a predetermined range, and multi-value data of the CCD output is stored for each changed timing position, and all the timing change positions are changed. When the multi-value data of the CCD output is stored, the multi-value data at each timing change position is analyzed, and the sensor operation characteristics such as the CCD output level, output linearity, and contrast transfer function CTF are determined and compared. The timing change position of the CCD drive pulse that gives the sensor operation characteristics of the above is determined as the optimum timing position.

Reference numeral 11 denotes data of the determined optimum timing position, which is data indicating the optimum timing position of the reset pulse and the sample hold pulse for the clock, and is stored in a nonvolatile memory or the like.

Reference numeral 12 denotes C executed during normal operation of the apparatus.
This is a CD drive control stage, in which the clock, the reset pulse, and the sample hold pulse are controlled using the data 11 at the optimum timing position determined by the optimum timing position detection stage 10 to drive the CCD.

Next, the C of the present invention shown in FIG.
In the CD driving device, reference numeral 13 denotes a system clock source, which is a pulse φCK ′, φRS ′, φS serving as a source of a clock φCK, a reset pulse φRS, and a sample-and-hold pulse φSP with a CCD driving frequency and a predetermined pulse width.
P 'respectively.

Reference numeral 14 denotes a timing changing means which can switch the delay amount composed of multi-stage delay lines or the like to a plurality of stages. The input pulse φCK ′, φRS ′, φS
P 'is given the indicated delay, and φC
K, φRS and φSP are generated. For example, φCK '= φ
CK and φRS, φSP are margins A, B, C (A ′, B ′,
Various delay amounts are set for φRS ′ and φSP ′ so that C ′) takes various values, so that the timing position can be changed back and forth.

Reference numeral 15 denotes a CCD to be driven, which has variations in element characteristics. Reference numeral 16 denotes an A / D converter.
An analog image signal output from a CD is converted into digital multi-value data.

Reference numeral 17 denotes a multi-value data storage means,
The multi-value data of the CCD output collected for the stage for detecting the optimal timing position of the D drive pulse is stored in correspondence with the timing position set at that time.

Numeral 18 denotes a characteristic analyzing means, which issues an instruction to change the timing position of the CCD drive pulse to the timing changing means 14 when the apparatus is adjusted, and outputs φR to φCK.
Various timing positions of S and φSP are set in order and CC
D15 is driven, and the multi-value data output at that time is
The data is collected in the multilevel data storage unit 17 in association with the set timing position. Next, the collected multivalued data corresponding to each timing position is sequentially extracted, the sensor operation characteristics for each timing position are analyzed, the timing position that gives the best sensor operation characteristics is detected, and determined as the optimal timing position.

Reference numeral 19 denotes the determined optimum timing position data. Numeral 20 denotes a CCD drive control means, which sends φRS and φRS to the timing change means 14 using the previously determined optimum timing position data 19 during normal operation of the apparatus.
Indicate the timing position of SP, and select the optimal φCK, φR
S and φSP are generated and supplied to the CCD 15, and the CCD 1
5 operate with the best characteristics.

[0024]

By adopting the CCD driving method or the CCD driving device of the present invention, the optimal timing position of the CCD driving pulse is individually determined at the time of shipping adjustment or maintenance adjustment of the image reading device, and is set in the device. In the operating state, the CCD is driven using the CCD driving pulse at the optimal timing position, so that even if the characteristics of the CCD elements vary, optimal operations can be performed for each. These are all handled automatically.

[0025]

FIG. 2 is a block diagram of a CCD driving device according to one embodiment of the present invention. In order to make it easier to understand the correspondence between the configuration of FIG. 2 and the configuration of the conventional device of FIG. 5, common elements are denoted by the same reference numerals.

In FIG. 2, 1 is a system clock source,
5 is a CCD, 6 is an analog processing circuit, 7 is an A / D converter, 21 and 22 are multi-stage delay circuits using delay lines, 23 and 24 are selectors, 25 is M
PU, 26 is PROM, 27 is SRAM, 28 is E ² P
The ROM, 29 is a characteristic analysis program, 30 is a φRS timing position table, 31 is a φSP timing position table, 33 is a multi-value data file, and 34 is optimal timing position data. The PROM 26 also stores a CCD drive control program and the like, but is not shown.

The system clock source 1 generates pulses φCK ′ and φR having the same CCD drive frequency and a predetermined pulse width.
S ′ and φSP ′ are generated. φCK ', φRS', φS
P 'may occur at the same timing location. φCK ′ is directly supplied to the CCD 5 as φCK without delay.
RS 'and φSP' are multistage delay circuits 21 and 22, respectively.
Is input to

The delay circuit 21 is provided as shown in FIG.
, The input φRS 'timing position t₀Multiple stages
Delay to the floor, t_iT at intervals of Δt_iMTo t
_{i + M}ΦRS at 2M + 1 different timing positions up to
Generate in parallel. Similarly, the delay circuit 22 is provided as shown in FIG.
As shown in the figure, the timing position t of the input φSP '
₀Is delayed in multiple stages, and t_jT at intervals of Δt
_jNTo t_{j + N}Up to 2N + 1 different timing positions
Are generated in parallel. The values of Δt, M, and N are appropriate.
It is set to the right.

The selectors 23 and 24 are respectively connected to the MPU 2
5, any of these φRS and φSP at different timing positions is selected and applied to the CCD 5. As a result, φRS and φSP are as shown in FIG.
As shown in the figure, the timing can be arbitrarily shifted forward and backward with respect to the timing position t _{0 of} φCK with respect to the timing positions t _i and t _j , respectively.

The MPU 25 has a characteristic analysis program 2 stored in a PROM 26 used as a control memory.
Step 9 is executed to set the various timing positions of φRS and φSP in the selectors 23 and 24 and drive the CCD 5. Timing position table 3 for φRS and φSP
0 and 31 are used to develop a combination for setting different timing positions for φRS and φSP. At the time of detecting the optimum timing position, the CCD 5 is caused to read the white reference.

The output of the CCD 5 is subjected to AGC correction of the signal level in an analog processing circuit 6 and converted into digital multi-value data by an A / D converter 7. SRA
The M27 multi-value data file 33 is a file created by collecting multi-value data of the CCD output at different timing positions of φRS and φSP, which have reached the effective level, for example, for 100 dots at the center of the main scanning line. It is.

M executing the characteristic analysis program 29
After creating the multi-value data file 33, the PU 25 performs a characteristic analysis, determines an optimal timing position, and writes the optimal timing position data 34 to the E ² PROM 28.

At the time of actual operation, the MPU 25 executes a CCD drive control program (not shown), reads out the optimal timing position data 34 of the E ² PROM 28,
The timing positions of φRS and φSP are set to 3, 24. CCD driving pulses φCK, φRS, φSP based on the set optimal timing position are supplied to the CCD 5 and driven.

FIG. 4 is a detailed flowchart of the characteristic analysis program in the embodiment of the present invention. In step (1), a new timing position is set and the CCD is driven. In step (2), the analog processing circuit corrects the CCD output level by the AGC operation, and extracts the AGC control voltage at that time, that is, the gain control voltage of the amplifier required to correct the CCD output level.

In step (3), it is determined from the value of the AGC control voltage whether or not the CCD output level has reached a sufficient level. If the CCD output level is insufficient, the process returns to step (1), and another timing position is set again. If the CCD output level is sufficient, proceed to step (4).

In step (4), the power supply voltage is reduced by 5 in order to check the margin of the characteristic with respect to the fluctuation of the power supply voltage.
V ± 0.5V. In step (5), the AGC operation of the CCD output level is performed with the power supply voltage varied, and the AGC control voltage at that time is extracted.

In step (6), the CCD output level is checked from the AGC control voltage, and if the level is insufficient, the process returns to step (1) to change the timing position. If the level is sufficient, proceed to step (7).

In step (7), φC shown in FIG.
K, φRS, CCD output, φSP, margin A,
The timing positions of φRS and φSP are changed so that B and C become smaller.

In step (8), the AGC operation for the CCD output level is performed, and the AGC control voltage at that time is extracted. In step (9), margins A, B, C
Of the result of changing the timing position so that
Determine whether the CD output level is sufficient,
If not, the process returns to step (1) to set the timing position. If the level is sufficient, proceed to step (10).

In step (10), the multi-value data of the CCD output is stored in the multi-value data file of the memory. In step (11), the process returns to step (1) until the check of the CCD output level has been completed for all of the changeable timing positions, and if completed, proceeds to step (12).

In step (12), the multi-value data is analyzed. As an analysis method, a variance value, a CTF value, a level difference between odd and even bits and the like are obtained, and the sensor operation characteristics of the CCD are evaluated. Here, CTF is equivalent to MTF (modulation transfer function) used for evaluating the characteristics of the optical lens. When the maximum value of the cell output voltage of the CCD is V _max and the minimum value is V _min , CTF = ( V _max -V _min) is given by / (V _max -V _min), reduction of the Kotorasuto image, i.e. used as a measure of blurriness.

In step (13), the results of the analysis of the multi-value data are compared to determine the optimal timing position. In step (14), writes data determined optimum timing position in E ² PROM.

[0043]

According to the present invention, in an image reading apparatus using a CCD, it is possible to automatically adjust the timing of a CCD drive pulse for each apparatus. Particularly, when the CCD drive frequency is high, fine timing margin adjustment can be performed. It can be performed quickly and accurately without using humans, and effects such as improvement of image quality, reduction of man-hours, and reduction of cost can be obtained.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a CCD driving device according to one embodiment of the present invention.

FIG. 3 is an explanatory diagram of a timing position change using a delay circuit in the embodiment of the present invention.

FIG. 4 is a detailed flowchart of a characteristic analysis program in a program according to an embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional CCD driving device.

FIG. 6 is a signal waveform diagram of a CCD drive pulse.

FIG. 7 is a signal waveform diagram of an example in which the timing of a CCD drive pulse is inappropriate.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Optimum timing position detection stage 11 Optimum timing position data 12 CCD drive control stage 13 System clock source 14 Timing changing means 15 CCD 16 A / D converter 17 Multi-value data storage means 18 Characteristic analysis means 19 Optimal timing position data 20 CCD Drive control means

Claims (2)

(57) [Claims] 1. A CCD driving pulse comprising a clock, a reset pulse and a sample hold pulse is generated.
In the CCD driving method, the timing positions of the reset pulse and the sample hold pulse are changed within a predetermined range with respect to the clock, and the multi-valued CCD output is output for each changed timing position of the reset pulse and the sample hold pulse. The data is stored in the memory, the multi-valued data at each timing position of the reset pulse and the sample hold pulse stored in the memory is analyzed, and the sensor operation characteristics of the CCD at each timing position are obtained. Comparing the characteristics to determine the optimal reset pulse and sample and hold pulse timing positions; generating a reset pulse and a sample and hold pulse based on the determined optimal reset pulse and sample and hold pulse timing positions; A CCD driving method characterized by driving a CD to operate. 2. A CCD driving pulse comprising a clock, a reset pulse, and a sample hold pulse is generated.
A timing change means for changing each timing position of the reset pulse and the sample hold pulse within a predetermined range with respect to the clock, and a reset pulse and a sample hold pulse changed by the timing change means. Multi-level data storage means for storing multi-level data of the CCD output at various timing positions; and instructing the timing changing means to change the respective timing positions of the reset pulse and the sample hold within a predetermined range. Characteristic analysis means for analyzing the sensor operation characteristics of multi-valued data of the CCD output at various timing positions of the sample hold pulse, obtaining optimum timing positions of the reset pulse and the sample hold pulse, and storing the data. Instructs the timing changing means based on the data of the optimal timing location of the stored reset pulses and sample-and-hold pulse, generates a reset pulse and sample hold pulse in the optimum timing position, C
CCD drive control means for supplying to a CD a CCD drive control means.