JP2914978B2 - Semiconductor circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor circuit, particularly to a current source of a differential amplifier circuit, and by changing an operating current supplied to the semiconductor circuit according to the circuit operation. More specifically, the present invention relates to a semiconductor circuit which can operate at high speed with low power consumption.

[Conventional technology]

Conventionally, as a logic circuit including a bipolar transistor, for example, there is a current switch circuit (CML circuit), that is, a circuit that switches an emitter current to change a collector voltage. In order to avoid this, the bipolar transistor is operated in an unsaturated region. However, since a constant current always flows through the circuit, the operation speed is high, but there is a problem that power consumption is large. Therefore, in order to reduce power consumption, a circuit system has been proposed in which current consumption is switched between an operation period and a standby period (for example, Japanese Patent Publication No.
No. 3219).

FIG. 11 is a diagram showing a conventional circuit described in the above publication. This circuit uses a current control signal phi _1, current Sui Tutsi circuit Q _1, Q ₂ and Emitsutafuorowa circuit Q _4, Q ₅
Of the current sources Q ₃ , Q ₆ , and Q ₇ are controlled. I ₁ and I ₂ are input signals, O,
Is an output signal. When the potential of the current control signal phi ₁ is high, bipolar transistors Q _3, Q _6, Q ₇ and resistors R _3, R _4, R ₅
A predetermined current is passed through the three current sources formed by
Current control signal phi ₁ is at the low level, to turn off the three current sources. In this way, the circuit consumes current only during the operating period (ie, φ is high) and has zero current consumption during the standby period (ie, φ ₁ is low). The power can be reduced. Such a current control method is effective in reducing the power of the memory LSI or the logic LSI. Here, the current control signal phi ₁ is a signal generated by the internal circuit (BINV1) using either direct input signal, or it from the outside.

[Problems to be solved by the invention]

The prior art determines the on-current at phi ₁ potential, and to ensure the current off, but must be set at a constant potential relative to the GND elevation potential of phi ₁ regardless of the changes in V _CC It is not easy to realize this with only a bipolar circuit. In addition, in order to avoid saturation of Q ₃ , Q ₆ , and Q ₇ , the high potential cannot be made too high. But usually φ ₁
Since get large load capacitance for driving the plurality of the constant current source at the same time, tends to occur over sheet Ute and ringing phi ₁ of the pulse waveform, this is the current value and the output waveform zero load circuits, the effects Exert. For the above reasons, the pulse current source method has a problem in current stability of the load circuit.

An object of the present invention is to provide a stable operating current, a simple configuration,
An object of the present invention is to provide a current source with a current switch function.

[Means for Solving the Problems] According to the present invention, a current source of a semiconductor circuit controls a current value setting element for setting a value of a current supplied to the semiconductor circuit, and controls a current supplied to the semiconductor circuit. A switching MOS transistor, and the current value setting element and the switching MOS transistor are connected in series.

Further, according to the present invention, the current source includes a second current value setting element for setting a minute current value smaller than a current value supplied to the semiconductor circuit, and a minute current supplied to the semiconductor circuit. A second current supply unit having a structure in which a second switch MOS transistor to be controlled is connected in series is provided, and the second current supply unit is a switch MOS transistor that controls a current supplied to the semiconductor circuit. Before turning on, a small current is supplied to the semiconductor circuit.

Further, according to the present invention, the current source is configured to be particularly effective as a current source of a differential amplifier circuit.

Further, according to the present invention, in the current source, the current value setting element is configured by a MOS transistor, and the gate area of the switching MOS transistor is set smaller than the gate area of the MOS transistor configuring the current value setting element. Configuration.

According to the invention, in the current source, the current value setting element is constituted by a MOS transistor, and the value of gate width / gate length of the switching MOS transistor is determined by the gate width of the MOS transistor constituting the current value setting element. / Gate length is set to be larger than the value.

According to the invention, the current source is a switching MOS.
The circuit includes signal generation means for generating a signal for controlling on / off of the transistor, and voltage generation means for generating a constant voltage applied to the current value setting element regardless of whether the switching MOS transistor is on or off.

Further, according to the invention, the voltage generation means has at least one MOS transistor, connects a gate of the MOS transistor constituting the current value setting element and a gate of the MOS transistor in common, and has a gate width of the MOS transistor. And the gate width ratio of the MOS transistor forming the current value setting element is set to a predetermined current ratio.

[Action]

The above current source consists of a current value setting element and a switch MOS
Since the transistors are connected in series, each element can be optimized according to the function, and a stable current can be supplied to the semiconductor circuit.

In addition, by providing the second current supply means, a minute current is supplied even when the semiconductor circuit is in a standby state.
Circuit operation when the semiconductor circuit is switched from standby to operation can be performed at high speed.

The structure of the current source according to the present invention is particularly effective for supplying a stable current to the differential amplifier circuit.

By making the gate area of the switching MOS transistor smaller than the gate area of the MOS transistor functioning as the current value setting element, the load capacitance of the switching MOS transistor can be reduced, and the switching MO transistor can be reduced.
The switching operation of the S transistor can be performed at high speed.

Also, by making the value of the gate width / gate length of the switching MOS transistor larger than the value of the gate width / gate length of the MOS transistor constituting the current value setting element, the on-resistance of the switching MOS transistor is reduced. Therefore, from the viewpoint of the MOS transistors constituting the current value setting element, the switching MOS transistor can be regarded as a simple switching element, and the value of the current supplied to the semiconductor circuit can be set by the current value setting element. Become.

Further, the current source according to the present invention includes a signal generating means for generating a signal for controlling on / off of the switching MOS transistor, and a voltage generating means for generating a constant voltage applied to the current value setting element regardless of whether the switching MOS transistor is on or off. By providing the means, the current value setting element is controlled by turning on / off the switching MOS transistor. Therefore, it is not necessary to control the current value setting element on / off, and a constant voltage is applied by the voltage generation means. Just do it.

Further, the voltage generating means is configured to have a MOS transistor, the gate of the MOS transistor and the gate of the MOS transistor forming the current value setting element are connected in common, and the gate ratio is set to a predetermined current ratio. ,
It is possible to supply a current with a constant current ratio even if the gate dimensions vary.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 1 shows a first embodiment of the present invention, in which a current source is composed of switch MOS transistors M ₁ , M ₂ , M ₃ and current value setting MOS transistors M ₄ , M ₅ , M ₆ . The gate of the M _1, M _2, M ₃ is controlled by phi _1. When φ ₁ is at a high potential, M ₁ , M ₂ , and M ₃ are turned on, and when φ ₁ is at a low potential, they are turned off. Since the on-resistance ron of these MOSs is in an unsaturated state, It is expressed as increasing the high potential phi _1, by increasing the W / L, normal operating conditions (V _CC 5V), about the operating current 1 mA)
Then, ron can be set to several tens to several hundreds Ω, and when M ₁ , M ₂ , and M ₃ are compared with M ₄ , M ₅ , and M ₆ , they can be regarded as mere switch elements. The Taking low potential phi ₁ below V _T, it can be made zero current completely.

On the other hand, M ₄ , M ₅ and M ₆ saturate the MOS (V
_DS > V _GS −V _T ). The current of M ₄ , M ₅ , M ₆ is And is independent of the drain voltage. This current also depends on the W / L and V _T of _{M 4, M 5, M 6} , W, L, the variation ΔW of the absolute value of V _G, ΔL, ΔV _G, by taking larger than the [Delta] V _T Thus, the current accuracy can be improved. In this configuration, the operating current does not depend on the emitter potentials of Q ₁ , Q ₂ , Q ₄ , and Q ₅ .
The advantage of this configuration is that it operates as a switch of M ₁ , M ₂ , M ₃ and uses the minimum L allowed by the processing technology for these,
_This is a point that the load capacity seen from ₁ can be reduced. If M ₄ , M ₅ ,
If the switch and current value are to be set at the same time only with M ₁ , M ₂ , and M ₃ without M ₆ , the high potential of the drive pulse φ ₁ is set with high accuracy with reference to GND, and M ₁ , M 2 _2, M ₃ of the L and W
Needs to be increased from the viewpoint of current value and processing variation. This increases the gate capacitance of M _1, M _2, M ₃ as viewed from the phi _1, increasing the power consumption of the delay time and phi ₁ generator of phi _1. As described above, in the configuration of FIG.
₁ can be achieved at the same time as the operating current can be made more accurate.

The feature of the embodiment shown in FIG. 2 is that the current is not completely reduced to zero at the time of standby as compared with FIG. Standby is ▲ ▼ shed a small current determined by the high potential and becomes M _7, M _8, M ₉ is turned on M _10, M ₁₁ of the W / L and V _G. When phi ₁ during operation and this way has decreased to a high potential, 0, 0 or accelerate the voltage change, or when waiting for, thereby facilitating the design of the subsequent circuit the potential does not become a floating state. Since 0 and the potential during the standby are both high and equal, the sources of M ₈ and M ₉ may be connected and pulled by one MOSM ₁₁ . The W / L of M ₁₀ and M ₁₁ for passing a small current is M ₄ and M which determine the current during operation
_5, is set to be smaller than the W / L of M _6.

The current control pulse phi ₁ or ▲ ▼ method generation described in Figure 1-Figure 2, simply but may only level converting the multichip enable signal ▲ ▼ from the outside, as described below the pulse width There are ways to change it.

Figure 3 is an example of current control pulses phi ₁ or ▲ ▼ method generating mentioned first to Figure 2. (A) is a circuit configuration, (b) is a timing chart. ▲ ▼ is an input signal for switching between the operation of the chip and the standby time. It is assumed that the operation is at a low potential and the standby is at a high potential. ₁ phi Taking such construction of (a), ▲ ▼ is the pulse width t ₂ and ▲ ▼ the pulse width t ₁ can be set by the delay circuit (Delay) independently.
In this way, if the operating current is supplied only for a period that is truly necessary for the circuit, the average current can be further reduced.

FIG. 4 shows an example applied to the latch circuit of the present invention. FIG. 5 is an outline of the voltage and current waveforms. In this circuit, the current and the load resistance are switched in conjunction with each other. Load resistance is PM
Formed by OS, MP ₁ and MP ₂ is (are W / L small) large resistance, MP ₃ and MP ₄ is a small resistor (W / L is large). The W / L of M ₃ takes greater than W / L of the M _4, W / L of M ₆ and M ₁₀ also made larger than the W / L of M _8, M _12. When φ ₁ , ▲ ▼, φ ₂ change as shown in Fig. 5, φ ₁
During the high potential period t ₂ , the information of the inputs I ₁ and I ₂ is taken, and 0,
Output to In this case, M ₂ is turned off, Q _1, a large current flows from one of Q _2, to generate an output amplitude determined by the product of the small load resistance. Also, the emitter current is
Since a large current flows which is determined by M _6, M _10, this period entire circuit operates at a high speed. Then phi ₂ acts period t ₃ in a feedback circuit of the high potential, the output 0, one of Q _3, Q ₄ are turned on in response to. Current less determined by M ₄ in this period, MP _3, MP ₄ is off, the load resistance has a large load resistance value so determined by the MP _1, MP _2. However, during this period, it is only necessary to hold the output, so it is desirable to reduce the current.
Diodes D _{1 to} D _{4 connected} in parallel to the PMOS load are effective for preventing saturation of Q _{1 to} Q _{4 and} for stabilizing the output amplitude.

FIG. 6 is based on the assumption of an address buffer circuit of a BiCMOS memory, and is provided after the bipolar current switch.
A BiCMOS type level conversion circuit is added. D _{1 to} D ₃
Is a clamp diode, but the number of diodes is reduced by one as compared with FIG. MP _3, M _7, M ₈ and MP _4, M _9, bipolar level signal portions of M ₁₀ (amplitude 1.6V in this view) MO
Convert to an S level signal (amplitude V _cc ). Thereafter, an address buffer output B _i , ▲ ▼ is generated by the BiCMOS driver. MP ₁ and MP ₂ are for raising the potentials of a _i and ▲ ▼ to V _CC so that a through current does not occur in the subsequent circuit during standby (φ ₁ : low potential). M _8, M ₁₀ is that this level conversion circuit achieved constant-Ryuka as to operate stably even with respect to wide variation of V _CC. phi ₁ is the ▲ ▼ signal processed input signal as previously mentioned, at the same time on a current source of a large number of addresses cross Hua This phi _1, can be turned off.
Thus, the output of the bipolar differential amplifier a _i , ▲ ▼
When driving the S inverter _{(MP 3, M 7, M} 8 and _{MP 4, M 9, M 10} ),
Since the amplitude of a _i and ▲ ▼ is set as large as possible to reduce the through current of CMOS and speed up the level conversion, diode clamp D _{1 to} D ₃ so that the bipolar Q ₁ and Q ₂ are not saturated. It is useful.

Next described the preferred embodiments to generate the MOS of the current control voltage V _G as described in the above embodiments. FIG. 7 shows an embodiment thereof, which constitutes a so-called MOS current mirror circuit. Gate length of M _Sn1 According to this embodiment, the threshold voltage, manufacturing conditions such as a gate oxide film thickness or the power supply, even if use conditions such as temperature fluctuates, M ₁ gate of the ~M _n i _1, A current having a width ratio multiple (the absolute value varies but the ratio does not vary) can flow. In this case, V _G is varied but M ₁ ~M _n
, A constant current flows according to the principle of a current mirror.

8 is a more specific structure of the i ₁ supply circuit in FIG. 7. Q _S1, R _S1, R _S2 and D _S1, D _S2 at a constant current i ₂ (= V
_BE / V _S2 ) flows, and M _SP2 and M _SP1 also form a current mirror, so that i ₁ can be made twice as large as the gate width ratio of i ₂ .

Although the current value setting elements are arranged on the GND side in the configurations of FIGS. 1 to 6, even if the order is reversed as shown in FIGS. 9 and 10, the characteristics hardly change. Ninth
The configuration shown in FIG.

FIG. 10 is a plan view and a sectional view of a series connection configuration of these two MOS transistors M ₁ and M ₂ . In this case, it is assumed that the gate widths W _{M1 of the} two are set equal and the gate lengths L _M2 and L _M1 are different. Take increasing the gate length L _M2 of the current value setting element M _2, and the manner difficult to influence manufacturing variations. load capacity of phi ₁ is mainly gate capacitance, gate area L _M1 × W _M1
Therefore, L _M1 should be made as small as possible, and the load capacity seen from φ ₁ should be made small.

〔The invention's effect〕

As described above, according to the present invention, the current source of the semiconductor circuit has a configuration in which the switching MOS transistor and the current value setting element are connected in series, so that the function of the element can be optimized according to the application. Becomes possible. MO for switch
By making the S-transistor low on-resistance and making the current setting element larger than the switching MOS transistor, the stable current can be proportional to the semiconductor circuit, especially the differential amplifier circuit. It becomes possible. Therefore, a large number of address buffer circuits and main amplifier currents are turned on only during operation, as in semiconductor memory,
This is suitable for a configuration that is turned off during standby. Especially when Dainamitsuku large power supply noise voltage as a RAM (DRAM) occurs, by taking a high V _G, it is possible to suppress the variation of the current value. In the embodiment, the input signal for switching between the standby mode and the operation mode is indicated by ▼. However, depending on the type of the integrated circuit, a different name from the ▲ (row address strobe) or ▲ (chip select) signal is used. May be taken.

[Brief description of the drawings]

1 to 4, FIGS. 6 to 9 are circuit diagrams of an embodiment of the present invention, FIG. 5 is a pulse timing diagram of FIG. 4, and FIG.
FIG. 11 shows a layout of a MOS current source, and FIG. 11 shows a conventional technique. φ ₁ , ▲ ▼: Drive pulse, I ₁ , I ₂ ... Input signal, O
…… Output signal, V _G …… Current control voltage.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Kazumasa Yanagisawa, 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Computer Division, Hitachi, Ltd. (72) Yoshiki Kawajiri 1-280, Higashi Koikebo, Kokubunji-shi, Tokyo Address: Hitachi, Ltd., Central Research Laboratory, Ltd. Inside the Central Research Laboratory of the Works (72) Inventor Kiyoo Ito 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of the Hitachi, Ltd. 56) References JP-A-63- 86188 (JP, A)

Claims (2)

(57) [Claims] 1. A differential amplifier having a current switch circuit comprising a bipolar transistor, wherein a current source of the current switch circuit has a series configuration of a switching MOS transistor and a current value setting MOS transistor, and wherein the switching MOS transistor Is disposed closer to the bipolar transistor than the DC value setting MOS transistor, and a pulse is applied to the gate of the switching MOS transistor of the current switch circuit to switch the current between standby and operation. And applying a common voltage that does not change between standby and operation to the gate of the current setting MOS transistor of the current switch circuit. 2. An emitter follower circuit comprising a bipolar transistor for performing an emitter follower of a bipolar transistor constituting the current switch circuit, wherein a current source of the emitter follower circuit comprises a switching MOS transistor and a current value setting circuit. A current is switched between a standby state and an operation state by applying a common pulse to the gates of the switching MOS transistors of the current switch circuit and the emitter follower circuit. 2. The semiconductor circuit according to claim 1, wherein a common voltage that does not change during standby and during operation is applied to the gate of the current setting MOS transistor of the emitter follower circuit.