JP2914766B2 - Waveform shaping circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to video signal processing used for TV (television) and the like.

[0003]

2. Description of the Related Art In signal processing in a TV set, a radio wave of a broadcasting station is received by a tuner, and the received signal is processed by an audio signal processing circuit and a video signal processing circuit. The audio signal processing circuit extracts and processes only the audio signal, and then sends the audio signal to the speaker. In the video signal processing circuit,
Performs luminance signal processing, color signal processing, and synchronization signal processing. In the luminance signal processing, the luminance is adjusted by adjusting the image quality from soft to sharp, adjusting the amplitude, and adjusting the brightness. In the color signal processing, the color signal is detected, the hue is adjusted, and the saturation is adjusted, and a color difference signal is output. A luminance signal and a color difference signal are calculated to output primary color signals (R, G, B).

In the synchronization signal processing, horizontal synchronization signal processing and vertical synchronization signal processing are performed after synchronization separation, and a timing signal is output so that the same image as a transmission signal is obtained when an RGB signal is captured on a display. By performing the above signal processing, the received signal is displayed on the display.

In the luminance signal processing, noise removal called coring is performed to improve the S / N of the received signal. There are two methods of coring, which are shown in FIGS. Generally, FIG. 2 is called noise removal, and FIG. 3 is called noise cancellation. FIG. 4 shows the waveform of each part in FIG. 2, and FIG. 5 shows the waveform of each part in FIG.

First, the noise elimination in FIG. 2 will be described with reference to FIG. 4 showing signal waveforms at various parts in FIG. An input signal shown in FIG. 4A is input from the input terminal 1 and supplied to the A1 path and the B1 path. In the A1 path, only the low-frequency signal (b) is extracted through the LPF 2 and input to the adder 3. In the B1 path, the input signal (a) passes through the HPF4,
A high-frequency signal (c) containing a noise component is extracted. Further, a small amplitude luminance signal and noise inside the dotted slice level SL shown in the high-frequency signal (c) are passed through the slice circuit 5.
, Only the high-amplitude high-frequency signal (d) including the edge noise is extracted. Then, this signal is input to the adder 3. The adder 3 adds the low-frequency signal (b) and the high-frequency signal (d) to obtain an output signal (e) with little noise from the output of the adder 3 to the output terminal 6.

Next, the noise cancellation in FIG. 3 will be described with reference to FIG. 5 showing the signal waveforms of various parts in FIG. In FIG. 3, an input signal (f) is input to the A2 path and the B2 path. In the A2 path, the delay signal g obtained by the delay circuit 8 for making the signal have the same phase as the B2 path is input to the subtractor 9. In the B2 path, the input signal (f) is limited by the output signal (h) of the HPF 10 through the limiter circuit 11,
An output signal (i) having only small-amplitude luminance and noise is extracted. Then, the limiter output signal (i) is input to the subtractor 9. The subtracter 9 subtracts the limiter output signal from the signal of the delay circuit 8 to obtain an output signal (j) with less noise at the output terminal 12.

However, since the circuit of FIG. 8 is actually used for the slice circuit 5 and the limiter circuit 11, the signal of FIG. 4D output from the slice circuit 5 of FIG. 4), and the signal of FIG. 4 (i) output from the limiter circuit 11 of FIG. 3 becomes the signal of FIG. 7 (m). Therefore, the actually obtained output signal becomes the signal (l) in FIG. 6 in the system of FIG. 2 and the signal (n) in FIG. 7 in the system of FIG. Therefore, the edge of the output signal becomes more dull than the output signals of FIGS.

The reason will be described with reference to the limiter circuit 11 of FIG. 3 using the circuit of FIG. In FIG. 8, the input terminal IN when there is no signal is biased to the same voltage as the bias source V1. Also, the base of transistor Q3 is always V
At the voltage of 1−VL, the base of the transistor Q6 is V1 +
Biased to a voltage of VL. Here, VL is V
L = V2 = V3 is the limiter setting voltage. Therefore, the voltage follower including transistors Q2 and Q3, the transistor Q2 is turned ON than the base of the input terminal IN from the transistor Q3 so low voltage, the transistor Q ₃ is turned OFF. At this time, since the relationship between the current sources I4 and I1 is set so that I4> I1, the transistor Q2 is saturated, and the transistor Q1 is connected to the voltage V between the base and the emitter.
BE cuts off when reverse biased. In the voltage follower including the transistors Q5 and Q6, the base voltage of the transistor Q6 is higher than the input terminal IN, so that the transistor Q5 is turned on and the transistor Q6 is turned off. At this time, since the relationship between the current sources I2 and I5 is I2> I5, the transistor Q5 is saturated and the transistor Q4 is
BE cuts off when reverse biased.

In such a circuit state, the HPF 10
Is input to the input terminal IN of the limiter circuit 11 shown in FIG. When the input terminal IN falls below V1 -VL, the transistor Q3 is turned on, so that the transistor Q1 is also turned on to limit the input signal. When the input terminal rises further than V1 + VL, the transistor Q
Since transistor 6 is turned on, transistor Q4 is also turned on to limit the input signal. At this time, both the transistors Q1 and Q4 rapidly change from OFF to ON. However, since both the transistors Q1 and Q4 start from the reverse bias state of VBE, they cannot follow a sudden change in the signal. Therefore, the limit waveform is not (i) of FIG. 5 but (m) of FIG.
Waveform. Therefore, the output signal of FIG. 3 becomes (n) of FIG. 7 in which the edge is less than that of (j) of FIG.

[0011]

In any of the conventional coring means, the slice circuit or the limiter circuit constituting the coring means cannot follow an abrupt change in the signal, so that the edge of the output waveform becomes dull. was there.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit which eliminates the above drawbacks, slices or limits in a straight line, and minimizes edge rounding of an output signal.

[Structure of the Invention]

[0014]

According to the present invention, there are provided first and second transistors having emitters connected in common, and the first and second transistors having the same structure.
A first reference voltage source connected to a common emitter of the second transistor via a current source or a resistor, an emitter connected to a base of the first transistor for supplying an input signal, and a collector of the first transistor; A third transistor having a base connected to the third transistor, a second reference voltage source connected to the collector of the third transistor and connected to the collector of the first transistor via a load, Means for always setting the voltage between the base and the emitter to a forward bias.

[0015]

According to the present invention, signal slicing and limiting can be performed in a straight line.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The same parts as those in FIG. 8 are described with the same reference numerals.
In FIG. 1, the input terminal IN when there is no signal is connected to a bias source V _1.
Biased to the same voltage as Further, always on the voltage of the base of the transistor Q ₃ are V ₁ -V _L, the base of the transistor Q6 is biased to a voltage of V1 + VL. Therefore, in the voltage follower including the transistors Q2 and Q3, the input terminal IN is connected to the transistor Q3.
Since the base of the transistor is low, the transistor Q2 turns on,
The transistor Q3 turns off. At this time, the current source I4,
Since I1 is set to satisfy the relationship of I4> I1, the transistor Q2 is clamped by the emitter of the transistor Q8 so as not to saturate the transistor Q2. At this time, the voltage applied to the resistor R1 is changed to Vx so that the transistor Q8 clamp voltage prevents the transistor Q2 from being saturated and the transistor Q1 is not turned on.
Choose In the voltage follower including the transistors Q5 and Q6, since the base voltage of the transistor Q6 is higher than the input terminal IN, the transistor Q5 is turned on and the transistor Q6 is turned off. At this time, the current sources I2 and I
5 has a relationship of I2> I5, so that the transistor Q5
Is clamped by the emitter of the transistor Q10 so as not to be saturated. At this time, the clamp voltage of the transistor Q10 prevents the transistor Q5 from saturating and the transistor Q4
The voltage applied to the resistor R2 is selected as Vx so as not to turn ON.

[0018] choose this way without saturating the transistor of the voltage follower in the no signal, and the voltage V _X across the resistor R1 and R2 as transistor for clamping is not turned ON, the forward bias transistor for clamping Can be cut off.

In the circuit state when there is no signal, the HP of FIG.
The limiter operation of the circuit when the output signal of F10 is input to the input terminal IN of FIG. 1 will be described. When a signal lower than V1 -VL is input to the input, the voltage follower including the transistors Q2 and Q3 is turned on because the input is lower than the base of the transistor Q3. Transistor Q1 turns on to limit signals whose voltage is below V1-VL. Since the transistor Q1 is turned on from the OFF state of the forward bias, it can follow a sudden change of the signal, and the signal can be limited to a straight line as shown in the waveform of FIG. Next, when a signal higher than V1 + VL is input to the input, the voltage follower including the transistors Q5 and Q6 is turned ON because the input is higher than the base of the transistor Q6.
I do. Transistor Q4 turns on to limit signals whose voltage is higher than V1 + VL. At this time, the transistor Q4
Is turned on from the OFF state of the forward bias, so that it can follow even if the signal changes abruptly.

With such an operation, the HPF 10 shown in FIG.
5 (h), which is the output signal of FIG. 5, is input to the input terminal IN, so that the output signal can be limited to a straight line as shown in the waveform of FIG. 5 (i). When this circuit is used in FIG. 2, the signal output to the output terminal 6 in FIG. 2 can minimize edge rounding as shown in (e) of FIG. 4 instead of (l) of FIG.

As described above, the slice circuit 5 shown in FIG.
When the circuit of the present invention is applied to the limiter circuit 11, the edge rounding of the output signal can be minimized.

[0022]

According to the present invention as described above,
You can slice or limit in a straight line,
Edge rounding of the output signal can be minimized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a conventional circuit diagram.

FIG. 3 is a conventional circuit diagram.

FIG. 4 is an ideal waveform diagram of a main part of FIG. 2;

FIG. 5 is an ideal waveform diagram of a main part of FIG. 3;

FIG. 6 is a waveform diagram of a main part of FIG. 2;

FIG. 7 is a waveform diagram of a main part of FIG. 3;

FIG. 8 is a specific circuit diagram of a main part of FIGS. 2 and 3;

[Explanation of symbols]

 Q1 to Q3, Q6, Q9: transistor GND: ground Vcc: power supply R1: resistance I8: current source

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-16775 (JP, A) JP-A-2-1344982 (JP, A) JP-A-1-268264 (JP, A) JP-A-63-1988 138884 (JP, A) JP-A-1-268263 (JP, A) JP-A-63-146666 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 5/14-5 / 217

Claims (1)

(57) [Claims] 1. A first and second transistor having emitters connected in common, a first reference voltage source connected to a common emitter of the first and second transistors via a current source or a resistor, and an input. A third transistor having an emitter connected to the base of the first transistor for supplying a signal and having a base connected to the collector of the first transistor; and a third transistor connected to the collector of the third transistor and having the collector connected to the first transistor. A waveform shaping circuit comprising: a second reference voltage source connected from a collector of a transistor via a load; and means for always setting a voltage between a base and an emitter of the third transistor to a forward bias. .