JP2910281B2 - Serial bus synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus (serial bus) for transmitting and receiving serial data. In a computer system in which a master CPU and a plurality of slave units are connected, each slave unit in an activated state during maintenance is used. The present invention relates to non-stop operation, which eliminates system disconnection due to insertion and removal of the bus.

In recent years, in computer systems,
There is an increasing demand for system non-stop when replacing a unit due to a failure or when inserting or removing a unit for system maintenance. For this reason, it is necessary that removal and insertion of the activation unit in the operating state of the system be performed without stopping the system.

[0003]

2. Description of the Related Art As shown in a block diagram of FIG. 4, a conventional computer system including a serial bus has one bus master (CPU) and N bus slaves 1 to N (I / O-1,
To I / ON) transmit and receive serial signals on a bus (BUS). As shown in the illustration of the serial bus in FIG. 5, the bus (BUS) is
Transmission line SD for accessing M (I / OM) and each bus slave M
Receive line RD that (I / OM) returns data to the bus master (CPU)
The master (CPU) sends a fixed-length I / O access mode I / O Read format `` I / O address '' to the slave (I / OM), and the slave M (I / OM) , The “I / O address” and “Write data” of the I / O Write format in the fixed-length return mode are received.

[0004]

In such a system, an "I / ON access" signal exists on a transmission line SD from a master (CPU) of a bus (BUS) to a slave N as shown in FIG. At the timing of (A) in the figure, a certain bus slave
When L is inserted into the bus and connected to the system, the bus master (C
PU) accesses data `` I / ON
`` Access '' is erroneously received by the bus slave L, and `` I /
There was a problem that the "OL return" signal could be returned incorrectly. An object of the present invention is to solve the above problem, that is, to turn on a power supply of a certain slave unit L while the serial bus (BUS) is in an active state in which data transmission / reception is performed between the master and another slave N. When the bus is activated and inserted into the bus, a serial bus synchronization method that can be inserted without affecting the operation of returning data in the opposite direction to the access operation from the master (CPU) to the other slave N is provided. is there.

[0005]

The object of the present invention will be described with reference to the principle diagram of FIG.
A system in which other slaves 21 and 22 are already operating is connected to a serial bus 30 consisting of an SD line 31 for transmitting an address for accessing 23 and an RD line 32 for returning data from the plurality of slaves to the master. A slave without stopping
In the method of inserting the serial bus 23 in an activated state, the monitoring device 1 includes a monitoring unit 1 that monitors the bus from the time when the certain slave 23 is activated and inserted into the serial bus and detects the presence or absence of return data on the RD line, First, a section ("H") in which there is no return data on the RD line 32 for a fixed time equal to the transmission time of a predetermined Read format transmitted from the master 10 to the other slaves 21 and 22 on the SD line 31 for access. ), And then return “Wr” from the other slaves 21 and 22 on the RD line 32.
It waits for the "ite data" to be transmitted only once, and then waits for access from the master 10 to the slave 23 via the SD line 31 and transmits the data of the slave to the master. Achieved.

[0006]

According to the present invention, an SD line 31 for transmitting an address for access from the master 10 to each of the plurality of slaves 21, 22, 23 is provided.
And RD for returning data from the multiple slaves to the master
A monitoring unit 1 for monitoring the bus is provided inside the unit of the slave 23 inserted into the serial bus 30 composed of the line 32. The monitoring unit 1 starts monitoring a certain slave 23 when the other slaves 21 and 22 have activated and inserted the bus into the serial bus 30 where the slaves 21 and 22 are already operating. Is detected. First, a predetermined Read transmitted from the master 10 to access the other slaves 21 and 22 on the SD line.
RD line 32 for a fixed time equal to the transmission time of the format
Detects and waits for a section where no return data exists ("H"), then waits for the return "Write data" from other slaves 21 and 22 to be transmitted only once on the RD line Then, after waiting for an access from the master 10 to the slave 23 via the SD line 31, the data of the slave is transmitted to the master.

[0007]

FIG. 2 is a block diagram showing a circuit configuration of an insertion bus / slave in a serial bus synchronous system according to an embodiment of the present invention, and FIG. 3 is a sequence diagram for explaining an insertion operation to the bus. . The circuit block diagram of FIG.
As shown by SD and RD in the operation sequence diagram in Fig. 3, the SD signal first has an access signal "slave N access" from the master to the slave N, and then the RD line has a return signal from the slave N to the master. There is "Slave N return". next
There is an access signal “slave M access” from the master to slave M on the SD line, followed by slave M access on the RD line.
There is a return signal "Slave M return" from the
After that, if there is an access signal `` Slave L access '' from the master to the inserted slave L on the SD line, the slave L to be inserted is activated by turning on its power supply + 5v and inserted into the bus 30 In this case, an example of the circuit configuration of the insertion slave L is shown. In this bus slave L, the bus
The transmission unit 100 for transmitting transmission data to be returned to the master 10 includes a register 111 that stores transmission data in parallel and a parallel-to-serial data converter 112 that converts its output into serial data. The converter 112 converts the parallel data P in the register Reg 111 of the transmission data of the insertion bus slave L into the serial data S and converts the serial data S to the
Send (return) to

The monitoring section 1 of the present invention comprises an RD data non-transmission time detecting section 11 and a read data detecting section 12. The RD data non-transmission time detecting unit 11 is connected to the master on the RD line 31 of the bus 30.
OR circuit that ORs the output obtained by inverting the sign of the data transmitted to the (CPU) with the inverter INV and the PORst of the output (A) of the power-on reset circuit 300 that generates a reset signal when the power supply + 5v is turned on (B) to reset
This is a counter type detector that detects that there is no transmission data to the master (CPU) on the D line for a certain period of time.It counts the clock CLK given when there is no transmission data on the RD line, and the counted transmission data is SD-R with no time
A counter 11a that carries (Carry) every time the transmission time becomes equal to the transmission time of the ead format, and a flip-flop D that inputs the Carry output (C) and outputs the sign "H" of the power supply + 5v
-FF 11b and an inverter I for inverting the sign of the output of DF.F
Consists of NV 11c. The read data detector 12 is reset by the output (D) of the inverter INV 11c, and the RD line 3
A detector 12a for monitoring the presence or absence of transmission data on the RD line and transmitting a detection signal (E) of code "H" when detecting the presence of transmission data on the RD line, and detecting the power of + It is composed of a flip-flop DF.F 12b that outputs a 5V code "H". Reference numeral 200 denotes a receiving unit for receiving data.
The serial / parallel converter 211 includes a parallel converter 211 and a register 212, and the serial / parallel converter 211 includes the flip-flop DF.F 1
Input the serial data (G) of the output of the AND circuit that ANDs the output (F) of 2b and the received signal of the access signal `` slave L access '' sent from the bus master 10 via the SD line 31. The data is converted into data, and is written and stored in the register 212 of the received data. In the embodiment of the present invention shown in FIG. 2, the monitoring unit 1 of the 23 bus slaves L to be inserted into the bus 30 is connected to the serial bus 30 (not shown) other than the slaves M and N already operating. When the power supply + 5v is turned on and activated to insert the unit of the own slave L, the bus is started to be monitored, and the presence or absence of return data on the RD line 32 is detected.
First, the RD data non-transmission time detection unit 11 equals the transmission time of a predetermined Read format transmitted from the master 10 to access the other slaves M and N on the SD line,
A given clock CLK is counted by the counter 11a for a certain period of time when there is no return data on the upper side, and the carry (Carry) output is obtained, and the level of the power supply + 5v is output by the DF.F 11b.
H "and waits, and then the read data detection unit 12
Wait until the "Write data" returned from the other slaves M and N is transmitted only once on the D line, and then the SD line
At 31, the slave 10 waits for an access “slave L access” sent from the master 10 to the own slave L, and then transmits the data of the own slave L to the master 10. Therefore, even if the inserted bus slave L is activated and inserted into the bus 30, there is no problem because the operation of the other slaves M and N is not hindered.

[0009]

As described above, according to the present invention, without affecting the operation of the already operating system,
Since the slave unit can be replaced and maintenance work can be performed while the system is in operation, the effect of contributing to nonstop of the system is great.

[Brief description of the drawings]

FIG. 1 is a principle diagram showing a basic configuration of a serial bus synchronization system of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of an insertion slave of a serial bus synchronous system according to an embodiment of the present invention.

FIG. 3 is a sequence diagram for explaining the operation of the embodiment of the present invention.

FIG. 4 is a block diagram of a computer system including a conventional serial bus.

FIG. 5 is an explanatory diagram illustrating a configuration of a conventional serial bus.

FIG. 6 is an explanatory diagram for explaining a problem of a conventional slave unit insertion.

[Explanation of symbols]

1 is a monitoring unit, 11 is an RD data non-transmission time detecting unit, 12 is a read data detecting unit, 10 is a master, 20 is a plurality of slaves, and 21 and 2.
2 is already running slave, 23 is slave to insert, 30
Is a bus, 31 is an SD line, 32 is an RD line, 100 is a transmission data transmission section, 200 is a reception data reception section, and 300 is a power-on reset circuit.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-293730 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/40

Claims (1)

(57) [Claims] 1. Each of a plurality of slaves (20) from a master (10)
SD line for sending address to access (21,22,23)
(31) and a serial bus (30) composed of RD lines (32) for returning data from the plurality of slaves to the master.
1, 22) is a method of inserting a certain slave (23) in an activated state without stopping the already operating system, and activating the certain slave (23) on the serial bus. A monitoring unit (1) for monitoring the bus from the time of insertion and detecting the presence or absence of return data on the RD line, and first transmitting a predetermined signal from the master to the other slave for access on the SD line.
RD for a fixed time equal to the transmission time of Read format
Wait for the section where no return data exists on the line (32), then wait for the return data from the other slave to be transmitted only once on the RD line, and then wait for the SD line (31) A serial bus synchronization method characterized by waiting for an access from the master (10) to the own slave (23) and transmitting the data of the own slave to the master.