JP2908857B2 - Ultrasonic flaw detector - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic scanning ultrasonic flaw detector, and more particularly to an electronic scanning ultrasonic flaw detector which is configured as a unit to improve the efficiency of manufacturing and control.

[Prior Art] The basic configuration of an electronic scanning ultrasonic flaw detector is described on pages 20 to 30 of "Japan Society of Electronic Machinery Manufacturers: Medical Ultrasonic Equipment Handbook: Corona (1985)". Although this conventional example is a technique of an ultrasonic diagnostic apparatus used for medical use, it is mentioned because it can be applied to an electronic scanning ultrasonic flaw detector for industrial nondestructive inspection. As shown in FIG. 16, the conventional example includes a switch circuit unit such as a multiplexer switch circuit 301 and a switch matrix 302 for realizing the scanning of the ultrasonic beam, and a phasing circuit 303 for realizing the focusing and the deflection of the ultrasonic beam. Have been. The phasing circuit section 303 is a delay circuit
It is composed of 12 signal synthesizing circuits 5. The control of the entire apparatus is performed by the control circuit 304 controlling the switch circuit 301, the switch matrix 302, and the phasing circuit 303, respectively. In this conventional configuration, a circuit for each control function is divided into a switch circuit, a switch matrix circuit, and a phasing circuit. Therefore, as a matter of course, the design and production of those circuits are performed for each circuit. Such a design and manufacturing method can optimize the circuit for each function in terms of circuit functions and manufacturing cost, and is effective when the number of manufactured devices is large to some extent, such as a medical ultrasonic diagnostic device. Is the way. Since a medical ultrasonic diagnostic apparatus is intended for human inspection, the specifications of the apparatus are unlikely to change significantly, and such a design and production method suitable for mass production is adopted. If the number of vibrators and the number of aperture channels are different, it is necessary to design each circuit each time. Referring to FIG. 16, for each specification, a switch circuit section such as a multiplexer 301 and a switch matrix 302, and a phasing circuit 303
Will be designed and manufactured. Accordingly, the control software must be changed. The above is the conventional apparatus configuration and the design and manufacturing method of the electronic scanning ultrasonic flaw detection apparatus common to the medical ultrasonic diagnostic apparatus.

By the way, in industrial nondestructive inspection, there are inspection targets of various structures, even for generators, water turbines, and the like, and products having new structures are being manufactured. For this reason, in many cases, ultrasonic flaw detectors for inspecting their soundness are required to have different specifications for each inspection object. Moreover, in most cases, the number of these devices manufactured is one in most cases.

A conventional example using a memory is disclosed in Japanese Patent Application Laid-Open No. 56-9248.
No. 1, JP-A-57-131058, JP-A-57-17856, JP-A-57-17856
57-66356 and JP-A-57-131059.

[Problems to be Solved by the Invention] In the apparatus shown in the conventional example, no consideration is given to reducing the price of the apparatus or shortening the manufacturing period. Industrial ultrasonic flaw detectors include nuclear pressure vessels, piping turbine blades,
There are many types of inspection objects having various shapes, such as a small number or a single item, and products having a new structure have been produced. Therefore, the electronic scanning ultrasonic flaw detectors to be inspected with them are designed and manufactured according to the specifications to be inspected. Moreover, most of them are made separately. This prevents the cost of the electronic scanning ultrasonic flaw detector from being reduced in designing and manufacturing, and causes a long manufacturing period.

Further, in each of the above-described conventional examples, there is no viewpoint that efficient control of many probes is performed when viewed as a system.

An object of the present invention is to solve the above problems,
In the manufacture of the device, a single type of device configuration circuit is used to reduce the cost and shorten the manufacturing period, a device with various specifications can be configured, and in the application of the device, linear scanning and sector scanning are possible, and An object of the present invention is to provide an electronic scanning ultrasonic flaw detector that can be easily controlled.

[Means for Solving the Problems] The above object can be achieved by configuring the electronic scanning ultrasonic flaw detector to have a configuration in which many single types of units are arranged and each unit can be controlled by a common control signal line. it can. In other words, instead of designing and manufacturing a circuit for each circuit function to configure an apparatus, a large number of single-type units (specifically, circuit boards) that disperse and combine each circuit function are used and shared. It is intended to be able to control and to perform necessary operations as a whole. Units for this purpose include a selection circuit for selecting one channel from a large number of channels, a delay circuit for changing the delay time, a gain adjustment circuit for adjusting the gain, and a channel for selecting these channels, which are the basic functions of the electronic scanning ultrasonic flaw detector. And a storage circuit for storing delay time and gain. This recording circuit stores data on how each circuit is set in accordance with the operation state of the apparatus (transmission / reception position of ultrasonic beam, focal length, deflection angle, etc.). You have access to it. In the configuration of the device, the required number of units are connected to a common control signal line, for example, a bus line. Then, the storage circuit of each unit is accessed via the common control signal line, and each circuit is set to a predetermined state according to the data output from the storage circuit. With this configuration, each unit is switched to a predetermined circuit state only by outputting a control signal from the control circuit to the common control signal line, and the operation state of the device changes according to the switching to the control signal. The control signal may be set independently of the transmission / reception position of the ultrasonic beam, the focal length, and the deflection angle so that each operation state can be individually controlled, or one operation is performed by combining the operation states. It may be set as a state. In any case, the control of the device can be easily performed only by the control signal output to the common signal line.

[Operation] If a unit having the above-described functions is prepared, the electronic scanning ultrasonic inspection apparatus can be configured by arranging at least the necessary number of aperture channels in the unit. Therefore, when devices having different specifications (the number of transducers and the number of aperture channels) are required, by arranging the same number of units as the number of aperture channels of the required specifications, an electronic scanning ultrasonic flaw detector that meets the required specifications can be constructed. . By doing so, it is not necessary to design and manufacture each circuit for each device having different required specifications, and it is possible to manufacture an electronic scanning ultrasonic flaw detector with the required specifications in a short time. Also, when the number of channels needs to be expanded, it can be dealt with by adding a unit.

From the manufacturing point of view, the design cost is not included in the device because a new circuit design is unnecessary, and the manufacturing cost of the unit is reduced due to the mass production effect because the same unit is used in one electronic scanning ultrasonic flaw detector. Become cheap. Therefore, the electronic scanning ultrasonic flaw detector manufactured as described above can be reduced in price as compared with the conventional one even if it is a single product.

From the viewpoint of control of the device, a storage circuit for storing design conditions for each operation state of each selection circuit, each delay circuit, and each gain adjustment circuit is provided in each unit, and a common control signal is used to control all units. Since the setting of the selection circuit, the setting of the delay circuit, and the setting of the gain adjustment circuit can be performed, the control of the apparatus is also simple.

Example Next, an example of the present invention will be described.

First Embodiment FIG. 1 is an embodiment of an electronic scanning ultrasonic flaw detector which scans and focuses an ultrasonic beam by selecting five transducers as aperture channels from 20 transducers. And five units of the present invention, the same number as the number of open channels.
In the embodiment shown in FIG. 1, the case of receiving an ultrasonic wave is shown to simplify the drawing. In the case of transmission, the internal configuration of the unit is slightly different, and this will be described later. In FIG. 1, 1 is a unit according to the present invention, 3 is a control circuit for controlling the entire unit, 4 is a common signal line to which the unit is connected, 5 is a combining circuit for combining signals of the number of open channels into one, 7 Is a vibrator.

The operation of the device is as follows. The control circuit 3 outputs a control signal to a common signal line 4 such as a bus line. The control signal is determined according to the transmitting / receiving position of the ultrasonic beam and the focal length of the convergence. Each unit 1 sets each circuit in each unit so as to be at a transmission / reception position and a focal length of an ultrasonic beam corresponding to the control signal output on the common signal line 4, and transmits / receives an ultrasonic wave. Next, the control signal is updated, the transmission / reception position or focal length of the ultrasonic beam is changed, and the next transmission / reception of the ultrasonic beam is performed.

The details and operation of the internal configuration of each unit for performing the above-described operation will be described below. In the following,
A storage circuit is synonymous with a memory. As shown in FIG. 2, one unit includes a selection circuit 11, a delay circuit 12, a level adjustment circuit 13, a selected channel storage circuit 14, a delay time storage circuit 15, a level storage circuit 16, and a channel sensitivity storage of the selection circuit 11. The circuit 17 includes a delay sensitivity storage circuit 18 of the delay circuit 12, an address conversion circuit 19, and an opening channel number and unit number setting circuit 20. The vibrator 7 in FIG. 1 and each channel of the unit 1 are connected in a relationship as shown in FIG. The selection circuit 11 of the unit 1 determines a channel to be selected by a 3-bit binary code G, A ₁ , A ₀ as shown in FIG. 4, and the correspondence between the binary code and the selected channel is as follows. As shown in FIG. In the electronic scanning ultrasonic flaw detector shown in FIG. 1, the ultrasonic beam is transmitted and received by five transducers, and the transmitting and receiving positions of the ultrasonic beam are shifted by shifting the transducers to be selected one by one as shown in FIG. Can be scanned one transducer at a time. FIG. 6 shows that the ultrasonic beam can be transmitted and received at 16 scanning positions by selecting five consecutive transducers from the twenty transducers. Also, the ultrasonic beam can be focused by delaying the transmission / reception signals of the five transducers. FIG. 7 is a diagram showing the relationship between the focusing and the delay of the ultrasonic beam, and shows that a focused ultrasonic beam can be obtained based on the Huygens principle by giving a larger delay time to the center oscillator. . By changing the delay time, the focusing position, that is, the focal length can be changed. In FIG. 7, the delay time is 5
And the focal length is changed in five steps. The above-described scanning and focusing of the ultrasonic beam are used in combination, and in the electronic scanning ultrasonic flaw detector, switching of the vibrator accompanying the scanning and switching of the delay time are performed. Now, an electron scanning ultrasonic flaw detector configuration of Figure 1, consider the case of scanning the focused ultrasound beam having a focal length f ₁ as shown in Figure 7. When transmitting and receiving an ultrasonic beam at the scanning position # 0 in FIG.
The transducers used are numbered 1 to 5, and the transmission and reception signals of each transducer are given delay times of t1,1, t1,2, t1,3, t1,4 and t1,5 in that order.
At the scanning position # 0, the vibrators No. 1 to No. 5 correspond to the unit # 1 to the unit # 5 in this order. Therefore, t1 is added to the delay circuit 12 of each unit in the order of the unit # 1 to the unit # 5. , 1, t1,2, t1,3, t1,4, t1,5. Next, when transmitting and receiving the ultrasonic beam at the scanning position # 1, the transducers used are numbered 2 to 6, and the transmitted and received signals of each transducer are t1,1, t1,2, t1,3, t1, in order. 4. Give delay time of t1,5. In the case of this scanning position # 1, the vibrators 2 to 6
Since the numbers correspond to the order of the units # 2, # 3, # 4, # 5, and # 1, the order from the unit # 1 to the unit # 5 is as follows.
T1, 5, t1, 1, t1, 2, t1, 3, t
This will give a delay time of 1,4. FIG. 8 summarizes the relationship between the transducer No. used at each scanning position and the delay time given to the delay circuit 12 of each unit. From FIG. 8, the binary code to be given to the selection circuit 11 of each unit at each scanning position is stored in the selected channel storage circuit 14 using the scanning position number as an address in a memory map as shown in FIG. With such a memory map, the selection circuits 11 of all units can be switched at once only by accessing the storage circuits 14 of all units with a common scanning position number. Next, a memory map of the delay time storage circuit 15 will be considered. When five oscillators are used as shown in FIG. 7, the delay time given to the delay circuit 12 of each unit is five for one focal length. In consideration of the delay time cycle relative to the scanning position as shown in FIG. 8, the memory map of the delay time storage circuit 15 is
As shown in Figure 10. Address of the delay time storage circuit 15, assigning a delay code from 0 from the focal length f ₀ in the order of f ₄ 4, [Memory Address = Delay Code] ×
[Number of aperture channels] + [Remainder obtained by dividing the scanning position number by the number of aperture channels]. When such a memory map is used, all the units are calculated using the address calculated by the above equation, regardless of whether the delay position is fixed and the scan position number is changed or the scan position number is fixed and the delay code is changed. The delay time of the delay circuits 12 of all units can be set at one time only by making common access. The first described above
In the illustrated embodiment, the level adjustment circuit 13 can be set in addition to the selection circuit 11 and the delay circuit 12, but the method and the configuration of the memory map are the same as those in the case of the delay circuit, and therefore will be omitted. . The address calculation may be performed by the control circuit 3 for controlling the entire electronic scanning ultrasonic flaw detector. However, if the address calculation is performed by the address conversion circuit 19 shown in FIG. 2, the set time can be shortened. The number of repetitions of transmission / reception of minute ultrasonic waves can be increased, and the flaw detection efficiency can be increased. In this case, the number of open channels is required for address calculation.
The number of open channels may be set in the number of open channels and unit number setting circuit 20 in the figure. As described above, an electronic scanning ultrasonic flaw detector can be configured by simply arranging a single type of unit as in the present invention, and furthermore, by writing necessary data into a storage circuit of each unit, the control is completely controlled. The units can be operated with a common control signal (memory address as described above). Therefore, when a device having a different specification of the number of channels is required, a device meeting the specification can be manufactured in a short time. In addition, since the same unit is used in large numbers in one device, the unit price of the unit is reduced due to the effect of mass production, and the manufacturing cost of the device itself can be reduced. The present invention has the effects as described above.

In this embodiment, FIG. 5 is an example of a binary code, and the binary code is generally increased in the order of increasing channel number.
Since it is only necessary to make a one-to-one correspondence, it is not always necessary to make it as shown in FIG. Although a multiplexer or the like is used as the selection circuit 11, the channel number does not have to be the same as the channel number here. Therefore, the channel numbering method may be changed for each unit. In such a case, the contents of the selected channel storage circuit may be changed so that the ultrasonic beam scanning form is substantially the same as that of this embodiment. Good.

Second Embodiment As a second embodiment, a unit configured to correct the sensitivity variation in the selected channel of the selection circuit 11 and the sensitivity variation in each delay time of the delay circuit 12 will be described again. This will be described with reference to FIG. FIG. 2 shows a channel sensitivity storage circuit 17 of the selection circuit 11 and a delay sensitivity storage circuit 18 of the delay circuit 12. The sensitivity of the selected channel and the sensitivity of the delay circuit for each delay time are added to the level of the level storage circuit 16. The level is input to the level adjustment circuit 13 to adjust the level. Therefore, the sensitivity of the selection circuit 11 and the delay circuit 12
Can be corrected. Although the sensitivity variation has been described as the sensitivity variation of the selection circuit 11, the sensitivity variation of the vibrator itself may be included in the variation.

Third Embodiment As a third embodiment, another configuration example of the memory map of the delay time storage circuit will be described. Looking at the arrangement of the delay time data in FIG. 10, it is noticed that the storage addresses of the same data are shifted for each unit. From the regularity, for example, the memory map of the delay time storage circuit of all units
In the case of the memory map of the unit # 5 in FIG. 11, [memory address] = [delay code] × [number of aperture channels] + [[scanning position number + number of aperture channels−unit number]] is divided by the number of aperture channels. Remainder]. In this case, as in the first embodiment, the number of open channels and the unit number setting circuit 20 of the device required for address calculation are as follows.
For example, a code switch is provided. By doing so, the contents of the delay time storage circuits of all units can be made the same. Therefore, in this embodiment, since the same contents can be simultaneously written in the delay time storage circuit of each unit, the cost and time involved in writing can be saved, so that the unit can be manufactured at a lower price, and the manufacturing of the device can be realized. Costs are also reduced.

Fourth Embodiment As a fourth embodiment, another embodiment of the memory map of the selected channel storage circuit and the delay time storage circuit will be described. In this embodiment, one memory address is assigned to each combination of the ultrasonic beam transmitting / receiving position, focal length, and deflection angle. Therefore, the scanning shown in FIG.
The memory map of each unit when the convergence in the figure is combined is as shown in FIG. In this embodiment, the use efficiency of the memory is low when the combination of scanning and focusing has periodicity, but the memory map configuration method required when there is no periodicity or when there is an exception in the periodicity is used. is there. Therefore, this embodiment is effective when the inspection object has various shapes and it is necessary to change the focal length for each ultrasonic beam transmission / reception position.

Fifth Embodiment As a fifth embodiment, a level adjustment circuit and a selection circuit for transmitting an ultrasonic beam will be described. Ultrasonic waves are generated by applying a pulse voltage to an ultrasonic transducer, and the amplitude of the generated ultrasonic waves can be changed by the pulse voltage.

This pulse voltage is applied to the capacitor 5 as shown in FIG.
0, 54, resistors 51, 53, FET 52, coil 55, diode 56,
57 can be generated. In order to change the pulse voltage, the power supply voltage Vpp of the circuit shown in FIG. 13 may be changed. Therefore, in the transmitting unit, the first
As shown in FIG. 4, as the level adjustment circuit 113 for adjusting the amplitude of the ultrasonic wave, a unit capable of changing the power supply voltage of the pulse voltage generation circuit 200 by using a power supply capable of changing the voltage by an external signal. What is necessary is just to be a structure.
In FIG. 14, the transmission selection circuit 111 includes the pulse voltage generation circuit 200 as shown in FIG. In addition, since the delay in the case of transmission is a delay of the digital trigger signal, it is not necessary to correct the level fluctuation in the delay circuit, so that the delay sensitivity storage circuit 18 shown in FIG. Has become. If the transducer itself has sensitivity variations, it is included in the sensitivity variation of the selection circuit 111 and the sensitivity variation data is stored in the channel sensitivity storage circuit 17 so that the pulse voltage generation circuit 20 during transmission can be used.
The variation of 0 and the variation of sensitivity of the vibrator itself can be corrected. As described above, according to this embodiment, adjustment and correction of the transmission level of the ultrasonic beam can be easily performed. In this embodiment, the transmission selection circuit 111 including the pulse voltage generation circuit of FIG. 14 switches the trigger signal by the selection circuit 11 as shown in FIG. Used for several minutes. This may be achieved by using a single pulse voltage generation circuit and switching the pulse voltage output by the selection circuit 11. As the selection circuit 11 in this case, a high breakdown voltage multiplexer or the like may be used.

Sixth Embodiment As a sixth embodiment, a case where a microcomputer is provided in a unit will be described. As shown in FIGS. 9 and 10, the contents of each storage circuit of the unit of the present invention have regularity, and once the unit number is determined, the contents can be obtained by calculation. For example, in the contents shown in FIG. 9, the contents of the memory address are different for each number of open channels, and are shifted for each unit number. Therefore, the microcomputer reads the number of aperture channels and the set value of the unit number setting circuit 20, and from the data, the contents of the memory shown in FIG. 9 can be calculated.
Also, the memory contents of the delay time shown in FIG. 10 provide the focal length and the element pitch of the array probe necessary for calculating the delay time to the microcomputer of the unit from the outside, and the delay time is calculated by the microcomputer. Can be obtained by calculation. This microcomputer is shown in FIG.
If provided in the address conversion circuit 19 in FIG. 14, each memory can be accessed, and at the same time, the address calculation required in the first embodiment can be performed. With this configuration of the unit, it is possible to set the conditions of each circuit so that the scanning form of the ultrasonic beam is not determined in advance, but becomes the scanning form necessary for actual use. Therefore, it is possible to form an ultrasonic beam most suitable for an inspection object, and the accuracy of ultrasonic inspection is also improved.

[Effects of the Invention] As described above, according to the present invention, the electronic scanning ultrasonic flaw detector is configured such that a single type of unit as described above is connected to a common signal line and arranged. It is possible to manufacture an electronic scanning ultrasonic flaw detector of required specifications in a short period of time and at a low price. Further, when the specifications of the device are expanded, it is possible to cope with the addition of the unit without newly designing and manufacturing.

From the viewpoint of control of the device, a storage circuit for storing setting conditions for each operation state of each circuit is provided in each unit,
By allowing each circuit setting of all units to be performed by a common control signal, control can be easily performed.

[Brief description of the drawings]

FIG. 1 is a view showing an embodiment of an electronic scanning ultrasonic flaw detector according to the present invention, FIG. 2 is a structural view of a unit according to the present invention, and FIG. FIG. 4 is a diagram illustrating the connection relationship between the unit and the channel, FIG. 4 is a diagram illustrating the function of the selection circuit of the unit in FIG. 2, FIG. 5 is a diagram illustrating the relationship between the control signal of the selection circuit in FIG. FIG. 6 is a diagram for explaining the scanning of the transmitting / receiving position of the ultrasonic beam, FIG. 7 is a diagram for explaining the focusing of the ultrasonic beam by delay control, and FIG.
FIG. 9 is a diagram showing the relationship between the transducer and the delay time using the transmitting / receiving position of the ultrasonic beam in the embodiment of FIG. 1. FIG. 9 is a memory map of the selected channel storage circuit of each unit of the first embodiment. FIG. 10 is a configuration diagram of a memory map of the delay time storage circuit in the first embodiment, and FIG. 11 is a second configuration diagram of a memory map of the delay time storage circuit in the first embodiment. FIG. 12 is a third configuration diagram of a memory map of the selected channel storage circuit and the delay time storage circuit, FIG. 13 is a pulse voltage generation circuit diagram,
FIG. 14 is a block diagram of the unit of the present invention for transmission, and FIG. 15 is a block diagram of FIG. 13 including the pulse voltage generation circuit of FIG.
FIG. 16 is a configuration diagram of a conventional electronic scanning ultrasonic flaw detector. 1 unit of the present invention, 3 control circuit, 5 signal synthesis circuit, 7 vibrator, 11 selection circuit, 12 delay circuit, 13 level adjustment circuit, 14 selection Channel storage circuit, 15: Delay time storage circuit, 16: Level storage circuit, 17: Channel sensitivity storage circuit, 18: Delay sensitivity storage circuit, 19: Address conversion circuit, 20: Number of aperture channels and unit Number setting circuit, 111: Transmission selection circuit including pulse voltage generation circuit, 112: Transmission level adjustment circuit, 200: Pulse voltage generation circuit, 300: Array probe, 301: Multiplexer, 302 ... switch matrix, 303 ... phasing circuit, 304 ... control circuit.

Continued on the front page (72) Inventor Hiroaki Chiba 3-1-1, Sachimachi, Hitachi-shi, Ibaraki Pref. Inside Hitachi, Ltd. Hitachi Plant (72) Inventor Tetsuo Taguchi 3-1-1, Sachimachi, Hitachi-shi, Ibaraki Stock Hitachi, Ltd. Hitachi Plant (72) Inventor Hirose Sakaigawa 3-2-1 Sakaimachi, Hitachi City, Ibaraki Prefecture Inside Hitachi Engineering Co., Ltd. (56) References JP-A-1-148243 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G01N 29/00-29/28

Claims (6)

(57) [Claims] An ultrasonic transducer array, which is coupled to the ultrasonic transducer row, selects a channel of the ultrasonic transducer based on a control signal, delay-controls a signal of the selected channel, and A plurality of ultrasonic control units that transmit and receive sound waves, and are commonly coupled to the plurality of ultrasonic control units,
In an electronic scanning ultrasonic flaw detector including a common signal line for carrying a control signal required for operation of the ultrasonic control unit and a control device for carrying a control signal on the common signal line, the ultrasonic control unit includes: A selection circuit for selecting a channel of the ultrasonic transducer row by channel designation data, a delay circuit for delaying transmission and reception of ultrasonic waves connected to the selection circuit by delay data, and a level control connected to the delay circuit for level adjustment A level adjustment circuit that performs adjustment by the adjustment data, a first memory that stores channel designation data and provides the selection circuit with the channel designation data;
A second memory for storing delay data and providing delay data to the delay circuit; a third memory for storing level adjustment data and providing level adjustment data to the level adjustment circuit; and a third memory connected to the common signal line. An ultrasonic flaw detector comprising: an access unit for giving an address to the first, second, and third memories to access the first, second, and third memories. 2. An ultrasonic transducer array, which is coupled to the ultrasonic transducer row, selects a channel of the ultrasonic transducer based on a control signal, delay-controls a signal of the selected channel, and A plurality of ultrasonic control units that transmit and receive sound waves, and are commonly coupled to the plurality of ultrasonic control units,
In an electronic scanning ultrasonic flaw detector including a common signal line for carrying a control signal required for operation of the ultrasonic control unit and a control device for carrying a control signal on the common signal line, the ultrasonic control unit includes: A selection circuit for selecting a channel of the ultrasonic transducer row by channel designation data, a delay circuit connected to the selection circuit for delaying transmission and reception of ultrasonic waves by delay data, and a level adjustment connected to the delay circuit for level adjustment A level adjustment circuit for performing data operation, a first memory for storing channel designation data and providing channel designation data to the selection circuit, a second memory for storing delay data and providing delay data to the delay circuit; A third memory for storing the level adjustment data, a fourth memory for storing the delay sensitivity data,
The fifth memory for storing the channel sensitivity data and the data read from the third, fourth, and fifth memories are added to create calibration level adjustment data, and this is used as the level adjustment data in the level adjustment circuit. And an access means connected to the common signal line for accessing the first, second, third, fourth, and fifth memories by giving an address. . 3. The access means receives a scan position number from a common signal line, and stores the scan position number in a first, second, and third memory according to a memory map corresponding to the first, second, and third memories. 2. The ultrasonic flaw detector according to claim 1, further comprising means for generating an address. 4. The control device has a memory map corresponding to first, second, and third memories in response to a common scanning position number, and outputs the memory map on the common signal line. The ultrasonic flaw detector according to claim 1. 5. A setting circuit for setting the number of open channels and the unit number is provided, and an access address to the second memory by the access means is set to the number of open channels, the unit number, and the common signal line by the setting circuit. And a scanning position number provided by the user.
Or 2 ultrasonic flaw detector. 6. An ultrasonic transducer array, which is coupled to the ultrasonic transducer row, selects a channel of the ultrasonic transducer based on a control signal, delay-controls a signal of the selected channel, and A plurality of ultrasonic control units that transmit and receive sound waves, and are commonly coupled to the plurality of ultrasonic control units,
In an electronic scanning ultrasonic flaw detector including a common signal line for carrying a control signal required for operation of the ultrasonic control unit and a control device for carrying a control signal on the common signal line, the ultrasonic control unit includes: A selection circuit for selecting a channel of the ultrasonic transducer row by channel designation data, a delay circuit connected to the selection circuit for delaying transmission and reception of ultrasonic waves by the delay data, and a level adjustment of the selection circuit by the level adjustment data A level adjustment circuit to perform,
A first memory for storing channel designation data and providing channel designation data to the selection circuit, a second memory for storing delay data and providing delay data to the delay circuit, and a third memory for storing level adjustment data A fifth memory for storing channel sensitivity data of the selection circuit, a means for adding the corresponding data of the third memory and the fifth memory, and providing the same as level adjustment data to the level adjustment circuit; An ultrasonic flaw detector, comprising: an access unit connected to a common signal line for giving an address to and accessing the first, second, third, and fifth memories.