JP2906819B2 - Parallel computer and data exchange controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer having a plurality of processing elements.

[0002]

2. Description of the Related Art FIG.
5 is a system configuration diagram showing the conventional distributed shared memory type parallel computer shown in FIG. In the figure, reference numeral 1 denotes a processing element (hereinafter, also referred to as PE). PE
Is a basic unit of a parallel computer, and the parallel computer is composed of an arbitrary number of PEs. Reference numeral 2 denotes a processor (MPU), and reference numeral 5 denotes a distributed shared memory distributed to each PE. A system bus 6 connects the PEs of the entire system. Reference numeral 29 denotes a FIFO register (hereinafter, also referred to as FIFO) having a function of buffering output data from the PE and controlling transfer timing. Reference numeral 30 denotes a data transfer control processor (hereinafter, also referred to as a transfer PE) that controls data transfer of the entire system. In this configuration, in the distributed shared memory, all PEs can access all addresses, but memory addresses arranged in the same PE can be accessed at high speed.

Next, the operation will be described. In this system, data required when each PE executes a program is basically stored in a distributed shared memory in its own PE. With this policy, it is not necessary to access data via the system bus as long as the relationship between the operation and the data is closed within the own PE, so that the memory can be accessed at high speed. However, when one process is shared and executed by a plurality of PEs, data exchange between the PEs is required in most cases. In this system, a dedicated data transfer control processor 30 is in charge of all data transfer between PEs in order to efficiently execute this data exchange. First, when it becomes necessary to transfer the operation result in each PE to another PE, the MPU transfers the data to the FIFO 29.
To be stored. In the transfer PE 30, the order in which each PE stores data in the FIFO and the transfer destination of the data are indicated in advance by the transfer program.
Can perform a data transfer operation asynchronously with the operation of the MPU. Further, since the FIFO 29 has an interrupt control mechanism for indicating the presence or absence of the requested data to the transfer PE 30, the transfer PE 30 can perform the transfer with the minimum synchronous overhead.

When this system is compared with the conventional centralized arrangement type shared memory + cache system (hereinafter referred to as a centralized system), in the centralized system, data transfer between PEs is performed by writing back from the cache to the memory and from the memory to the cache. It is necessary to transfer data on the bus twice for writing data. In the centralized system, the transfer from the memory to the cache occurs after the data is required for the operation of each PE. Therefore, the transfer timing is fixed, and there is a high possibility that the transfer operation conflicts. Was waiting for. On the other hand, in the distributed shared memory system shown here, the number of data transfers is halved, the degree of freedom in data transfer timing is improved, and the actual bus performance is improved.

[0005]

In the conventional data transfer control processor system in the distributed shared memory system parallel computer, a dedicated data transfer program is required for each application for the transfer operation, and the program design is complicated. In addition, there is a problem that it is necessary to statically define a load distribution method in advance in order to create a data transfer program, and that dynamic load distribution during execution is difficult.

The present invention facilitates the design of a compiler by designating an address of a data transfer destination by a load distribution among PEs in a parallel computer by an address mapping method and further using a part of a memory as a broadcast area. It aims to reduce the complexity in designing application programs.

Another object of the present invention is to provide a system which can realize a data exchange control device having a broadcast unit and an asynchronous access unit.

[0008]

A parallel computer according to the present invention includes a plurality of processing elements having a processor for performing data processing, and a plurality of processing elements for storing data.
Memory to multiple processing elements
Each memory is allocated to other processing.
Normally used as a distributed shared memory shared with elements
In column computer, each processing element, de
Data to the data area of the distributed shared memory where
Address mapping means for performing dress mapping ;
Distribution mapped by the address mapping means
A specific area of the shared memory data area is assigned to each processor.
Group as a common broadcast area
Broadcasting means and the address mapping means
Processing based on broadcast and broadcast means
Within the element and other processing elements.
Receives a memory access request from the processor and responds to the request.
Request the actual memory access
Command execution operation and asynchronous access means to execute asynchronously
And the parallel computer has the broad key
Placed on each processing element as a custom area
A specific area of each processed memory to each processing element.
Physically secured for each broadcast and the broadcast
Writing to the flash memory area is performed by the processing elements described above.
Identification of each physically reserved memory for each element
For each area by each asynchronous access means
The reading from the broadcast area is
Each processing element for reading
The specified area of the physically secured memory is
By the asynchronous access means of the processing element
It is characterized by being performed.

A data exchange control device according to the present invention has the following elements. (A) a self-processing element master request control means for receiving a memory access request from a processor of the self-processing element, determining whether or not the request is a broadcast access request, performing address mapping, and completing the memory access request asynchronously with the processor; (B) another processing element master request control means for receiving a memory access request from a processor of another processing element, determining whether the request is a broadcast access request, performing address mapping, and completing the memory access request asynchronously with the processor; (C) Communication control means for controlling data exchange via the data transfer path by the own processing element master request control means and the other processing element master request control means.

[0010]

The parallel computer according to the present invention controls the data division to each PE by address mapping. Also,
In the case of dividing one set of data on a logical address such as an array into a plurality of PEs, by mapping the data to a broadcast area placed on a memory, a change in address mapping due to a change in data division does not occur. For example, in a system in which the memory address of the shared memory distributed in each PE is represented by an upper address including the PE address and a lower address using the offset address, each of the PE addresses indicating each PE is added. The broadcast function is realized by recognizing one specific PE address determined in advance as a broadcast address in combination with the address mapping function.

The data exchange control device according to the present invention realizes the broadcast means and the asynchronous access means, and controls the access request from the processor and the communication control between the data exchange control devices of its own processor. performs the arithmetic operation asynchronously, it is determined whether a broadcast access request, the communication control and Memoria for broadcast access request
Access .

[0012]

【Example】

Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 denotes a processing element (PE), in which four PEs are described,
Actually, a parallel computer is composed of an arbitrary number of PEs. Each PE is composed of the following 2 to 5 elements. 2 is a processor (MPU). Reference numeral 3 denotes a memory management unit (MMU) which performs address conversion from a logical address to a physical address. Reference numeral 4 denotes a data exchange control unit (DXU) which controls all memory accesses. 5
Is a distributed shared memory. The distributed shared memory is a shared memory having one linear physical address in the entire computer system. However, since it is distributed in each PE, it has the property of a local memory, and each MP
For U, the memory in its own PE can be accessed faster than the memory in other PEs. A system bus 6 connects all the PEs in the parallel computer. In the present system, the DXU 4 is connected to this system bus.

FIG. 2 is a block diagram showing the internal configuration of the DXU 4. As shown in FIG. Reference numeral 7 denotes a self-PE master request control unit which is in charge of control accompanying an access request from a master (MPU 2 and MMU 3) in its own PE. 8 is another P
This is another PE master request control unit that controls an access request from the master of E. Reference numeral 9 denotes a priority control unit that determines the priority according to the type of the access request. Reference numeral 10 denotes a memory access control unit that actually accesses the distributed shared memory 5 in its own PE. 11 is DXU via bus
DXU communication control unit for controlling inter-communication. These have an appropriate buffer inside. In addition, the own PE master request control unit 7, the other PE master request control unit 8, and the DXU communication control unit 11 transmit the master (MPU2 and MM) in their own PE.
U3) and is designed to operate asynchronously with the masters of other PEs.

Next, the operation will be described. First, a case where four PEs in FIG. 1 share a group of processes will be described. In this case, there is one logical address space in the whole system. Each MPU has its own MMU, but its address mapping table is centrally managed by the OS from the entire system. The address mapping table managed by the OS may be fixedly used during the execution of the process, or may be changed during the execution of the process according to the dynamic scheduling.

Although the memories are arranged in a distributed manner, since the memories are shared memories, each area of the logical address space 12 is assigned to one of the areas of the physical address space 13 on a one-to-one basis as shown in FIG. In this method, for example, "address in logical address space" 15 is composed of an index number (upper address) and an offset address (lower address). The MMU generates an “ address in the physical address space” 16 by converting the index number of the “address in the logical address space” 15 into a page number. The page number in the “address in the physical address space” 16 can be composed of, for example, a PE number and a page number.
By composing the upper address from the E number and the page number, the “address in the distributed physical address space” 17 can be composed. The PE number indicates the address of the PE. For example, when there are four PEs, P
E number (also called PE address) is “00”, “0”
1 "," 10 ", and" 11 "As described above, the upper bits of the physical address are assigned to the P specifying the PE.
Used as E address. Therefore, all MPU
Does not need to be aware of whether specific data is allocated to the physical address space of its own PE or to the physical address space of another PE, and can freely access in either case. However, since the access speed is different, necessary data should be
In the area.

First, data relating to only a specific PE throughout the execution of the process is mapped to the memory of that PE. The problem is how to handle large-scale data exchange between PEs during the execution of the process. FIG. 4 shows such an example. This is an operation on array data. First, it is assumed that when the process 1 is performed on the array A, the data is divided into rows and allocated to each PE as shown in the figure. Here, in order to speed up access, array data is allocated to each PE in units of rows as in the case of processing division.
Can be performed without the need for data exchange. Next, array B is created as a result of this processing. In this case, the data is divided into the distributed shared memories of the PEs as indicated by B-1. Here, when the next processing 2 needs to divide the data of this array as shown in B-2 and process it in each PE, large-scale data exchange occurs between the PEs.

In such a case, a method for executing the data exchange between PEs at a high speed and an address mapping method for dividing the array A, the array B, the array C, etc. into each PE will be described below. First, as shown in FIG. 3, when there are four PEs,
How to perform a focus inter-PE data exchange at high speed will be described. Array B when "Process 1" sequentially outputs the operation results
Instead of being output as −1, it is directly output as an array B-2 divided according to the next “processing 2”. That is, as an output of the processing 1, the PE1 stores the data X11
Is output to the distributed shared memory of PE1, and data X12 is
E2 is directly output to the distributed shared memory, and data X13 is
E3 is directly output to the distributed shared memory, and data X14 is
Output directly to the E4 distributed shared memory. Similarly, PE2
Outputs data X21 to the distributed shared memory of PE1,
Output data X22 directly to the distributed shared memory of PE2,
Output data X23 directly to the distributed shared memory of PE3,
Data X24 is directly output to the distributed shared memory of PE4. Hereinafter, the same applies to the data X31 to X44. As a result, the data can be forwarded immediately after the previous processing is completed, not when data is needed for the next processing. At this time, since each control unit of the DXU has a function of operating asynchronously with the MPU, even if a transfer wait occurs due to a bus neck, this does not immediately become an overhead of the MPU. As a result, the data transfer performance of the bus is substantially improved.

Next, as shown in FIG.
An address mapping method for dividing an array into each PE will be described by taking an example where there are three PEs. This
Thus, in the method shown below, P which is one more than the actual number of PEs
E-address required. In general, arrays are arranged in blocks on logical addresses. To divide this into a plurality of PEs, the method shown here uses address mapping from logical addresses to physical addresses. However, since this address mapping is performed on a page basis, it is not easy to realize a desired division method, and it is necessary to devise a special arrangement in advance on a logical address.
In order to solve such a problem, this system introduces a broadcast area in a memory. First, a specific area on a logical address is defined as a broadcast area, and a compiler or the like assigns an array in this area, and specifies that this array is physically broadcast to the OS or the like to the distributed shared memory of each PE. I do. As this address, in this embodiment, the fourth PE address, that is,
It is assumed that “11” is assigned. When mapping a logical address to a linear physical address using the MMU,
Only the broadcast area has a fixed PE address.
It is mapped to the same PE address “11”. However, the page address can be freely set as long as it does not conflict with the general area.
You can ping. Further, as shown in the figure, this area on the physical address is simultaneously mapped to the same page of all PEs with respect to the actual physical memory by the function of the DXU.

The operation of the DXU for realizing this function will be specifically described. FIG. 5 is a diagram showing address mapping when there are three PEs, and the memory addresses in each PE have different PE numbers (PE addresses) as shown at 17 in FIG.
It is assumed that the page number and the offset address (lower address) are set exactly the same. DX
U determines this PE address and takes action if it is its own memory. A specific PE address, for example, “1”
An address having "1" is defined as a broadcast address. In the case of this address, all DXUs perform an access operation and write to this broadcast area is performed by each PE.
Distributed Shared Memory Broadcast Address Page
And writing to the same address as the offset address (in the case of writing). This allows broadcasting. However, when a command to read the PE address is issued, the processing is performed locally in the own PE. That is, writing to the array or the like assigned to the broadcast area is performed in the distributed shared memory of all PEs, and reading is performed from its own distributed shared memory. It has been shown that when the logical address is assigned, the broadcast address can be indicated to the OS by setting the PE address to 11. However, the maximum capacity of the broadcast area is limited to each P regardless of how many PEs increase.
Since it is constant and equal to the maximum memory amount of E, this method can be used. Also, in this method, the write operation is immediately reflected in all memories, so that coherency is maintained. In addition, by defining priorities for the types of access, the quality of coherency can be kept high and the performance can be improved.

Embodiment 2 FIG. By providing a buffer in the DXU, the function of asynchronous access can be further improved, and the degree of freedom can be further increased.

Embodiment 3 FIG. This broadcast area is a logical address space.
It may change its application range in page units by the region assignment from 0 to a total area of the system.

Embodiment 4 FIG. In the above embodiment, the case where the number of PEs is four or three is described, but the number is not limited.

Embodiment 5 FIG. Next, a case where a plurality of processes run simultaneously will be described. In this case, there are a plurality of logical address spaces, which are mapped to one physical address space. This can be handled in exactly the same way as for a single process, just by creating an address mapping table in that way.

Embodiment 6 FIG. In the first embodiment, the case where the entire parallel computers are connected by one system bus has been described. However, as shown in FIG. 6, the parallel computers may be divided and connected to a plurality of buses. This is described in the above-mentioned “Japanese Patent Application No. Hei 3-04956.
FIG. 5 is a configuration diagram of a parallel computer using a multiple cluster bus indicated by No. 5; The method described in the first embodiment can be applied to a case where a plurality of clusters are formed in the system as shown in FIG. The address mapping table is centrally managed throughout the system, and each process is allocated so as to be closed in one cluster. In this way, the applicable range of the broadcast access request can be physically limited within the cluster, so that the same offset area can be used for storing another array for each cluster. Another advantage is that the bus load can be reduced.

[0025]

As described above, according to the present invention, in the case of dividing data into PEs in a parallel computer, address designation is performed by address mapping, and
A broadcast function is provided, so if data that is treated as a group on a logical address such as an array is divided into multiple PEs, any variable that stores that data can be specified only as a broadcast variable when designing a program. And the data division can be dynamically changed at the time of execution. Further, in addition to the above, since the DXU is configured to execute the data transfer operation asynchronously with the MPU, it is possible to maintain the degree of freedom of the transfer and to keep the effective performance of the bus high as in the conventional case.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a parallel computer according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a data exchange control device according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing address mapping in one embodiment of the present invention.

FIG. 4 is an explanatory diagram showing data exchange between PEs, which is an object of the present invention.

FIG. 5 is an explanatory diagram showing a broadcast area mapping method according to an embodiment of the present invention.

FIG. 6 is a system configuration diagram of a conventional parallel computer, and is also a system configuration diagram of a parallel computer showing one embodiment to which the present invention can be applied.

FIG. 7 is a system configuration diagram of a conventional parallel computer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processing element (PE) 2 Processor (MPU) 3 Memory management unit (MMU) 4 Data exchange control unit (DXU) 5 Distributed shared memory 6 System bus 7 Own PE master request control unit 8 Other PE master request control unit 9 Priority Control unit 10 Memory access control unit 11 Inter-DXU communication control unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 15/16 645 G06F 9/38 370 G06F 15/177 682

Claims (2)

(57) [Claims] A plurality of processing elements having a processor for performing data processing , and storing data;
A plurality of memories to be processed by the plurality of processing elements.
On each memory, and allocate each allocated memory to other processes.
Used as distributed shared memory shared with the
In the parallel computer used, each processing element is assigned to the data area of the distributed shared memory where the data is located.
An address mapping means for performing address mapping, minutes mapped by the address mapping means
A specific area of the shared memory data area is assigned to each processor.
As a common broadcast area for
Broadcasting means, the address mapping means and the broadcasting means.
Step-based self-processing elements and other processes
Processor memory access in the processing element
When a request is received, the actual memory access
Is executed asynchronously with the instruction execution operation of the requesting processor.
Which has a asynchronous access means for rows, the parallel computer, as the broadcast area, the processing error
A specific area of each memory located in the
Each physical element is physically secured, and writing to the broadcast area is
Physically reserved for each processing element
Each asynchronous access to a specific area of
Performed respectively by stage, reading from the broadcast region, read out
For each processing element that performs
The process for a specific area of physically secured memory.
By the asynchronous access means of the
A parallel computer characterized by the following. 2. A parallel first of claims have the following elements
Data exchange control device used for column computer (a) Receives a memory access request from the processor of its own processing element, determines whether it is a broadcast access request, performs address mapping, and completes the memory access request asynchronously with the processor. (B) receiving a memory access request from a processor of another processing element, determining whether the request is a broadcast access request, performing address mapping, and completing the memory access request asynchronously with the processor. The other processing element master request control means, and (c) the data transfer path by the own processing element master request control means and the other processing element master request control means. Communication control means for controlling the data exchange.