JP2906794B2 - Method of manufacturing wafer with insulating film and wafer with insulating film - Google Patents

Method of manufacturing wafer with insulating film and wafer with insulating film

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Publication number
JP2906794B2
JP2906794B2 JP33348391A JP33348391A JP2906794B2 JP 2906794 B2 JP2906794 B2 JP 2906794B2 JP 33348391 A JP33348391 A JP 33348391A JP 33348391 A JP33348391 A JP 33348391A JP 2906794 B2 JP2906794 B2 JP 2906794B2
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JP
Japan
Prior art keywords
film
wafer
insulating film
compound semiconductor
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33348391A
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Japanese (ja)
Other versions
JPH05166795A (en
Inventor
毅彦 谷
春典 坂口
彰二 隈
健 目黒
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、絶縁膜付き化合物半導
体結晶ウェハの製造方法及び絶縁膜付き化合物半導体結
晶ウェハに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor crystal wafer with an insulating film and a compound semiconductor crystal wafer with an insulating film.

【0002】[0002]

【従来の技術】化合物半導体は、ショットキーゲート電
界効果トランジスタ(MESFET)、高移動トランジ
スタ(HEMT)、ヘテロ接合バイポーラトランジスタ
(HBT)、種々の受光発光デバイスの作製に用いられ
ている。半導体表面・界面、すなわち、自由表面、半導
体−半導体界面、金属−半導体界面、絶縁体−半導体界
面は、あらゆる半導体デバイスの基本構成要素である。
ことに数多くの未結合種を持つ表面は、本質的に活性
で、外部の原子、分子、イオンを吸着し易く、そのため
表面の電子状態は変化する。そこで、表面を絶縁膜など
で覆い、未結合手を終端し、表面を不活性とする。半導
体デバイスは、半導体表面を使用するので、この表面不
活性化技術は非常に重要な技術である。
2. Description of the Related Art Compound semiconductors have been used in the fabrication of Schottky gate field effect transistors (MESFETs), high mobility transistors (HEMTs), heterojunction bipolar transistors (HBTs), and various light receiving and emitting devices. A semiconductor surface / interface, that is, a free surface, a semiconductor-semiconductor interface, a metal-semiconductor interface, and an insulator-semiconductor interface are basic components of any semiconductor device.
In particular, surfaces with a large number of unbound species are intrinsically active and tend to adsorb external atoms, molecules, and ions, thereby changing the electronic state of the surface. Therefore, the surface is covered with an insulating film or the like to terminate dangling bonds, and the surface is made inactive. Since semiconductor devices use a semiconductor surface, this surface passivation technique is a very important technique.

【0003】GaAs結晶は、表面が酸化されることに
より高密度の表面準位が形成されてしまう。このこと
が、GaAsではMIS構造を有するデバイスが製作を
阻む原因となっている。表面を安定化させる方法とし
て、光化学酸化、硫化物処理、セレン化処理等が提案さ
れているが、この表面を充分に安定化させる方法は未だ
見いだされていない。最近、硫化物処理を発展させ、表
面の安定化を高めた方法として、As2 3 膜をGaA
s結晶表面に堆積させる方法がE.Yablonovitch等によっ
て報告された。この方法は以下に示す5つの工程よりな
り、〜へと順に行われる。
[0003] The surface of a GaAs crystal is oxidized to form high-density surface states. This causes a device having a MIS structure to hinder fabrication of GaAs. As a method for stabilizing the surface, photochemical oxidation, sulfide treatment, selenization treatment and the like have been proposed, but a method for sufficiently stabilizing the surface has not yet been found. Recently, as a method of improving the surface stabilization by developing sulfide treatment, As 2 S 3 film is made of GaAs.
A method of depositing on s-crystal surfaces was reported by E. Yablonovitch et al. This method comprises the following five steps, which are performed in order from to.

【0004】H2 SO4 :H2 2 :H2 O=1:
8:500の溶液でエッチング、水洗 (NH4 2 S溶液に浸漬、水洗 アンモニア溶液に0.16M As2 3 を溶解した
溶液:CH3 OH=2:1の溶液に浸漬 スピン乾燥 290〜300 ℃で熱処理(空気雰囲気)
H 2 SO 4 : H 2 O 2 : H 2 O = 1:
Etching with 8: 500 solution, washing with water Dipping in (NH 4 ) 2 S solution, washing with water Dipping in a solution of 0.16 M As 2 S 3 dissolved in ammonia solution: CH 3 OH = 2: 1 Spin drying 290- Heat treatment at 300 ° C (air atmosphere)

【0005】[0005]

【発明が解決しようとする課題】ところで、前述したE.
Yablonovitch等のウェット処理でAs2 3 を堆積させ
てMISダイオードを作製した場合、そのCーV曲線
は、理想曲線から(数V)シフトしており、またヒステ
リシスも現れている。これは、GaAs基板と絶縁膜で
あるAs2 3 の界面準位が充分に低減されておらず、
また膜質の純度にも問題があるためである。このよう
に、未だGaAs基板上にMIS構造デバイスが作製で
きるだけの充分に低い界面準位密度を有する絶縁膜の堆
積方法は見つかっておらず、絶縁膜付きウェハは開発さ
れていない。
By the way, the aforementioned E.
When As 2 S 3 is deposited by a wet process such as Yablonovitch to produce a MIS diode, the CV curve is shifted (several volts) from the ideal curve, and hysteresis also appears. This is because the interface state between the GaAs substrate and the insulating film As 2 S 3 is not sufficiently reduced,
Also, there is a problem with the purity of the film quality. As described above, a method for depositing an insulating film having a sufficiently low interface state density that a MIS structure device can be formed on a GaAs substrate has not yet been found, and a wafer with an insulating film has not been developed.

【0006】本発明の目的は、前記した従来技術の課題
を解消し、絶縁膜−基板界面の界面準位密度をMIS構
造デバイスが完全に動作するために充分に低くすること
を可能にする絶縁膜付きウェハの製造方法及び絶縁膜付
きウェハを提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide an insulating film capable of lowering the interface state density at the insulating film-substrate interface sufficiently for the MIS structure device to operate completely. An object of the present invention is to provide a method for manufacturing a wafer with a film and a wafer with an insulating film.

【0007】[0007]

【課題を解決するための手段】本発明は、前記目的を達
成するために、GaAs等の III−V族化合物半導体結
晶ウェハ表面にAs2 3 絶縁膜をCVD法で堆積する
ものである。また、結晶ウェハ表面にAsを堆積し、そ
のAsを硫化水素ガス又はフッ化イオウガスと反応させ
てAs2 3 膜を形成するものである。さらに、結晶ウ
ェハ表面にチオフイン誘導体及びチオフェノール誘導体
のLangmuir-Blodgett 膜(以下「LB膜」という。)を
付着させ保護膜とし、実際に素子を作成する時点でこれ
を熱処理してAs2 3 膜を形成するものである。さら
にまた、結晶ウェハ表面にAs2 3 膜を形成し、これ
にCVD法等でSiO2 膜又はSiN膜を形成するもの
である。
The present invention SUMMARY OF THE INVENTION In order to achieve the above object, is to deposit the As 2 S 3 insulating film by the CVD method on the III-V compound semiconductor crystal wafer surface such as GaAs. Further, As is deposited on the surface of the crystal wafer, and the As is reacted with a hydrogen sulfide gas or a sulfur fluoride gas to form an As 2 S 3 film. Furthermore, Langmuir-Blodgett film of Chiofuin derivative and thiophenol derivatives crystal wafer surface (hereinafter referred to as "LB film".) By adhering a protective film, by heat-treating it at the time of actually create the element As 2 S 3 It forms a film. Furthermore, an As 2 S 3 film is formed on the surface of a crystal wafer, and a SiO 2 film or a SiN film is formed thereon by a CVD method or the like.

【0008】本発明において III−V族化合物半導体結
晶ウェハとしては、GaAs、InP又はGaPが挙げ
られる。
In the present invention, examples of the III-V compound semiconductor crystal wafer include GaAs, InP and GaP.

【0009】CVD法としては、高周波プラズマCVD
法,電子シンクロトロン共鳴プラズマCVD法等のプラ
ズマCVD法、熱分解CVD法、赤外線励起CVD法,
紫外線励起CVD法等の光励起CVD法がある。
As the CVD method, high frequency plasma CVD is used.
, Plasma CVD such as electron synchrotron resonance plasma CVD, thermal decomposition CVD, infrared excitation CVD,
There is a light excitation CVD method such as an ultraviolet excitation CVD method.

【0010】結晶ウェハ表面にAsを堆積させる方法と
しては、ウェハ表面をAsH3 ガス雰囲気中で熱処理し
てそのウェハ表面にAsを堆積する方法があり、そのA
sH 3 の他にAsCl3 ,As(C2 5 ),As(C
3 ),As(OC2 5 ),C2 9 AsH2 を用い
てもよい。また、真空中でウェハ表面にAsを蒸着して
もよい。
A method for depositing As on the surface of a crystal wafer;
The surface of the wafer with AsHThreeHeat treatment in a gas atmosphere
There is a method of depositing As on the wafer surface by
sH ThreeIn addition to AsClThree, As (CTwoHFive), As (C
HThree), As (OCTwoHFive), CTwoH9AsHTwoUsing
You may. In addition, As is deposited on the wafer surface in vacuum
Is also good.

【0011】フッ化イオウガスとしてはS2 4 ,SF
4 ,SF6 がある。
As the sulfur fluoride gas, S 2 F 4 , SF
4, there is a SF 6.

【0012】LB膜の層数は2分子層以上とすることが
よい。
The number of layers of the LB film is preferably two or more.

【0013】[0013]

【作用】前記構成により、 III−V族化合物半導体結晶
ウェハ表面に絶縁膜が良好に形成されることになり、ウ
ェハ表面が充分に安定化する。また、ウェハ表面にAs
2 3 膜を形成し、この上にSiO2 膜又はSiN膜を
形成することで、従来の技術の欄で述べたE.Yablonovit
ch等の方法でAs2 3 膜を形成した際に膜の絶縁性及
びウェハとの界面が形成されなくなる要因であるGaが
膜中に含まれても、そのAs2 3 膜のGaはSi
2 ,SiN膜中にパイルアップされる。
According to the above-mentioned structure, an insulating film is favorably formed on the surface of the III-V compound semiconductor crystal wafer, and the wafer surface is sufficiently stabilized. In addition, As
By forming a 2 S 3 film and forming a SiO 2 film or a SiN film thereon, E. Yablonovit described in the section of the prior art can be used.
even ch a factor that interface is not formed between the insulation and the wafer of film at the time of forming the As 2 S 3 film by a method such as Ga is contained in the film, Ga of the As 2 S 3 film Si
It is piled up in the O 2 , SiN film.

【0014】従って、絶縁膜−ウェハ界面の界面準位密
度はMIS構造デバイスが完全に動作するために充分に
低くなる。
Therefore, the interface state density at the interface between the insulating film and the wafer is sufficiently low for the MIS structure device to operate completely.

【0015】[0015]

【実施例】以下、本発明の実施例を説明する。Embodiments of the present invention will be described below.

【0016】(実施例1)n型(100)GaAs基板
を硫酸系エッチングした後、この表面にAsH 3 、H
2 Sを原料ガスとし電子シンクロトロン共鳴(ECR)
CVD法で絶縁膜であるAs2 3 膜を1000A堆積させ
た。そして、その基板にマスク蒸着によりAu電極を形
成し、また裏面にオーミック接触を取るためにIn−G
a半田を塗布して、MISダイオードを作製した。
(Example 1) After etching an n-type (100) GaAs substrate with a sulfuric acid system, the surface thereof was coated with AsH 3 , H
Electron synchrotron resonance (ECR) using 2 S as source gas
An As 2 S 3 film serving as an insulating film was deposited at 1000 A by a CVD method. Then, an Au electrode is formed on the substrate by mask evaporation, and an In-G
(a) Solder was applied to produce a MIS diode.

【0017】(実施例2)n型(100)GaAs基板
を硫酸系エッチングした後、この基板を加熱炉に入れて
AsH3 雰囲気中、 300℃で加熱した。次にH2 Sガス
を炉中に導入し、基板に堆積させたAsと反応させAs
2 3 膜を1000A堆積させた。そして、前記実施例1と
ほぼ同様のプロセスでMISダイオードを作製した。
Example 2 After an n-type (100) GaAs substrate was subjected to sulfuric acid etching, the substrate was placed in a heating furnace and heated at 300 ° C. in an AsH 3 atmosphere. Next, H 2 S gas is introduced into the furnace, and is reacted with As deposited on the substrate.
A 2 S 3 film was deposited at 1000A. Then, an MIS diode was manufactured in substantially the same process as in the first embodiment.

【0018】(実施例3)n型(100)GaAsウェ
ハを硫酸系エッチングし、純水で流水洗浄した。このあ
いだに純水の入った別の容器にエーテルを溶媒としたチ
オフイン誘導体及びチオフェノール誘導体溶液を数滴た
らし、水面に単分子膜を形成させた。流水洗浄中のウェ
ハを取り出し、単分子層膜に覆われた水面をよぎってウ
ェハを垂直上下させ数分子層からなるLB膜を形成し
た。次にLB膜付きウェハを水素、窒素あるいはアルゴ
ン雰囲気で 300℃から 400℃で熱処理を行う。これによ
り、LB膜の最上層は表面に付着した不純物と共に蒸発
し、下層は熱分解しウェハ表面のAsと化学反応し、ウ
ェハ表面にAs2 3 膜を形成させた。そして、前記実
施例1とほぼ同様のプロセスでMISダイオードを作製
した。
(Example 3) An n-type (100) GaAs wafer was subjected to sulfuric acid etching and washed with running pure water. During this time, several drops of a solution of a thiophene derivative and a thiophenol derivative using ether as a solvent were dropped into another container containing pure water to form a monomolecular film on the water surface. The wafer under running water washing was taken out, and the wafer was vertically moved up and down across the water surface covered with the monomolecular film to form an LB film composed of several molecular layers. Next, the wafer with the LB film is heat-treated at 300 to 400 ° C. in a hydrogen, nitrogen or argon atmosphere. Thus, the uppermost layer of the LB film is evaporated with impurities adhering to the surface, the lower layer is As and the chemical reaction of the thermal decomposed wafer surface to form a As 2 S 3 film on the wafer surface. Then, an MIS diode was manufactured in substantially the same process as in the first embodiment.

【0019】(実施例4)n型(100)GaAs基板
を硫酸系エッチングした後、まず、プラズマCVD法又
はE.Yablonovitch等のウェット処理法で、その基板表面
にAs2 3 膜を50A堆積し、次にこの上にプラズマC
VD法でSiO2 膜を 700A堆積した。そして、前記実
施例1とほぼ同様のプロセスでMISダイオードを作製
した。
(Example 4) After an n-type (100) GaAs substrate is subjected to sulfuric acid etching, a 50 A As 2 S 3 film is first deposited on the surface of the substrate by a plasma CVD method or a wet processing method such as E. Yablonovitch. And then plasma C
A 700 A SiO 2 film was deposited by the VD method. Then, an MIS diode was manufactured in substantially the same process as in the first embodiment.

【0020】(比較例)E.Yablonovitch等が行ったウェ
ット処理、As2 3 をソース(原料)とした真空蒸着
法でAs2 3 膜を 750A堆積し、前記実施例1とほぼ
同様のプロセスでMISダイオードを作製した。
(Comparative Example) 750 A of an As 2 S 3 film was deposited by a wet process performed by E. Yablonovitch et al. By a vacuum evaporation method using As 2 S 3 as a source (raw material). An MIS diode was manufactured by the process.

【0021】上述のようにして作製したMISダイオー
ドの評価をC−V特性及び絶縁膜質につていて行った。
尚、C−V特性は周波数1MHzで測定した。
The MIS diode fabricated as described above was evaluated for CV characteristics and insulating film quality.
The CV characteristics were measured at a frequency of 1 MHz.

【0022】その結果、実施例1〜4のダイオードは、
いずれもC−V特性が理想曲線とよく一致しており、ヒ
ステリシスも現れておらず、絶縁膜−基板界面の界面準
位密度が充分低く、またAs2 3 の膜質も良好であっ
た。
As a result, the diodes of Examples 1 to 4
In each case, the CV characteristics were in good agreement with the ideal curve, no hysteresis appeared, the interface state density at the interface between the insulating film and the substrate was sufficiently low, and the film quality of As 2 S 3 was good.

【0023】これに対して比較例では、そのC−V特性
が理想曲線から数ボルト(V)シフトしており、またヒ
ステリシスも現れていた。
On the other hand, in the comparative example, the CV characteristics were shifted from the ideal curve by several volts (V), and hysteresis also appeared.

【0024】また、前述の実施例1において熱分解CV
D法、高周波プラズマCVD法、紫外線励起CVD法、
レーザー励起CVD法についても同様の実験を行ったと
ころ、これらのCVD法においてもECRCVD法の場
合と同様にダイオードのC−V特性は良好であった。
又、実施例3において、SiO2 の代わりにSiNを堆
積した場合もSiO2 の場合と同様の結果が得られた。
In the first embodiment, the thermal decomposition CV
D method, high frequency plasma CVD method, ultraviolet excitation CVD method,
The same experiment was performed for the laser excitation CVD method, and the CV characteristics of the diode were good in these CVD methods as in the case of the ECRCVD method.
Further, in Example 3, if the case where SiN is deposited in place of SiO 2 in SiO 2 and similar results were obtained.

【0025】さらに、実施例4において、LB膜付着
後、ウェハを大気中に放置しても、ウェハ表面の酸化は
進まなかった。その大気中に放置したLB膜付きウェハ
を熱処理し、これにAs2 3 膜を形成させた後、前記
実施例1とほぼ同様のプロセスでMISダイオードを作
製し、そのC−V特性を測定した。その結果、理想曲線
とよく一致し、またヒステリシスを現れなかった。この
ようにLB膜は良好なウェハ表面保護膜になり、プロセ
ス段階において良好なAs2 3 膜が得られる。これは
例えばエピタキシャル成長とプロセスとの間に時間が開
く場合など特に有効になる。これは、エピタキシャル成
長させた化合物半導体結晶ウェハの場合、素子構造に合
わせた多層成長を行うため、前述のE.Yablonovitch等が
行ったウェット処理ののエッチングにより酸化膜を取
り除く方法を使えないことが多い。このため、ウェハ表
面の酸化を防ぐため、エピタキシャル成長後、前述の処
理をすぐに行わなければならない。そのエピタキシャル
成長と素子作成との間に時間があく場合、As2 3
表面に汚染が発生する。レーザダイオードやヘテロバイ
ポーラトランジツタなどの端面処理だけを目的とする素
子では、As2 3 膜表面に汚染が発生しても問題にな
らない。しかし、MIS構造のように、As 2 3
等の上に電極を形成するものは、その汚染により絶縁膜
と電極との界面の特性を劣化させてしまうため問題にな
る。
Further, in Example 4, even after the LB film was deposited, the wafer surface was not oxidized even if the wafer was left in the air. After heat-treating the wafer with the LB film left in the air and forming an As 2 S 3 film thereon, a MIS diode is manufactured in substantially the same process as in the first embodiment, and its CV characteristics are measured. did. As a result, it coincided well with the ideal curve, and no hysteresis appeared. Thus, the LB film becomes a good wafer surface protective film, and a good As 2 S 3 film can be obtained in the process stage. This is particularly effective when, for example, a time is opened between the epitaxial growth and the process. This is because, in the case of a compound semiconductor crystal wafer grown epitaxially, a method of removing an oxide film by wet etching performed by E. Yablonovitch or the like cannot be used in many cases because multi-layer growth according to the element structure is performed. . Therefore, in order to prevent oxidation of the wafer surface, the above-described processing must be performed immediately after the epitaxial growth. If time is required between the epitaxial growth and the device preparation, contamination occurs on the surface of the As 2 S 3 film. In a device such as a laser diode or a hetero-bipolar transistor for the purpose of treating only the end face, there is no problem even if contamination occurs on the surface of the As 2 S 3 film. However, an electrode formed on an As 2 S 3 film or the like, such as the MIS structure, causes a problem because the contamination deteriorates the characteristics of the interface between the insulating film and the electrode.

【0026】従って、本発明によれば III−V族化合物
半導体結晶ウェハ表面に良好の絶縁膜が形成されること
になり、絶縁膜−ウェハ界面の界面準位密度を充分に低
くした絶縁膜付きウェハが得られる。このため、その絶
縁膜付きウェハを用いることにより、良好なMIS構造
素子や電流リークの少ないMESFET,HEMT,H
BT,LD及びLEDを作製することができると共に、
それらの素子特性や歩留を大幅に向上することができ
る。
Therefore, according to the present invention, a good insulating film is formed on the surface of the group III-V compound semiconductor crystal wafer, and the insulating film having the sufficiently low interface state density at the insulating film-wafer interface is provided. A wafer is obtained. Therefore, by using the wafer with the insulating film, a good MIS structure element and MESFET, HEMT, H
BT, LD and LED can be manufactured,
These device characteristics and yield can be greatly improved.

【0027】[0027]

【発明の効果】以上要するに本発明によれば、 III−V
族化合物半導体結晶ウェハ表面に良好の絶縁膜が形成さ
れるので、絶縁膜−ウェハ界面の界面準位密度をMIS
構造デバイスが完全に動作するために充分に低くした絶
縁膜付きウェハが得られる。
In summary, according to the present invention, III-V
Since a good insulating film is formed on the surface of the group III compound semiconductor crystal wafer, the interface state density at the insulating film-wafer interface is set to MIS.
A wafer with an insulating film that is sufficiently low for the complete operation of the structural device is obtained.

フロントページの続き (72)発明者 目黒 健 茨城県土浦市木田余町3550番地 日立電 線株式会社アドバンスリサーチセンタ内 (56)参考文献 特開 平4−112520(JP,A) 特開 昭58−141576(JP,A) 特開 平5−102128(JP,A) 特開 昭62−240908(JP,A) 特開 平3−257972(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01L 21/314 JICSTファイル(JOIS)Continuation of the front page (72) Inventor Takeshi Meguro 3550 Kida Yomachi, Tsuchiura City, Ibaraki Prefecture Advanced Research Center, Hitachi Cable, Ltd. (56) References JP-A-4-112520 (JP, A) JP-A-58- 141576 (JP, A) JP-A-5-102128 (JP, A) JP-A-62-240908 (JP, A) JP-A-3-257972 (JP, A) (58) Fields investigated (Int. 6 , DB name) H01L 21/314 JICST file (JOIS)

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 GaAs等の III−V族化合物半導体結
晶ウェハ表面に絶縁膜であるAs2 3 をCVD法で堆
積することを特徴とする絶縁膜付きウェハの製造方法。
1. A method of manufacturing a wafer with an insulating film, comprising depositing As 2 S 3 as an insulating film on a surface of a III-V group compound semiconductor crystal wafer such as GaAs by a CVD method.
【請求項2】 GaAs等の III−V族化合物半導体結
晶ウェハ表面に、Asを堆積し、その堆積したAsを硫
化水素ガス又はフッ化イオウガスと反応させてAs2
3 膜を形成することを特徴とする絶縁膜付き化合物半導
体結晶ウェハの製造方法。
2. As is deposited on the surface of a III-V compound semiconductor crystal wafer such as GaAs, and the deposited As is reacted with a hydrogen sulfide gas or a sulfur fluoride gas to produce As 2 S.
A method for producing a compound semiconductor crystal wafer with an insulating film, comprising forming three films.
【請求項3】 GaAs等の III−V族化合物半導体結
晶ウェハ表面に、チオフイン誘導体あるいはチオフェノ
ール誘導体のLangmuir-Blodgett 膜を付着させ、その
後、これを熱処理してAs2 3 膜を形成することを特
徴とする絶縁膜付きウェハの製造方法。
3. A method of depositing a Langmuir-Blodgett film of a thioin derivative or a thiophenol derivative on the surface of a III-V compound semiconductor crystal wafer of GaAs or the like, followed by heat treatment to form an As 2 S 3 film. A method for manufacturing a wafer with an insulating film, comprising:
【請求項4】 GaAs等の III−V族化合物半導体結
晶ウェハ表面にAs2 3 膜を形成し、この表面にSi
2 膜を形成したことを特徴とする絶縁膜付きウェハ。
4. An As 2 S 3 film is formed on the surface of a III-V group compound semiconductor crystal wafer such as GaAs, and Si is formed on the surface.
A wafer with an insulating film, wherein an O 2 film is formed.
【請求項5】 GaAs等の III−V族化合物半導体結
晶ウェハ表面にAs2 3 膜を形成し、この表面にSi
N膜を形成したことを特徴とする絶縁膜付きウェハ。
5. An As 2 S 3 film is formed on the surface of a III-V group compound semiconductor crystal wafer such as GaAs, and Si
A wafer with an insulating film, wherein an N film is formed.
JP33348391A 1991-12-17 1991-12-17 Method of manufacturing wafer with insulating film and wafer with insulating film Expired - Fee Related JP2906794B2 (en)

Priority Applications (1)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33348391A JP2906794B2 (en) 1991-12-17 1991-12-17 Method of manufacturing wafer with insulating film and wafer with insulating film

Publications (2)

Publication Number Publication Date
JPH05166795A JPH05166795A (en) 1993-07-02
JP2906794B2 true JP2906794B2 (en) 1999-06-21

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