JP2900512B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JP2900512B2
JP2900512B2 JP2114411A JP11441190A JP2900512B2 JP 2900512 B2 JP2900512 B2 JP 2900512B2 JP 2114411 A JP2114411 A JP 2114411A JP 11441190 A JP11441190 A JP 11441190A JP 2900512 B2 JP2900512 B2 JP 2900512B2
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JP
Japan
Prior art keywords
chip
layer
transistor
semiconductor device
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2114411A
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Japanese (ja)
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JPH0411762A (en
Inventor
英生 釜掘
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NEC Corp
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Nippon Electric Co Ltd
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Priority to JP2114411A priority Critical patent/JP2900512B2/en
Publication of JPH0411762A publication Critical patent/JPH0411762A/en
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Publication of JP2900512B2 publication Critical patent/JP2900512B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/30111—Impedance matching

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に高周波高出力トラン
ジスタを実装するハイブリッド構成の半導体装置とその
製造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a hybrid configuration in which a high-frequency high-output transistor is mounted and a method of manufacturing the same.

〔従来の技術〕[Conventional technology]

従来、高周波高出力トランジスタを実装するハイブリ
ッド構成の半導体装置では、インピーダンス整合回路を
含ませることが多い。例えば、ベース接地トランジスタ
を実装する場合には、トランジスタの出力側のコレクタ
・ベース間に直列のLC回路を挿入してインピーダンスを
変換している。通常、Ｌ（インダクタンス）はボンディ
ングワイヤにより構成し、Ｃ（キャパシタンス）はコン
デンサチップによって構成している。Conventionally, a semiconductor device having a hybrid configuration in which high-frequency high-output transistors are mounted often includes an impedance matching circuit. For example, when a common-base transistor is mounted, a series LC circuit is inserted between the collector and the base on the output side of the transistor to convert the impedance. Usually, L (inductance) is constituted by a bonding wire, and C (capacitance) is constituted by a capacitor chip.

第３図はこの種の半導体装置の一例を示しており、ベ
リリア基板31上にモリブデン層32を形成し、この上にニ
ッケルおよび金の２層構造のメタライズ層33,34を形成
する。また、ベリリア基板31の他の領域には絶縁層35を
形成し、その上にメタライズ層36を形成する。FIG. 3 shows an example of this type of semiconductor device, in which a molybdenum layer 32 is formed on a beryllia substrate 31, and a metallized layer 33, 34 having a two-layer structure of nickel and gold is formed thereon. Further, an insulating layer 35 is formed in another region of the beryllia substrate 31, and a metallized layer 36 is formed thereon.

そして、前記メタライズ層33に0.5〜2mm角程度のトラ
ンジスタチップTRと0.5〜2mm角程度のコンデンサチップ
Ｃを搭載し、メタライズ層34にコンデンサチップＣを搭
載し、メタライズ層36に入力端子37,出力端子38をそれ
ぞれ接続する。しかる上で、トランジスタチップTRおよ
びコンデンサチップＣをそれぞれ前記メタライズ層33,3
4,36にボンディングワイヤ39で接続している。Then, a transistor chip TR of about 0.5 to 2 mm square and a capacitor chip C of about 0.5 to 2 mm square are mounted on the metallization layer 33, the capacitor chip C is mounted on the metallization layer 34, the input terminal 37 is provided on the metallization layer 36, and the output is provided. Terminals 38 are connected respectively. Then, the transistor chip TR and the capacitor chip C are respectively connected to the metallization layers 33 and 3.
4, 36 are connected by bonding wires 39.

この構成により、コンデンサチップＣでキャパシタン
スを構成し、ボンディングワイヤ39でインダクタンスを
構成し、所要のLCインピーダンス回路を構成している。With this configuration, the capacitance is constituted by the capacitor chip C, the inductance is constituted by the bonding wires 39, and the required LC impedance circuit is constituted.

なお、トランジスタチップTRとコンデンサチップＣを
交互に搭載しているが、これは第１に熱の発生源となる
トランジスタチップを分散させることにより熱抵抗を低
くおさえるためであり、第２にインピーダンス整合回路
素子をトランジスタチップ間に入れてやることにより寄
生容量，抵抗が生じることなく各トランジスタに均一に
働かせるためである。この構成により、各トランジスタ
の高周波動作は均一になり高い出力電力が得られる。The transistor chips TR and the capacitor chips C are alternately mounted. The first reason is to reduce the thermal resistance by dispersing the transistor chips that generate heat, and the second is to match the impedance matching. By inserting circuit elements between the transistor chips, parasitic capacitance and resistance do not occur, so that they work uniformly for each transistor. With this configuration, the high-frequency operation of each transistor is uniform, and high output power is obtained.

また、コンデンサチップＣにセラミックコンデンサを
用いているが、これはMIS構造を用いたコンデンサにく
らべ、セラミックコンデンサの方が高周波での損失が少
ないからである。In addition, a ceramic capacitor is used for the capacitor chip C, because a ceramic capacitor has less loss at high frequencies than a capacitor using the MIS structure.

なお、この種の一例として、特開昭53−12271号に開
示されたものがある。One example of this type is disclosed in Japanese Patent Application Laid-Open No. 53-12271.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

ところで、前記したトランジスタチップTRをメタライ
ズ層33に搭載するためには、コレクタとして構成されて
いるトランジスタチップTRの裏面とメタライズ層とのコ
ンタクトのオーミック特性を得るために、そのロー材に
はAuSbを用いている。一方、セラミックで構成されるコ
ンデンサチップＣをメタライズ層33,34に搭載するため
には、熱的疲労による熱抵抗の損失を低減するためにAu
Siを用いている。By the way, in order to mount the above-described transistor chip TR on the metallization layer 33, in order to obtain ohmic characteristics of the contact between the back surface of the transistor chip TR configured as a collector and the metallization layer, AuSb is used for the brazing material. Used. On the other hand, in order to mount the capacitor chip C made of ceramic on the metallized layers 33 and 34, Au is required to reduce the loss of thermal resistance due to thermal fatigue.
Si is used.

したがって、同一のメタライズ層上でAuSbとAuSiの異
なるロー材が使用されることになり、これらのロー材が
溶融時にメタライズ層上で混合されてしまう。このた
め、混合されたロー材がトランジスタチップTRの裏面に
侵入されたときには、トランジスタにおけるコレクタの
オーミック特性がばらつき、半導体装置の特性が劣化さ
れるという問題がある。Therefore, different brazing materials of AuSb and AuSi are used on the same metallized layer, and these brazing materials are mixed on the metallized layer at the time of melting. For this reason, when the mixed brazing material enters the back surface of the transistor chip TR, there is a problem that the ohmic characteristics of the collector of the transistor vary, and the characteristics of the semiconductor device are deteriorated.

本発明の目的は異なるロー材の混合を防止した半導体
装置とその製造方法を提供することにある。An object of the present invention is to provide a semiconductor device in which mixing of different brazing materials is prevented and a method of manufacturing the same.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の半導体装置は、トランジスタチップとコンデ
ンサチップを並んで搭載するメタライズ層の、トランジ
スタチップとコンデンサチップの間に、異なるロー材の
混合を防止するためのロー材をはじく領域を設けてい
る。In the semiconductor device of the present invention, a region for repelling a brazing material for preventing mixing of different brazing materials is provided between the transistor chip and the capacitor chip of the metallization layer on which the transistor chip and the capacitor chip are mounted side by side.

例えば、ロー材をはじく領域は、メタライズ層の下側
にロー材をはじく材料層を形成するとともに、メタライ
ズ層の表面に溝を形成して該ロー材をはじく材料層を露
出させた構成とする。For example, the region that repels the brazing material has a structure in which a material layer that repels the brazing material is formed below the metallized layer, and a groove is formed on the surface of the metallized layer to expose the material layer that repels the brazing material. .

また、ロー材をはじく領域は、メタライズ層に溝を形
成し、この溝内にロー材をはじく材料を充填し、かつこ
の材料をメタライズ層の表面上に突出させた構成とす
る。In the region where the brazing material is repelled, a groove is formed in the metallized layer, a material for repelling the brazing material is filled in the groove, and this material is projected on the surface of the metallized layer.

また、本発明の半導体装置の製造方法は、同一のメタ
ライズ層に、トランジスタチップとコンデンサチップと
の各搭載領域の境界に沿ってロー材をはじく材料を充填
し、前記各搭載領域に前記トランジスタチップと前記コ
ンデンサチップをそれぞれ異なるロー材を用いて前記メ
タライズ層に接着し、ハイブリッド構成の半導体装置を
形成する工程を含むことを特徴とする。The method of manufacturing a semiconductor device according to the present invention may further comprise filling the same metallization layer with a material that repels a brazing material along a boundary between the mounting areas of the transistor chip and the capacitor chip, and filling the mounting area with the transistor chip. And bonding the capacitor chip and the capacitor chip to the metallized layer using different brazing materials to form a semiconductor device having a hybrid configuration.

〔作用〕[Action]

本発明によれば、異なるロー材はメタライズ層に設け
たロー材をはじく領域によって相互の混合が防止され、
特に混合されたロー材がトランジスタチップの搭載面に
影響することが防止される。According to the present invention, different brazing materials are prevented from being mixed with each other by a region for repelling the brazing material provided in the metallized layer,
In particular, the mixed brazing material is prevented from affecting the mounting surface of the transistor chip.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第１図は本発明の第１実施例の斜視図である。厚さ1m
m程度，大きさが５〜10mm角程度のベリリア基板１上の
両端部を除く領域にモリブテン，マンガン等のロー材を
はじく金属層２を20μｍ程度の厚さに形成する。さら
に、この金属層２の上に素子搭載用メタライズ層３およ
び４をメッキ法によりそれぞれ所要領域に形成する。こ
のメッキ法によるメタライズ層3,4の形成に際しては、
ニッケルを２μｍ程度被着し、その上に金を２μｍ程度
被着することにより形成される。また、前記ベリリア基
板１の両端部には絶縁層５を形成し、この絶縁層５には
同様にして端子用メタライズ層６を形成する。FIG. 1 is a perspective view of a first embodiment of the present invention. 1m thick
A metal layer 2 repelling a brazing material such as molybdenum or manganese is formed to a thickness of about 20 μm in a region except for both ends on the beryllia substrate 1 having a size of about 5 m and a size of about 5 to 10 mm square. Further, element mounting metallized layers 3 and 4 are formed on the metal layer 2 in required areas by plating, respectively. When forming the metallized layers 3 and 4 by this plating method,
It is formed by depositing nickel on the order of 2 μm and depositing gold on it on the order of 2 μm. An insulating layer 5 is formed on both ends of the beryllia substrate 1, and a terminal metallization layer 6 is formed on the insulating layer 5 in the same manner.

前記素子搭載用メタライズ層３上には、トランジスタ
チップTRとコンデンサチップＣを交互位置に搭載する。
また、メタライズ層上にはコンデンサチップＣを搭載す
る。さらに、端子用メタライズ層６には入力端子７と出
力端子８をそれぞれ接続している。そして、前記トラン
ジスタチップTR,コンデンサチップＣと、前記各メタラ
イズ層3,4,6との間をボンディングワイヤ９で相互に接
続している。On the element mounting metallization layer 3, transistor chips TR and capacitor chips C are mounted at alternate positions.
The capacitor chip C is mounted on the metallization layer. Further, an input terminal 7 and an output terminal 8 are connected to the terminal metallization layer 6, respectively. The transistor chip TR, the capacitor chip C, and the metallization layers 3, 4, and 6 are interconnected by bonding wires 9.

ここで、前記トランジスタチップTRとコンデンサチッ
プＣを搭載するメタライズ層３では、各チップの搭載領
域の境界線に沿った部分には、前記した素子搭載用のメ
ッキを施さず、前記金属層２を露出させた溝領域10を形
成する。この溝領域10は、例えばメタライズ層３の全幅
にわたって100μｍ程度の幅で形成する。そして、この
溝領域10で分離されるメタライズ層3a〜3d上に、トラン
ジスタチップTRとコンデンサチップＣをそれぞれ搭載し
ているが、トランジスタチップTRの搭載にはコンタクト
のオーミック特性を良くするためにロー材としてAuSbを
用いており、コンデンサチップＣの搭載にはロー材とし
てAuSiを用いている。Here, in the metallization layer 3 on which the transistor chip TR and the capacitor chip C are mounted, portions along the boundary of the mounting area of each chip are not subjected to the plating for mounting the element, and the metal layer 2 is coated. An exposed groove region 10 is formed. The groove region 10 is formed with a width of about 100 μm over the entire width of the metallized layer 3, for example. The transistor chip TR and the capacitor chip C are mounted on the metallized layers 3a to 3d separated by the groove region 10, respectively. AuSb is used as the material, and AuSi is used as the brazing material for mounting the capacitor chip C.

この構成によれば、トランジスタチップTRとコンデン
サチップＣの搭載時に、それぞれのロー材がメタライズ
層3a〜3d上で流動されても、各ロー材は溝領域10におい
て金属層２によってはじかれるため、各ロー材が溝領域
10を越えて隣接するメタライズ層3a〜3dに進入し、相互
に混合されることはない。これにより、異なるロー材が
混合されることが原因とされるトランジスタチップTRに
おけるコンタクトのオーミック特性が損なわれることが
防止される。According to this configuration, even when each row material flows on the metallized layers 3a to 3d when the transistor chip TR and the capacitor chip C are mounted, each row material is repelled by the metal layer 2 in the groove region 10, Each brazing material has a groove area
Over 10 adjacent metallization layers 3a to 3d enter and are not mixed with each other. This prevents the ohmic characteristics of the contacts in the transistor chip TR from being impaired due to the mixing of different brazing materials.

第２図は本発明の第２実施例の断面図である。 FIG. 2 is a sectional view of a second embodiment of the present invention.

同図に示すように、ベリリア基板21上にモリブテン層
22を10μｍメタライズし、その上にニッケル層23を１μ
ｍメタライズし、さらにその上に金層24を２μｍメタラ
イズしてメタライズ層を形成する。そして、金層24およ
びニッケル層23には、メタライズ層を分離させる幅0.1m
mの溝25を形成し、この溝25内にアルミナ膜26をコーテ
ィングし、溝25内に充填するとともにその上端をメタラ
イズ層の表面上に突出させている。そして、このアルミ
ナ膜26によってそれぞれ分離された金24上に、0.7mm角
トランジスタチップTRと0.5mm角コンデンサチップＣを
それぞれ個別のロー材で搭載している。As shown in the figure, a molybdenum layer
22 is metallized 10 μm, and a nickel layer 23 is
m metallized, and a metallized layer is formed thereon by metallizing the gold layer 24 by 2 μm. The gold layer 24 and the nickel layer 23 have a width of 0.1 m for separating the metallized layer.
An m-shaped groove 25 is formed, an alumina film 26 is coated in the groove 25, the groove 25 is filled, and the upper end of the groove 25 is projected above the surface of the metallized layer. Then, on the gold 24 separated by the alumina film 26, a 0.7 mm square transistor chip TR and a 0.5 mm square capacitor chip C are mounted with individual brazing materials.

この実施例においても、トランジスタチップTRとコン
デンサチップＣを搭載するための各ロー材がアルミナ26
によってはじかれるため、相互に混合されることはな
く、トランジスタチップTRにおけるコンタクトのオーミ
ック特性の劣化が防止される。Also in this embodiment, each brazing material for mounting the transistor chip TR and the capacitor chip C is made of alumina 26.
Therefore, they are not mixed with each other, and the deterioration of the ohmic characteristics of the contacts in the transistor chip TR is prevented.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、トランジスタチップと
コンデンサチップを搭載するメタライズ層にロー材をは
じく領域を設けているので、異なるロー材が相互に混合
されることが防止され、特に混合されたロー材がトラン
ジスタチップの搭載面に影響してそのオーミック特性が
ばらつき、半導体装置の特性劣化が生じることを防止す
る効果がある。As described above, according to the present invention, since a region for repelling the brazing material is provided in the metallization layer on which the transistor chip and the capacitor chip are mounted, different brazing materials are prevented from being mixed with each other, and in particular, the mixed brazing material is prevented. The material has an effect of preventing the ohmic characteristics from fluctuating due to the influence of the material on the mounting surface of the transistor chip and the deterioration of the characteristics of the semiconductor device.

また、本発明の製造方法では、同一メタライズ層のト
ランジスタチップとコンデンサチップの搭載領域の境界
に沿ってロー材をはじく領域を形成しているので、トラ
ンジスタチップとコンデンサチップのそれぞれ異なるロ
ー材が混合されずに、各チップを好適に搭載することが
可能となる。Further, in the manufacturing method of the present invention, since the region where the brazing material is repelled is formed along the boundary of the mounting region of the transistor chip and the capacitor chip of the same metallization layer, different brazing materials of the transistor chip and the capacitor chip are mixed. Instead, each chip can be suitably mounted.

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明の第１実施例の斜視図、第２図は本発明
の第２実施例の断面図、第３図は従来の半導体装置の斜
視図である。 １……ベリリア基板、２……金属層、3,4……メタライ
ズ層、５……絶縁層、６……メタライズ層、７……入力
端子、８……出力端子、９……ボンディングワイヤ、10
……溝領域、21……ベリリア基板、22……モリブデン
層、23……ニッケル層、24……金層、25……溝、26……
アルミナ膜、31……ベリリア基板、32……モリブデン
層、33,34……メタライズ層、35……絶縁層、36……メ
タライズ層、37……入力端子、38……出力端子、39……
ボンディングワイヤ、TR……トランジスタチップ、Ｃ…
…コンデンサチップ。FIG. 1 is a perspective view of a first embodiment of the present invention, FIG. 2 is a sectional view of a second embodiment of the present invention, and FIG. 3 is a perspective view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1 ... Beryllia board, 2 ... Metal layer, 3, 4 ... Metallization layer, 5 ... Insulating layer, 6 ... Metallization layer, 7 ... Input terminal, 8 ... Output terminal, 9 ... Bonding wire, Ten
... groove region, 21 ... beryllia substrate, 22 ... molybdenum layer, 23 ... nickel layer, 24 ... gold layer, 25 ... groove, 26 ...
Alumina film, 31 ... beryllia substrate, 32 ... molybdenum layer, 33, 34 ... metallized layer, 35 ... insulating layer, 36 ... metallized layer, 37 ... input terminal, 38 ... output terminal, 39 ...
Bonding wire, TR ... Transistor chip, C ...
... capacitor chip.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】トランジスタチップとコンデンサチップと
をそれぞれ異なるロー材を用いて同一のメタライズ層上
に並んで搭載してなるハイブリッド構成の半導体装置に
おいて、前記トランジスタと前記コンデンサチップとの
間のメタライズ層に溝を形成し、前記溝にロー材をはじ
く材料を充填し、かつ前記ロー材をはじく材料を前記メ
タライズ層の表面上に突出させてなることを特徴とする
半導体装置。2. A semiconductor device having a hybrid structure in which a transistor chip and a capacitor chip are mounted side by side on the same metallization layer using different brazing materials, respectively, wherein a metallization layer between the transistor and the capacitor chip is provided. A semiconductor device, wherein a groove is formed in the groove, the groove is filled with a material that repels a brazing material, and the material that repels the brazing material is projected on the surface of the metallized layer. 【請求項２】同一のメタライズ層にトランジスタチップ
とコンデンサチップとの各搭載領域の境界に沿って溝を
形成し、前記溝にロー材をはじく材料を充填し、かつ前
記メタライズ層表面上に突出させた後に、前記トランジ
スタチップと前記コンデンサチップをそれぞれ異なるロ
ー材を用いて前記メタライズ層に接着し、ハイブリッド
構成の半導体装置を形成する工程を含むことを特徴とす
る請求項１の半導体装置の製造方法。2. A groove is formed in the same metallization layer along a boundary between respective mounting areas of a transistor chip and a capacitor chip, and the groove is filled with a material repelling a brazing material, and protrudes above the surface of the metallization layer. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of bonding the transistor chip and the capacitor chip to the metallized layer using different brazing materials to form a semiconductor device having a hybrid structure. Method.
JP2114411A 1990-04-28 1990-04-28 Semiconductor device and manufacturing method thereof Expired - Lifetime JP2900512B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2114411A JP2900512B2 (en) 1990-04-28 1990-04-28 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2114411A JP2900512B2 (en) 1990-04-28 1990-04-28 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0411762A JPH0411762A (en) 1992-01-16
JP2900512B2 true JP2900512B2 (en) 1999-06-02

Family

ID=14637019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2114411A Expired - Lifetime JP2900512B2 (en) 1990-04-28 1990-04-28 Semiconductor device and manufacturing method thereof

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Country Link
JP (1) JP2900512B2 (en)

Also Published As

Publication number Publication date
JPH0411762A (en) 1992-01-16

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