JP2895025B2 - Operation and maintenance cell generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchronous Tran) using an asynchronous transfer mode.
OAM (OAM), which is an operation and maintenance cell used for monitoring and controlling the ATM layer network in a sfer mode (Sfer Mode) network.
peration and Maintenance)
The present invention relates to an operation and maintenance cell generation method for inserting cells.

[0002]

2. Description of the Related Art For monitoring and controlling an ATM layer network, A
IS (Alarm Indication Signa)
l) Cell or RDI (Remote Defect I)
An alarm transfer method using an OAM cell called an “nication” cell is defined in international standards such as ITU. In the ATM network, an exchange that detects a line failure sends out an AIS cell of one cell per second in the upstream direction, and the upstream side knows that the line is in a failure state by receiving the AIS cell. Cell for 2.5 seconds (± 0.5 seconds)
If not received, it is possible to know that the fault has been cleared. When the upstream exchange detects the AIS, it transmits one cell RDl per second in the downstream direction. On the downstream side, the reception of the RDl cell indicates that the upstream line is in a failure state. The cell is allowed to stand for 2.5 seconds (± 0.5
Second) If you do not receive it, you can know that the fault has been cleared.

At a virtual path level, which is one sublayer of the ATM layer, a VP-AIS cell or a VP-R
An OAM cell called a DI cell is used. On the other hand, at the virtual channel level, which is the other sublayer, O-cells called VC-AIS cells or VC-RDI cells are called.
AM cells are used.

A conventional example of an operation and maintenance cell generation method in an ATM network is described in Japanese Patent Application Laid-Open No. 4-181839. FIG. 9 is a block diagram showing a conventional operation and maintenance cell generation method, FIG. 10 is a time chart for explaining the operation of FIG. 9, and FIG. 11 is a diagram showing the positioning in the ATM exchange of FIG. is there.

The conventional operation / maintenance cell generation system shown in FIG. 9 employs an optical signal reception circuit 20, a cell synchronization circuit 21, a link failure detection circuit 22, a VP-AIS cell transmission interval control circuit 2
3, table scanning circuit 24, VP table 25, VP-
It comprises an AIS cell generation circuit 26, a selection circuit 27, and an empty cell generation circuit 28.

This operation will be described with reference to FIGS. 9 and 10. When a link failure occurs, the table scanning circuit 24 is started immediately, and each word of the VP table 25 is sequentially scanned from the head address. When a virtual path corresponding to each word is used, a VP-AIS cell is transmitted. . This operation is repeated until the last address of the VP table 25 is scanned. After scanning the last address,
One second is measured by a counter inside the VP-AIS cell transmission interval control circuit 23. During this time, empty cells generated by the cell generation circuit are sent to the output link.

After sending empty cells for one second, the table scanning circuit 24 is activated to sequentially scan each word of the VP table 25 from the start address. When a virtual path corresponding to each word is used, the VP-AIS cell is used. Is sent. This operation is repeated until the last address of the VP table 25 is scanned. After scanning the last address, VP-
One second is measured again by the counter inside the AIS cell transmission interval control circuit 23. During this time, the empty cell generated by the empty cell generating circuit 28 is sent to the output link.

As shown in FIG. 11, the conventional operation and maintenance cell generation method is arranged on a line basis.

[0009]

In such a conventional operation / maintenance cell generation system, when an operation / maintenance cell generation system is provided for each line, when a link failure occurs, all the cells in use every second are used. VP- 1 cell per virtual path
It is excellent in that it can transmit AIS cells.

However, if the operation and maintenance cell generation circuit is provided for each line, there is a problem that the line corresponding portion of the ATM exchange becomes large.

Conventionally, M operation / maintenance cell generation circuits are required when an M line is accommodated in a switch port of an ATM exchange. This is because if the operation and maintenance cell generation circuit is provided after multiplexing the M lines, only one operation and maintenance cell generation circuit is required.

When a conventional operation / maintenance cell generation circuit is provided after the M lines are multiplexed, a. It is necessary to send a large number of VP-AIS cells up to 4096 × M cells. b. Since the number of simultaneously faulty lines among the M lines is different, the received valid cells cannot be discarded, and it is necessary to insert a VP-AIS when receiving invalid cells. Under such conditions, it becomes difficult to transmit VP-AIS cells one cell per second to all virtual paths multiplexed on each line.

Since the number of simultaneously faulty lines of a plurality of lines and the total number of virtual paths used differ from time to time,
During the occurrence of a failure, the time variation until the transmission of the VP-AIS cell is completed for each virtual path one cell at a time becomes large, and the transmission completion of the worst VP-AIS cell exceeds 1 second at worst. This makes it difficult to transmit VP-AIS cells one cell per second.

The present invention has been made in order to solve the problems, and even when a failure of a plurality of lines or a failure of a virtual path line of a plurality of virtual paths occurs, an average of one per second occurs.
An object of the present invention is to provide a small operation and maintenance cell generation method while providing cell operation and maintenance (OAM) cell transmission.

[0015]

According to the present invention, in order to solve the above-mentioned problems of the conventional example, one second time is repeatedly counted autonomously irrespective of a line failure occurrence timing, a VP-AIS cell insertion timing, and the like. A 1-second timer counter that outputs a 1-second elapsed signal, and 1
The line number and VPI of the memory with the second elapsed signal as the start instruction
Insertion identifier search means for autonomously searching for insertion identifiers from the youngest number to the oldest number (last number) and stopping when searching for the oldest number, and the insertion identifier when a one-second elapsed signal is received from a one-second timer counter If the state of the search means is monitored and the search is not completed up to the old number (final number) consecutively N times, the state monitor means after 1 second for instructing to start the search from the young number even during the search, It is characterized by having.

Further, the present invention is characterized in that the operation and maintenance cell generation of the present invention is provided at a stage after M lines are multiplexed by accommodating M lines in the line corresponding portion of the ATM exchange.

According to the present invention, the one-second timer counter autonomously repeats the one-second time independently of the line failure occurrence timing and the VP-AIS cell insertion timing, and outputs a one-second elapsed signal to search for the insertion identifier. By means of a one-second elapsed signal as a start instruction, the line number of memory and VP
The insertion identifiers from the youngest number to the oldest number (the last number) of the l-number are autonomously searched, and when the oldest number is searched, the operation is stopped. Monitoring the state of the insertion identification search means upon receipt of the search result, it is determined that the search is not completed until the old number (final number).
By instructing to search from the youngest number in the middle of the search after successive times, even if a failure of multiple lines or a path failure of multiple virtual paths occurs, the average is 1 per second.
Cell operation and maintenance (OAM) cell transmission can be performed.

Further, according to the present invention, M lines are accommodated in a line-corresponding portion of an ATM exchange, and the operation-maintenance cell generation of the present invention is provided after the M-line is multiplexed, whereby the line-corresponding portion of the ATM exchange is downsized. It is possible.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the operation and maintenance cell generation system according to the present invention. The operation and maintenance cell generation method shown in FIG.
Each line fault state holding means 3, memory 4, one-second timer counter 5, insertion identifier searching means 6, cell generation means 7, invalid cell detection & cell insertion means 8, state after elapse of one second And a monitoring means 9.

Next, the operation of the embodiment shown in FIG. 1 will be described. In FIG. 1, a physical layer terminating means 1 detects a normal / failed line state and outputs an invalid cell when the line is in a failed state. Multiplexing 2 multiplexes a plurality of lines to be accommodated into one line. Each line fault state holding means 3
Holds the line state (normal state / failure state) of a plurality of accommodated lines detected by the physical layer terminating means 1.
The memory 4 holds an insertion identifier indicating whether or not to insert an OAM cell and a state of the virtual path line (normal state / failure state). The one-second timer counter 5 autonomously repeats the one-second time and outputs a one-second elapsed signal. The insertion identifier searching means 6 uses the one-second elapsed signal from the one-second timer counter 5 as a start instruction,
The insertion identifiers from the youngest number to the oldest number (last number) are independently searched, and when the oldest number (last number) is searched, the operation is stopped.
The cell generation means 7 generates an OAM cell based on the data in the memory 4 searched by the insertion identifier means 6 and the data in each line fault state holding means 3. The invalid cell detection & cell insertion means 8 detects a valid cell / invalid cell of the received ATM cell, and when the invalid cell is detected, the cell generation means 7
Is inserted. The one-second elapsed state monitoring means 9 monitors the state of the insertion identification search means 6 when a one-second elapsed signal is received from the one-second timer counter 5 and searches when the search is not completed up to the old number (last number). Instructs the search to be forcibly started from the youngest even during the process.

[0022]

Next, a first embodiment of the present invention will be described with reference to FIG.

In FIG. 1, the physical layer terminating means 1 detects a normal / failure state of a line state, and outputs an invalid cell when the line is in a failure state.

Multiplexing 2 multiplexes the accommodated M lines into one line. Each line fault state holding means 3 holds the line state (normal state / fault state) detected by the physical layer terminating means 1 arranged in each of the accommodated M lines in real time.

The memory 4 is composed of M × 4096 words corresponding to M lines accommodated in 4096 words per line, and each word has an insertion flag indicating whether or not a VP-AIS cell is inserted during a line failure. Hold. FIG. 4 shows a table configuration in the memory 4.

The one-second timer counter 5 autonomously repeats the one-second time irrespective of the occurrence timing of a line failure, the timing of inserting a VP-AIS cell, and outputs a one-second elapsed signal.

The insertion identifier search means 6 uses the one-second elapsed signal from the one-second timer counter 5 as a start instruction and starts address “M × 4096-1” from address “0” in the memory 4.
Autonomously searches for insertion identifiers up to the address “M × 40”.
When the search reaches 96-1 ", the operation is stopped.

The cell generation means 7 checks whether the insertion flag of the VP-AIS cell searched by the insertion identifier means 6 is a valid line number and VPI number and the state of the line held in each line fault state holding means 3 is In a failure state, a VP-AIS cell is generated based on the corresponding line number and the corresponding VPI.

The invalid cell detection & cell insertion means 8 detects a valid cell / invalid cell of the received ATM cell, and when an invalid cell is detected, generates the VP-
Insert AIS cell.

When a one-second elapsed signal is received from the one-second timer counter 5, the state monitoring means 9 monitors the state of the insertion identifier retrieving means 6 and receives the address "M.times.4096-
If the search is not completed up to the first number N times consecutively, it is instructed to start the search from the address "0" even during the search.

Next, the operation of the first embodiment will be described. The physical layer terminating means 1 detects a normal / failure state of the line state, outputs a line state signal to each line failure state holding means 3, and when the state is normal, the received ATM cell is directly transmitted to the multiplexing unit 2. And outputs an invalid cell to the multiplexing unit 2 in a failure state.

In multiplexing 2, the ATM cells output from the physical layer terminating means 1 of each line at the preceding stage are multiplexed on one line and output.

Each line fault state holding means 3 holds the line state signal output from the physical layer terminating means 1 of each of the accommodated M lines in real time so that the line state of each line (normal state / fault state). Is displayed.

The memory 4 is composed of M × 4096 words for M lines accommodated in 4096 words per line.
Each word holds an insertion flag indicating whether or not to insert a VP-AIS cell during occurrence of a line failure.

The one-second timer counter 5 autonomously repeats the one-second time and outputs a one-second elapsed signal irrespective of the occurrence timing of the line failure or the timing of inserting the VP-AIS cell.

When the insertion identifier search means 6 receives the one-second elapsed signal from the one-second timer counter 5, it starts searching from the address "0" of the memory 4 and temporarily searches if the VP-AIS cell insertion flag is valid. It stops the operation and outputs a cell generation request signal to the cell generation means 7. Upon receipt of the cell generation request signal, the cell generation means 7 detects the line state of the line corresponding to the temporarily stopped address of the memory 4 from each of the line fault state holding means 3. VP-AIS cell is generated based on the temporarily stopped address. Then, when the line state of the corresponding line is normal or when the generated VP-AIS is inserted, the search is restarted from the next address which has been temporarily stopped. A similar operation is performed with the address “M × 4096-1” of the last address of the memory 4.
When the number reaches “0”, the operation is stopped at the address “0” of the start address of the memory 4. Next, when a 1 second elapsed signal is received from the 1 second timer counter 5, the address “0” of the memory 4 is read.
The search is started from "number" and the same operation is repeated.

When the VP-AIS cell is generated by the cell generation means 7, the invalid cell detection & cell insertion means 8 detects a valid cell / invalid cell of the ATM cell received from the multiplexing 2 in the preceding stage, and determines the invalid cell. Invalid cell when detected
-Replace with AIS cells.

When the one-second elapsed state monitoring means 9 receives the one-second elapsed signal from the one-second timer counter 9, the state monitoring means 9 monitors the state of the insertion identifier searching means 6 at that time and obtains "M × 4096-
It is monitored whether or not the search has been completed up to “No. 1.” If the search has not been completed, the search is continued, and if the search is completed up to the address “M × 4096-1” of the memory 4, the address “ The search is performed from "No. 0" and up to the address "M.times.4096-1" in the memory 4. When the one-second elapsed signal from the one-second timer counter 9 is received, the state of the insertion identifier search means 6 is monitored. And "MX4
If the search has not been completed up to the number 096-1, N times in a row, an instruction is issued to forcibly start the search from the address "0" in the memory 4 even during the search.

Alternatively, after the lapse of one second, the state monitoring means 9 determines that the insertion identification / retrieval means 6 has changed the address “0” of the start address of the memory 4 to the address “M × 4096-1” of the last address.
When a specific time exceeding 1 second elapses, the search is forcibly instructed to start the search from the address “0” of the memory 4 even during the search.

Next, the operation of the first embodiment will be described with reference to the timing chart of FIG. 1 second timer counter 5
When the received ATM cell is an invalid cell using the 1-second elapsed signal as the start signal, the first line is inserted from the VP-AIS cell for line 0 / VP0, and the VP-AIS cell for line 0 / VP1 ... 0 line / VP-AIS cell for VP4095,
1 line / VP-AIS cell for VP0 ... 1 line / V
VP-AIS cell for P4095 ··· M line / VP0
VP-AIS cell for M line / V for VP 4095
After inserting up to the P-AIS cell, stop. When the next one-second elapsed signal is received, it is inserted for the first time from the VP-AIS cell for line 0 / VP0, and then the same is repeated.

FIG. 8 is a diagram showing the positioning of the operation and maintenance cell generation circuit in the ATM switching system. The operation and maintenance cell generation circuit according to the present invention is provided at a stage after M lines are multiplexed by accommodating M lines in a line corresponding portion of the ATM exchange.

Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 3 is a block diagram showing a second embodiment of the operation and maintenance cell generation method according to the present invention.

In FIG. 3, multiplexing 2 multiplexes M lines to be accommodated into one line. Memory 4 is one line warm 40
A virtual path line state holding table consisting of M × 4096 words for M lines accommodating 96 words and holding a flag indicating a virtual path line state of a virtual path in each word, and Y words for Y connections of the number of simultaneous processing connections VC during virtual path line failure
-Insertion bit indicating whether to insert AIS cell or VC-A
Line number, VPI number, VC used to generate IS cell
It consists of a virtual channel table holding the l number. FIG. 5 is a diagram showing a table configuration of a virtual path line state holding table in the memory 4, and FIG. 6 is a diagram showing a table configuration of a virtual channel table in the memory 4.

The one-second timer counter 5 autonomously repeats the one-second time regardless of the occurrence timing of the virtual path line failure, the insertion timing of the VC-AIS cell, etc., and outputs a one-second elapsed signal.

The insertion identifier search means 6 starts from the one-second elapsed signal from the one-second timer counter 5 as a start instruction and starts from the virtual channel table address "0" in the memory 4 to the virtual channel table address "Y-1". The insertion identifiers up to are searched independently, and when the address “Y−1” of the virtual channel table is searched, the operation is stopped.

The cell generation means 7 determines whether the VC-AIS cell insertion flag retrieved by the insertion identifier means 6 is a valid system internal connection number and the corresponding line number held in the virtual path line state holding table in the memory 4. When the virtual path line state (normal state / failure state) of the corresponding VPI number is a failure state, a VC-AIS cell is generated based on the corresponding system internal connection, the corresponding line number, the corresponding VPI and the corresponding VCl.

The invalid cell detection & cell insertion means 8 detects a valid cell / invalid cell of the received ATM cell, and when an invalid cell is detected, replaces it with the VC-AIS cell generated by the cell generation means 7.

When one second has elapsed from the one-second timer counter 5, the state monitoring means 9 monitors the state of the insertion identifier searching means 6 when a one-second elapsed signal is received from the one-second timer counter 5, and checks the address "Y-1" of the virtual channel table in the memory 4. If the search is not completed up to N times consecutively, an instruction is issued to forcibly start the search from the address “0” of the virtual channel table in the memory 4 even during the search.

Next, the operation of the second embodiment will be described. In multiplexing 2, ATM cells received from each line are multiplexed into one line and output. In the memory 4, one line warm 40
A virtual path line state holding table consisting of M × 4096 words for M lines accommodating 96 words and holding a flag indicating a virtual path line state of a virtual path in each word, and Y words for Y connections of the number of simultaneous processing connections VC during virtual path line failure
-Consists of a virtual channel table holding an insertion flag indicating whether or not to insert an AIS cell.

The one-second timer counter 5 autonomously repeats the one-second time irrespective of the occurrence timing of the virtual path line failure, the insertion timing of the VC-AIS cell, and outputs a one-second elapsed signal.

When the insertion identifier search means 6 receives the one-second elapsed signal from the one-second timer counter 5, it starts searching from the address "0" of the virtual channel table in the memory 4, and the VC-AIS cell insertion flag is valid. If an address is found, the cell is temporarily stopped and a cell generation request signal is output to the cell generation means 7. When the cell generation means 7 receives the cell generation request signal, based on the line number and the VPl number held at the temporarily stopped address in the memory 4, the corresponding line and the corresponding VP are obtained from the virtual path line state table in the memory 4.
If the virtual path line status of the “1” is a fault status, the VC-VC-number is determined based on the suspended address of the memory 4, that is, the line number, VPI number, and VCl number held in the system internal connection number and the suspended address. An AIS cell is generated.

When the line state of the corresponding virtual path line is normal or when the generated VC-AIS is inserted, the search is restarted from the next address which has been temporarily stopped.
When the same operation is performed up to the address “Y-1” of the final address of the virtual channel table in the memory 4, the operation is stopped at the address “0” of the start address of the virtual channel table in the memory 4. Next, when a one-second elapsed signal is received from the one-second timer counter 5, a search is started from the address "0" of the virtual channel table in the memory 4, and the same operation is repeated.

In the invalid cell detection & cell insertion means 8, when the cell generation means 7 generates the re-VC-AIS cell, the valid cell / invalid cell of the ATM cell received from the multiplexing 2 in the preceding stage is detected, and the invalid cell is detected. When a cell is detected, VC is set to an invalid cell.
-Replace the AIS cell.

When the one-second elapsed state monitoring means 9 receives the one-second elapsed signal from the one-second timer counter 9, the state monitoring means 9 monitors the state of the insertion identifier searching means 6 at that time and checks the address "Y-
It is monitored whether or not the search is completed up to No. 1. If the search is not completed, the search is continued as it is, and when the search is completed up to the address "Y-1" of the virtual channel table in the memory 4, the memory 4 is continued. The search is performed from the address “0” of the internal virtual channel table, and thereafter the same operation is performed.When a one-second elapsed signal is received from the one-second timer counter 9, the state of the insertion identifier search means 6 is monitored. If the search is not completed up to address "Y-1" N times consecutively, the address "0" of the virtual channel table in the memory 4 is forcibly forced even during the search.
Instructs the search to start from "number".

Alternatively, after the lapse of one second, the state monitoring means 9 completes the search by the insertion identification search means 6 from the address "0" of the start address of the virtual channel table in the memory 4 to the address "Y-1" of the last address. When a specific time exceeding 1 second elapses, a command is issued to forcibly search from the address “0” of the virtual channel table in the memory 4 even during the search.

The timing chart of the second embodiment is the same except that the VP-AIS cell in the operation / maintenance cell generation timing chart of the first embodiment of FIG. 2 is changed to the VC-AIS cell. .

[0057]

As described above, according to the present invention, even if the operation and maintenance cell generation circuit is provided, it is possible to reduce the size of the line corresponding portion in the ATM exchange. When M lines are accommodated in the line-corresponding section of the ATM exchange, M operation and maintenance cell generation circuits are required. However, after multiplexing the M lines, the operation and maintenance cell generation circuit is provided to provide one operation and maintenance cell generation circuit. This is because the operation and maintenance cell generation circuit is sufficient.

Further, according to the present invention, since the number of simultaneously failed lines of a plurality of lines and the number of all virtual paths used differ depending on the occasion, transmission of a VP-AIS cell for every virtual path one cell at a time of a failure occurs. Even if the time variation to complete is large or the worst VP-AIS cell transmission completion exceeds one second at worst, the average is one per second.
It is possible to transmit VP-AIS cells on a cell-by-cell basis. This means that the VP-AIS cell is transmitted one cell per second irrespective of the number of simultaneously failed lines of a plurality of lines or the total number of virtual paths being used by activating the insertion identifier searching means by the one-second timer counter. When the transmission is not completed N times consecutively by the state monitoring means after 1 second, the youngest VP-AI
This is because it is possible to start sending from S.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an operation and maintenance cell generation method according to the present invention.

FIG. 2 is an operation maintenance cell generation timing chart according to the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a table configuration in a memory according to the first embodiment.

FIG. 5 is a diagram illustrating a table configuration of a virtual path line state holding table in a memory according to a second embodiment;

FIG. 6 is a diagram illustrating a table configuration of a virtual channel table in a memory according to a second embodiment.

FIG. 7 is a diagram showing a cell format in a system according to a second embodiment.

FIG. 8 is a diagram showing an arrangement of an operation and maintenance cell generation circuit in the ATM switching system of the present invention.

FIG. 9 is a diagram showing a conventional operation and maintenance cell generation circuit.

FIG. 10 is a conventional operation and maintenance cell generation timing chart.

FIG. 11 is a diagram showing an arrangement of an operation and maintenance cell generation circuit in a conventional ATM switching system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Physical layer termination means 2 Multiplexing 3 Each line fault state holding means 4 Memory 5 1 second timer counter 6 Insertion identifier search means 7 Cell generation means 8 Invalid cell detection & cell insertion means 9 State monitoring means after 1 second elapsed 10 Physical layer Termination unit 11 Multiplexing 12 OAM cell transmission unit 13 VPI / VCl conversion unit 14 Line correspondence unit 15 Switch unit 20 Optical signal reception circuit 21 Cell synchronization circuit 22 Link failure detection circuit 23 VP-AIS transmission interval control circuit 24 Table scanning circuit 25 VP table 26 VP-AIS cell generation circuit 27 selection circuit 28 empty cell generation circuit

Claims (4)

(57) [Claims] 1. An ATM layer network monitoring / control system for use in an ATM switching network used in an ATM switching network, wherein each line fault state holding means for holding a line state of a plurality of lines accommodated therein; And a memory for holding an insertion identifier indicating whether or not to insert a VP-AIS cell during a line failure in each virtual path multiplexed on the line, and a line failure occurrence timing and a VP-AIS cell insertion timing. A one-second timer counter that autonomously repeatedly counts one-second time and outputs a one-second elapsed signal independently of the above, and a one-second elapsed signal from the one-second timer counter is used as a start instruction to determine the line number and VPl number of the memory. Independently searching for insertion identifiers from the youngest to the oldest, and stopping after searching for the oldest one, the insertion identifier searching means, When the inserted identifier of the retrieved VP-AIS cell is a valid line number and VIP number, and the state of the line held in each line fault state holding means is a fault state, based on the line number and the corresponding VPl number, V
A cell generation unit for generating a P-AIS cell; a valid cell / invalid cell of a received ATM cell is detected; and if an invalid cell is detected, an invalid cell detection & A cell insertion unit, when the one-second elapsed time signal is received from the one-second timer counter, the state of the insertion identifier search unit is monitored, and if the search is not completed up to the oldest number N times consecutively, the search is forcibly performed even during the search. And a state monitoring means after one second elapses, which instructs to perform a search from a younger number. 2. The operation and maintenance cell generation system according to claim 1, wherein M lines are accommodated in a line-corresponding section of the ATM exchange and are arranged after the M lines are multiplexed. 3. A method for monitoring and controlling an ATM layer network in a line-corresponding portion of an ATM exchange used in an ATM switching network, wherein a virtual path line state of a plurality of virtual paths is held for each line, and A memory for holding an insertion identifier indicating whether or not to insert a VC-AIS cell during the occurrence of a virtual path line failure in units of virtual channels multiplexed on a path, a timing of occurrence of a virtual path line failure, and a VC-AI
A one-second timer counter that autonomously repeats the one-second time and outputs a one-second elapsed signal independently of the S-cell insertion timing; and a one-second elapsed signal from the one-second timer counter as a start instruction. An insertion identifier search means for autonomously searching for insertion identifiers from the lowest number to the home number of the internal connection number and stopping when searching to the end, a system in which the insertion identifier of the VC-AIS cell searched by the insertion identifier searching means is valid The corresponding line and the corresponding VPl which is the internal connection number and is held in the memory
When the virtual path line state (normal state / failure state) is in a failure state, the VC-AIS based on the corresponding system internal connection number, the corresponding line number, the corresponding VPI and the corresponding VCI
Cell generation means for generating cells; invalid cell detection & cell insertion means for detecting valid / invalid cells of received ATM cells and inserting a VC-AIS cell generated by the cell generation means upon detection of invalid cells When a one second elapsed signal is received from the one second timer counter, the state of the insertion identification search means is monitored, and if the search is not completed until the old number is repeated N times consecutively, the search is forcibly started from the youngest even during the search. An operation and maintenance cell generation method, comprising: state monitoring means after one second elapses for instructing to perform a search. 4. The state monitoring means after one second has passed, when a specific time exceeding one second from the youngest number to the home number of the insertion identifier searching means completes the search, even during the search, the state monitoring means forcibly performs the processing. 4. The operation and maintenance cell generation method according to claim 1, wherein an instruction is issued to start searching from a younger number.