JP2894751B2 - Demodulator and receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a demodulation device and a receiver.

(Prior Art) In general, when demodulating a received signal subjected to transmission path distortion by multipath, it is necessary to reduce a bit error rate by demodulating after performing waveform equalization using an adaptive automatic equalizer. Can be.

However, when an adaptive automatic equalizer is applied to a received signal that has passed through a transmission path with good multipath, the bit error rate is worse than when no adaptive automatic equalizer is applied.

Japanese Patent Application Laid-Open No. 64-8750 discloses a technique relating to a demodulator using an adaptive automatic equalizer adaptively, focusing on such a point.

FIG. 26 is a diagram showing the configuration of the demodulation device disclosed in this publication.

In the figure, reference numeral 1 denotes a distributor for dividing a received signal into two.

One of the received signals distributed by the distributor 1 is supplied to a first demodulator 4 having an adaptive automatic equalizer, and the other is supplied to a second demodulator 6 not having an adaptive automatic equalizer. Supplied.

Thereafter, the output of one of the first demodulation unit 4 and the second demodulation unit 6 is selected by the signal selector 7.

Then, the bit error rate of the selected signal is measured by the measuring circuit 8, and the result is sent to the determining circuit 9.

The determination circuit 9 compares the value of the bit error rate measured by the measurement circuit 8 with a predetermined measurement value, and determines the bit error rate of the output of the first demodulator 4 and the output of the second demodulator 6. And outputs a selection signal to the signal selector 7.

By the way, in such a demodulator, it is assumed that the received signal includes a known training signal, and the code error rate is obtained by comparing the code of the training signal with the code of the demodulated signal. .

However, the number of training signals is very small compared to the number of all signals, and it takes a considerable amount of time to obtain a code error rate used as a threshold, during which a path with a low code error rate is selected. there is a possibility.

For example, consider a TDMA in which one burst is 256 bits and the training signal is 15 bits. In the example of the above publication, a threshold value is used for the code error rate 10 ⁻⁶ . Thus, in order to obtain a code error rate of 10 ^-6 , a code of at least 10 ⁶ bits is required, and 6 × 10 ⁴ or more bursts are required. Even if the threshold of the code error rate is set to 10 ^-2 , several tens of bursts are required. Thus, such a measurement time that may select a path with a bad bit error rate is not negligibly small.

Further, in the demodulation device configured as described above, both the first path and the second path need to be constantly operated. That is, it is necessary to always supply power to both the first path and the second path.

However, when such a demodulation device is used in a device such as a mobile phone or a mobile phone, there is a problem that the life of the power supply is shortened because the power supply capacity of these devices is limited. In particular, since the power consumption of the equalizer is much larger than other parts, it is problematic to keep such a circuit constantly operating.

On the other hand, in a general demodulator, a frequency offset occurs due to a difference between an oscillation frequency of a local oscillator and a carrier frequency of a received signal. For this reason, a means for removing this is required.

FIG. 27 is a diagram showing an example of a digital demodulator having means for removing such a frequency offset.

In the figure, reference numeral 11 denotes an input terminal to which a received RF (IF) signal is input.

The RF signal input to this input terminal 11 is
Is multiplied by the multiplier 13 and converted into a baseband signal.

This baseband signal is subjected to a frequency offset removal circuit 15
Sent to

The frequency offset removal circuit 15 removes the frequency offset from the baseband signal based on the output of the frequency offset detection circuit 16 that detects the amount of frequency offset from the baseband signal output from the multiplier 13.

The baseband signal from which the frequency offset has been removed in this way is subjected to waveform equalization by the equalizer 17, and then sent to a subsequent channel decoding unit for performing error correction and the like.

 Reference numeral 18 denotes a power supply unit that supplies power to each unit.

By the way, in the demodulation device having such a configuration, it is necessary to keep the frequency offset detection circuit 16, the communication channel decoding unit, and the like operating at all times.

However, the constant operation of the frequency offset detection circuit or the like as described above poses a problem in terms of power supply life when such a demodulation device is applied to a device having a limited power supply capacity such as a mobile phone or a mobile phone. is there.

In addition, when the frequency offset detection circuit and the like are always operated, the amount of calculation becomes extremely large, that is, a large number of gates are required from a hardware aspect. For this reason, there is a problem from the viewpoint of miniaturization and LSI of the device.

In particular, when a transversal filter type circuit is used as the frequency offset detection circuit, the ratio of the current consumption and the amount of calculation to the entire demodulation device becomes very large.
Therefore, in this case, operating the frequency offset detection circuit constantly as described above is a very serious problem.

(Problems to be Solved by the Invention) In the conventional demodulator using the adaptive automatic equalizer as described above, the code error rate can be reduced over the entire region with respect to multipath distortion. There is a problem that it takes a long time to measure the bit error rate for use as a threshold value.

In addition, in the conventional demodulator, circuits that are unnecessary for the operation are always operated, so that the power supply life and the size of the device can be reduced.
There is a problem in terms of LSI implementation.

Therefore, a first object of the present invention is to provide a demodulation apparatus which can reduce the bit error rate over the entire region with respect to multipath distortion and has a short time for measuring the bit error rate for use as a threshold value. And a receiver.

A second object of the present invention is to provide a demodulation device and a receiver which are suitable in terms of power supply life, miniaturization of the device, and LSI.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a signal distribution means for dividing received signals into two, and an adaptive automatic equalizer for compensating for transmission line distortion. A first demodulation means for converting the first received signal distributed by the signal distribution means into a digital signal, and a first demodulation means having no adaptive automatic equalizer and distributed by the signal distribution means. A second demodulation means for converting the received signal of the second demodulation means into a digital signal, at least a reception period of the data signal which is a non-training period, a sign of an output of the first demodulation means and an output of the second demodulation means. Code comparing means for detecting codes and calculating the ratio of mismatch between these codes, and the first demodulating means when the ratio of mismatch calculated by the code comparing unit is equal to or greater than a predetermined threshold value. Output of demodulated signal And to select, when the ratio of the discrepancy is less than the threshold value, in which is configured by including a signal selector for selecting an output of said second demodulating means.

Further, the present invention includes signal distribution means for dividing received signals into two, and an adaptive automatic equalizer for compensating for transmission line distortion, and converts the first received signals distributed by the signal distribution means into digital signals. First demodulating means for converting the received signal distributed by the signal distributing means into a digital signal without the adaptive automatic equalizer, and a sequence of the received signal. A multipath detecting means for detecting the presence of the multipath from above, and selecting the output of the second demodulating means when the multipath is detected by the multipath detecting means, and selecting the output of the second demodulating means when the multipath is not detected. Signal selection means for selecting the output of the first demodulation means.

(Operation) In the invention described in claim 1, at least the non-training period of the data signal, the ratio of the mismatch between the sign of the output of the first demodulation unit and the sign of the output of the second demodulation unit. Is calculated and the demodulated signal is selected based on the result, so that the time for measuring the bit error rate to be used as the threshold can be shortened.

According to the invention described in claim 2, by detecting the presence of multipath from the sequence of the received signal and selecting an optimal path based on the detection result, a good code can be obtained without being affected by fading. An error rate can be obtained.

(Example) Hereinafter, details of an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a demodulation device according to one embodiment of the present invention.

In the figure, reference numeral 100 denotes a distributor for dividing a received signal into two.

One of the received signals distributed by the distributor 100 is
Supplied to a first demodulation unit 102 having an adaptive automatic equalizer,
The other is a second demodulation unit 104 without an adaptive automatic equalizer.
Supplied to

Then, the first demodulation unit 102 compensates for transmission line distortion included in the received signal by the adaptive automatic equalizer, and converts the received signal with the transmission line distortion compensated into a digital signal. Further, second demodulation section 104 converts the received signal into a digital signal as it is without compensating for transmission line distortion.

The code comparator 106 measures the rate of mismatch between the code of the output from the first demodulation unit 102 and the code of the output from the second demodulation unit 104 for a predetermined period. For example, assuming TDMA, the rate of mismatch is measured during N bursts.

 Here, the measured mismatch rate is D.

The sign comparator 106 compares the mismatch rate D with a predetermined mismatch rate Dc.

When D> Dc, it is determined that the bit error rate of the output of the first demodulation section 102 is better than the bit error rate of the output of the second demodulation section 104, and the output of the first demodulation section 102 is determined. Output a selection signal to select.

On the other hand, when D <Ds, it is determined that the bit error rate of the output of the second demodulation section 104 is good, and a selection signal is output to select the output of the second demodulation section 104.

Thereafter, one of the outputs of the first demodulation unit 102 and the second demodulation unit 104 is selected by the switch 108, and is sent to a subsequent circuit.

The switching of the switch 108 is performed by the switch control unit 110 based on a selection signal from the code comparator 106.

Here, as described above, the output of one of the demodulation units is selected by comparing the mismatch rate D with a predetermined mismatch rate Dc for the following reason.

FIG. 2 shows the case where the degradation of the bit error rate due to the multipath delay wave is passed through an equalizer and the case where the degradation is not passed.

The bit error rate without passing through the equalizer (FIG. 2) is
It is low in a transmission line without a delay wave, and deteriorates rapidly as the delay amount of the delay wave increases.

On the other hand, the bit error rate when passing through an equalizer (Fig. 2)
Although there is degradation due to an increase in the amount of delay of a delayed wave, the rate of degradation is much smaller than when the signal does not pass through an equalizer.

Therefore, the code when the signal passes through the equalizer and the code when the signal is not passed are compared, and the rate of mismatch is measured. Then, the second
On the left side of the intersection (FIG. 2) of the two bit error rate curves shown in the figure, that is, when the code error rate is better without passing through the equalizer, the maximum code mismatch rate is 10 ^{−. It} is very close to ^{2 and} less than 2 × 10 ^{-2 at the} intersection. Also, on the right side of the intersection, that is, when the code error rate is better through the equalizer, the code mismatch rate is a very large value compared to 2 × 10 ^-2 .

Therefore, for example, a value where the code mismatch rate is around 10 ^-2 is set as the threshold value (corresponding to Dc in the present embodiment). If the rate of code mismatch (equivalent to D in the present embodiment) is greater than this threshold, the output through the equalizer is selected. Select the output when not passing through. As a result, it is possible to select a path having a better code error rate.

As described above, in the present embodiment, in the initial operation, it is possible to quickly select a demodulation unit having a good error rate.
In the steady state, more reliable selection can be made.

That is, in the related art, the error rate is measured only with the training signal, and a demodulation unit having a good error rate is selected based on the measurement result. On the other hand, in the present embodiment, the measurement of the error rate is performed on all the signals including the training signal and the data signal, and the demodulation unit having the good error rate is selected based on the measurement result. Is extremely short.

 Next, another embodiment will be described.

FIG. 3 is a block diagram showing the configuration of the demodulation device according to this embodiment.

In the embodiment shown in the figure, first, a received signal is orthogonally demodulated by a demodulation unit 112 and converted into a baseband signal.

This baseband signal is split into two by a splitter 114, one of which is supplied to a first detector 116 having an adaptive automatic equalizer, and the other being a second detector having no adaptive automatic equalizer. Is supplied to the detection unit 118 of FIG.

The sign comparator 120 measures the rate of mismatch between the sign of the output from the first detector 116 and the sign of the output from the second detector 118, as in the above-described embodiment.

After that, one of the outputs of the first detection unit 116 and the second detection unit 118 is selected by the switch 124 whose switching is controlled by the switch control unit 122, and is sent to the subsequent circuit.

In the present embodiment, the circuits of the first embodiment shown in the two sets of demodulators except for the detection function are replaced by one set of demodulators.
It is common to 112. Therefore, simplification, downsizing, and low power of the circuit can be realized. Therefore, such a demodulation device is extremely useful when applied to a device in which the size and power supply capacity of the device are limited, such as a mobile phone or a mobile phone.

 Next, another embodiment will be described.

FIG. 4 is a block diagram showing the configuration of the demodulation device according to this embodiment.

In the figure, reference numeral 126 denotes a distributor for dividing a received signal into two.

One of the received signals distributed by the distributor 126 is
Supplied to a first demodulation unit 128 having an adaptive automatic equalizer,
The other is a second demodulation unit 130 without an adaptive automatic equalizer.
Supplied to

Then, first demodulation section 128 compensates for transmission line distortion included in the received signal by the adaptive automatic equalizer, and converts the received signal with the transmission line distortion compensated into a digital signal. Further, second demodulation section 130 converts the received signal into a digital signal as it is without compensating for transmission line distortion.

The digital signal converted by the first demodulation unit 128 is sent to the first eye opening degree measurement unit 132 and the switch 134. The digital signal converted by the second demodulation unit 130 is supplied to the second eye opening measurement unit 136 and the switch 1.
Sent to 34.

The first eye opening degree measuring section 132 and the second eye opening degree measuring section 136 are for obtaining the eye opening degree from the digital signal (input signal). Here, the eye opening degree is
It shows the degree of opening of a waveform pattern in which a demodulated baseband signal sequence is drawn on a time axis synchronized with bits. The first eye opening degree measuring unit 132 and the second eye opening degree measuring unit 136 are configured, for example, as shown in FIG.

As shown in the drawing, the sign of the input signal is determined by a determination circuit 138. After the determination value is multiplied by the input signal by the multiplier 140, the average level thereof is obtained by the first integrator 142, the signal passes through the adjacent signal difference extraction circuit 144 and the square circuit 146, and the second determination value is obtained. The noise average level is obtained by the integrator 148. And the divider
By dividing the average level by 150 and the noise average level,
Eye opening is required. By setting the integration time of the first integrator 142 and the second integrator 148 to a burst length or a code block length, the first demodulation unit 128 and the second demodulation unit 130
Can be selected in units of burst length or code block length.

Thus, the eye opening degree obtained by the first eye opening degree measuring unit 132 and the second eye opening degree measuring unit 136 is calculated by the comparator 1
Sent to 52.

The comparator 152 compares these eye opening degrees, and when the eye opening degree by the first eye opening degree measurement unit 132 is large,
The switching of the switch 134 is controlled so that the output of the first demodulation unit 128 is selected as a demodulated signal. On the other hand, when the eye opening degree by the second eye opening degree measuring unit 136 is large, the second eye opening degree
Of the switch 134 so as to select the output of the demodulation unit 130 as a demodulated signal.

Therefore, in this embodiment, a good error rate can be obtained without being affected by fading. That is, the reception electric field intensity becomes extremely low due to fading mainly during flat fading. Therefore, the case where the training sequence falls into the valley of fading and the demodulation of one burst cannot be performed is mainly the case of flat fading. By the way, at the time of such flat fading, an equalizer is not particularly required. That is, good demodulation can be performed by delay detection or the like constituting a demodulation unit without passing through an equalizer. Moreover, in this differential detection, even if demodulation in the training sequence fails, it is possible to demodulate only the data portion. Therefore, when the equalizer fails to converge, an overall good error rate can be obtained by using the output of the delay detection of the demodulation unit having no equalizer.

Here, the determination as to whether or not such flat fading is performed can be made by obtaining and comparing each eye opening degree of the output of the equalizer and the output of differential detection as in the present embodiment.
That is, the eye opening of the output of the equalizer never increases when the equalization does not converge. In particular, RL
When a high-speed synchronization algorithm such as the S algorithm is used, the convergence or complete divergence is achieved, and the eye has a characteristic of being closed unless converged. On the other hand, the eye opening of the output of the differential detection is always open unless the S / N ratio at that time is sufficiently high and the multipath delay spread is not so large. Therefore, in the demodulation impossible state due to non-convergence of the equalizer at the time of flat fading where the delay spread is not large, the eye opening degrees of the output of the equalizer and the output of the differential detection may be compared.

Further, if the delay spread is large to some extent, the probability that the training sequence falls into the fading valley is reduced sufficiently, so that the equalizer operates normally. That is, by selecting one of the outputs of the equalizer and the delay detection output based on each eye opening degree as in the present embodiment, a good error rate can always be obtained.

By the way, in the case of the configuration of the demodulation device as shown in FIG. 4, the configuration is considered to be complicated because a delay detector is additionally required. However, hardware that implements the Kalman algorithm, the RLS algorithm, and the like, which are generally used as tap coefficient correction algorithms for mobile communication equalizers, is several tens of times or more of these. For this reason,
The increase in hardware due to the addition of the delay detector is 1% or less, and the configuration is not so complicated.

In the demodulation device shown in FIG. 4, memories 154 and 156 may be provided after each of the first demodulation unit 128 and the second demodulation unit 130, as shown in FIG. That is, the first demodulation unit 128
And outputs of the second demodulation unit 130 are stored in a memory 154,
Once stored in 156, each eye opening is measured. Then, based on the measurement result of each eye opening, the memory
First demodulation unit 128 stored in 154 and 156 and used for the measurement
Alternatively, the output of the second demodulation unit 130 is selected. Thereby, better results can be obtained. This is because, for example, a burst signal is input, and any demodulated data can be determined based on the eye opening degree of the burst signal itself. At this time, the eye opening may be an average value of the eye opening over the entire eye opening.

In addition, when the block REC is applied to the input signal of the demodulation device in the above-described embodiment and the decoding must be obtained at a subsequent stage of the demodulation device, the eye opening degree is measured in units of code blocks, and the selected output is output. Should be performed.

Furthermore, when an AGC is arranged in front of the second demodulation section 130, the eye opening degree measurement means may be as shown in FIG. In the figure, 158 is AGC,
Reference numeral 160 denotes a second eye opening degree measuring unit. This second
In the eye opening degree measuring section 160, the determination of the sign is performed by the determination circuit 152, and the determination value is subtracted from the input signal by the subtractor 164.
The eye opening degree is obtained through the integrator 168. in this case,
When the output of the second eye opening degree measuring unit 160 is small, the eye opening degree is large.

Further, the first eye opening degree measuring means of the system including the equalizer may be the one shown in FIG. In the figure, reference numeral 170 denotes an equalizer, and 172 denotes a first eye opening degree measuring unit. The first eye opening degree measurement unit 172 obtains the eye opening degree by passing the error signal e (t) used for tap correction of the equalizer 170 through the square circuit 174 and the integrator 176.

Further, when the characteristics of the first eye opening degree measuring section and the second eye opening degree measuring section are different, as shown in FIG. The correction table 178 may be inserted so as to obtain the lowest BER (Bit Error Rate) by compensating for the difference.

 Next, another embodiment will be described.

FIG. 10 is a block diagram showing the configuration of the demodulation device according to this embodiment.

In the figure, reference numeral 180 denotes a distributor for dividing a received signal into two.

One of the received signals distributed by the distributor 180 is
Supplied to a first demodulation unit 182 having an adaptive automatic equalizer,
The other is a second demodulation section 184 without an adaptive automatic equalizer.
Supplied to

Then, first demodulation section 182 compensates for transmission line distortion included in the received signal by the adaptive automatic equalizer, and converts the received signal with the transmission line distortion compensated into a digital signal. Further, second demodulation section 184 converts the received signal into a digital signal as it is without compensating for transmission line distortion.

The digital signal converted by the first demodulation unit 182 is sent to the selection output device 188. The second demodulation unit 1
The digital signal converted by 84 is sent to an eye opening degree measuring unit 186 and a selection output device 188.

The eye opening degree measuring section 186 calculates the eye opening degree from the digital signal (input signal), and is configured, for example, as shown in FIG.

The eye opening determined by the eye opening measuring unit 186 is sent to the selection output device 188.

The selection output device 188 compares the eye opening with a predetermined threshold value, and if the eye opening is large, the second
Is selected as a demodulated signal. on the other hand,
If the eye opening is small, the output of the first demodulation unit 182 is selected as a demodulated signal.

Also in this embodiment, a good error rate can be obtained without being affected by fading.

 Next, another embodiment will be described.

FIG. 11 is a block diagram showing the configuration of the demodulation device according to this embodiment.

In the figure, reference numeral 190 denotes a distributor for dividing a received signal into two.

One of the received signals distributed by the distributor 190 is
Supplied to a first demodulation unit 192 having an adaptive automatic equalizer,
The other is a second demodulation unit 194 without an adaptive automatic equalizer.
Supplied to

Then, first demodulating section 192 compensates for transmission line distortion included in the received signal by the adaptive automatic equalizer, and converts the received signal with the transmission line distortion compensated into a digital signal. Further, second demodulation section 194 converts the received signal into a digital signal as it is without compensating for transmission line distortion.

The digital signal converted by the first demodulation unit 192 is sent to the error rate measurement device 196 and the selection output device 198. The digital signal converted by the second demodulation unit 194 is sent to the selection output device 198.

Here, assuming that a received signal to be an input signal to the demodulation device is in a burst form, the received signal includes a training signal and a refresh signal as shown in FIG. Then, the equalizer operates by the training signal and the refresh signal. By the way, these two signals are known signals to the demodulation unit. The error rate measurement device 196 measures the error rate of the output of the first demodulation unit 192 by one burst or a predetermined number of bursts using the known value.

The error rate determined by the error rate measurement device 196 is sent to the selection output device 198.

The selection output device 198 compares the error rate with a predetermined threshold value, and when the error rate is small, selects the output of the first demodulation unit 192 as a demodulated signal. On the other hand, when the error rate is high, the output of the second demodulation section 194 is selected as a demodulated signal.

Therefore, also in this embodiment, a good error rate can be obtained without being affected by fading.

 Next, another embodiment will be described.

FIG. 13 is a block diagram showing the configuration of the demodulation device according to this embodiment.

In the figure, reference numeral 200 denotes a distributor for dividing a received signal into two.

One of the received signals distributed by the distributor 200 is
Supplied to a first demodulation unit 202 having an adaptive automatic equalizer,
The other is a second demodulation unit 204 without an adaptive automatic equalizer.
Supplied to

Then, the first demodulation unit 202 compensates for transmission line distortion included in the received signal by the adaptive automatic equalizer, and converts the received signal with the transmission line distortion compensated into a digital signal. Also, the second demodulation unit 204 converts the received signal as it is into a digital signal without compensating for the transmission line distortion.

The digital signals converted by the first demodulation unit 202 and the second demodulation unit 204 are sent to the selection output device 206.

On the other hand, the received signal before being distributed by the distributor 200 is
It is also input to the matched filter 208. As shown in FIG. 14, the matched filter 208 outputs a signal having impulse-like power when the received signal has no multipath (FIG. 14A), and outputs the signal when the received signal has multipath. A signal is output so that the power has a certain width (FIG. 6B).

The multipath detection device 210 is configured as shown in FIG. 15, and first calculates a power value from a signal sent from the matched filter 208 by the power calculation circuit 212. After this, the comparator
In step 214, the calculated power value is compared with a predetermined threshold value set in the threshold value memory 216 in advance. When the calculated power value is larger than the threshold value, the counter 218 is turned on, and when it is smaller, the counter 218 is turned off. The value of the ON period t obtained by the counter 218 in this way is passed to the selection control circuit 220. When the ON period t is longer than a predetermined length, the selection control circuit 220 determines that a multipath exists, outputs a signal to select the second demodulation unit 204 to the selection output device 206, and If the period t is shorter than a predetermined length, it is determined that there is no multipath, and the first demodulation unit 202
Is output.

As described above, in the present embodiment, the amount of multipath delay is estimated and the demodulation unit is selected based on the estimated value, so that a good error rate can be obtained without being affected by fading.

 Next, another embodiment will be described.

FIG. 16 is a block diagram showing the configuration of the demodulation device according to this embodiment.

In the figure, reference numeral 222 denotes a distributor that distributes a burst-like received signal used in TDMA into two.

One of the received signals distributed by the distributor 222 is
Supplied to a first demodulation unit 224 having an adaptive automatic equalizer,
The other is a second demodulation unit 226 without an adaptive automatic equalizer.
Supplied to

Then, first demodulation section 224 compensates for transmission line distortion included in the received signal by the adaptive automatic equalizer, and converts the received signal with the transmission line distortion compensated into a digital signal. Further, second demodulation section 226 converts the received signal into a digital signal as it is without compensating for transmission line distortion.

The digital signals converted by the first demodulation unit 224 and the second demodulation unit 226 are sent to the selection output device 228.

The selection control circuit 230 includes an eye opening degree measuring device 1 shown in FIG.
86, an error rate measuring device 196 shown in FIG. 11, a multipath detecting device 210 shown in FIG. 13, and the like, and controls switching of the selection output device 228 according to predetermined conditions.

The selection output device 228 selects the output from the first demodulation unit 224 for the next 100 bursts and opens the switch 232 when the output of the first demodulation unit 224 is selected 9 or more out of 10 bursts. Then, the supply of power from the power supply unit 234 to the second demodulation unit 226 is stopped. On the other hand, when the output of the second demodulation unit 226 is selected to be 9 or more out of 10 bursts, the output of the second demodulation unit 226 is selected for the subsequent 100 bursts, and the switch 236 is opened to open the power supply unit 234. To the first demodulation unit 22
Stop supplying power to 4. In other cases, power is supplied to both the first demodulation unit 224 and the second demodulation unit 226, and the selection output unit 228 performs selection for each burst.

Therefore, in this embodiment, battery saving can be performed without deteriorating the error rate.

 Next, another embodiment will be described.

FIG. 17 is a block diagram showing the configuration of the demodulation device according to this embodiment.

In the figure, reference numeral 238 denotes a distributor for dividing a received signal including a training signal into two.

One of the received signals distributed by the distributor 238 is
Supplied to a first demodulation unit 240 having an adaptive automatic equalizer,
The other is a second demodulation unit 242 without an adaptive automatic equalizer.
Supplied to

Then, first demodulating section 240 compensates for transmission line distortion included in the received signal by the adaptive automatic equalizer, and converts the received signal with the transmission line distortion compensated into a digital signal. Further, the second demodulation unit 242 converts the received signal into a digital signal as it is without compensating for transmission line distortion.

In the training period in which the training signal is being received, the output of the second demodulation unit 242 is
Supplied to 44. The code error measurement unit 244 measures a code error of the output of the second demodulation unit 242 during the training period, and determines whether or not a code error equal to or greater than a predetermined threshold NE occurs within the training period. If no code error equal to or more than the predetermined threshold value NE occurs continuously for the predetermined period D, it is determined that the output of the second demodulation unit 242 satisfies the desired quality, and the second A signal for selecting demodulation section 242 is output. On the other hand, when a code error equal to or more than the predetermined threshold value NE occurs continuously for the predetermined period D, it is determined that the output of the second demodulation unit 242 does not satisfy the desired quality, and the first A signal for selecting demodulation section 240 is output.

The operation control unit 246 controls both the first demodulation unit 240 and the second demodulation unit 242 to operate during the training period. If the output of the code error measurement unit 244 is a signal for selecting the second demodulation unit 242 during the data period during which the data signal subsequent to the training signal is being received, the second demodulation unit 242 At the same time as
The operation of the first demodulation unit 240 is controlled to be stopped. On the other hand, in a data period during which a data signal subsequent to the training signal is being received, and when the output of the code error measurement unit 244 is a signal for selecting the first demodulation unit 240, the first
The operation of the demodulation unit 240 of the second
Control is performed to stop the operation of 42. The operation of the demodulation unit is stopped by the first and second demodulation units 240 and 2.
In the case where 42 is formed of CMOS, this can be performed by cutting off the clock supplied to the first and second demodulation units 240 and 242. In addition, these first and second
When the demodulation units 240 and 242 are not configured by CMOS, the power supply to the first and second demodulation units 240 and 242 can be physically cut off.

The switch 248 is connected to the output side of the first demodulation unit 240 under the control of the operation control unit 246 when the first demodulation unit 240 is operating during the data period.
When 42 is operating, it is connected to the output side of the second demodulation unit 242.

For example, the operation when the training signal is “101”, the threshold value NE is “1”, and the predetermined period D is “2” is described in the eighteenth.
A description will be given based on the drawings.

In FIG. 18, a received signal is input to distributor 238 at time t11. First training period T starting at time t11
In R11, the first and second demodulation units 240 and 242 are both operating, and the outputs of the first and second demodulation units 240 and 242 are both "101". No errors are detected. However, in this case, since a code error has not yet been detected in two consecutive training periods, the code error measurement unit 244 outputs a signal for selecting the first demodulation unit 240. Therefore, in the data period following the first training period TR11, the first demodulation unit 240 continues to operate, but the operation of the second demodulation unit 242 is stopped.

In the first training period TR12, the first and second training
The demodulation units 240 and 242 operate together. In this case as well, the outputs of the first and second demodulation units 240 and 242 are both “101”, so that the code error measurement unit 244 does not detect a code error. Here, since no code error has been detected in two consecutive training periods, the code error measurement unit 244 outputs a signal for selecting the second demodulation unit 242. Therefore, in the data period following the second training period TR12, the second demodulation unit 242 continues to operate, but the operation of the first demodulation unit 240 is stopped.

Thereafter, in the training period TR, the second demodulation unit 24
From the output of 2 until a code error is detected, the second demodulation unit 2
42 operates continuously, and the first demodulation unit 240 operates only during the training period.

In the training period TR14 starting from the subsequent time t13, when the output of the second demodulation unit is “100” and the code error measurement unit 244 detects a code error, the code error measurement unit 2
44 determines that the second demodulation unit 242 no longer satisfies the desired quality, and outputs a signal for selecting the first demodulation unit 240. Therefore, in the data period following the training period TR14, the operation of the first demodulation unit 240 is continued, but the operation of the second demodulation unit 242 is stopped.

In the subsequent training periods TR15 and TR16,
In this case, the outputs of the first and second demodulation units 240 and 242 are both "101", and the code error is still generated in two consecutive training periods. , The code error measurement section 244 outputs a signal for selecting the second demodulation section 242 at time t14.
Therefore, in the data period following the second training period TR16, the second demodulation unit 242 continues to operate, but the operation of the first demodulation unit 240 is stopped.

Thereafter, again in the training period TR, the second demodulation unit 242 operates continuously and the first demodulation unit 240 operates only during the training period until a code error is detected from the output of the second demodulation unit 242. I do.

As described above, in the present embodiment, when the adaptive automatic equalizer is not necessary, the operation of the adaptive automatic equalizer is stopped by the first demodulation unit 240 stopping the operation of the operation. The power consumption of the demodulation device can be reduced.

 Next, another embodiment will be described.

FIG. 19 is a diagram showing the configuration of the demodulation device of this embodiment.

In the figure, reference numeral 250 denotes an input terminal to which a received RF (IF) signal is input, 252 denotes a local oscillator that oscillates a signal of a predetermined frequency, and 254 denotes an RF signal input to the input terminal 250. This is a multiplier that multiplies the output of the local oscillator 252 and converts it to a baseband signal.

256 is a demodulation unit for demodulating the baseband signal output from the multiplier 254 into a digital sequence, and 258 is a multiplier 2
A frequency offset detection circuit 260 detects the amount of frequency offset from the baseband signal output from 54. Reference numeral 260 denotes a memory for storing the detection result of the frequency offset detection circuit 258.

The demodulation unit 256 includes a low-pass filter 262 that removes low-frequency components from the baseband signal, a frequency offset detection circuit 2
A frequency offset removing circuit 264 for removing a frequency offset of a baseband signal based on a detection result sent from the memory 58 or the memory 260, compensating for transmission line distortion by performing waveform equalization of the baseband signal and determining the sign of the baseband signal And the like. The equalizer 266 observes the convergence state of the error signal or the tap coefficient for a predetermined period.

Further, 270 is a power supply unit for supplying power to each unit, and 272 is a frequency offset detection circuit 2 from the power supply unit 270 based on the error signal output from the equalizer 266 or the convergence result of the tap coefficient.
Whether to supply power to 58 or memory 260 and switch 268
Is a power supply control circuit that switches between the two.

Next, the operation of the demodulation circuit thus configured will be described.

The RF signal input to the input terminal 250 is multiplied by the output of the local oscillator 252 by the multiplier 254, and is converted into a baseband signal.

This baseband signal is subjected to a frequency offset removal circuit after a low-pass component is removed by a low-pass filter 262.
264.

The baseband signal from which the frequency offset has been removed by the frequency offset removing circuit 264 is output to the equalizer 26.
After waveform equalization and the like are performed in step 6, the sign is determined.

On the other hand, the frequency offset detection circuit 258 initially operates by receiving power supply from the power supply unit 270 via the power supply control circuit 272, detects the amount of frequency offset from the baseband signal output from the multiplier 254, The result is sent to the frequency offset removing circuit 264. At this time, switch 2
60 is turned on, and the supply of power to the memory 260 is stopped.

Thereafter, when the power control circuit 272 receives an error signal or a signal indicating that the tap coefficients have converged from the equalizer 266, the power control circuit 272 starts supplying power to the memory 260, and outputs the output of the frequency offset detection circuit 258 at that time. After that, the switch 268 is turned off. As a result, data relating to the amount of the frequency offset detected by the frequency offset detection circuit 258 at that time is stored in the memory 260. After that, the power supply control circuit 272 stops supplying power to the frequency offset detection circuit 258. Further, data relating to the amount of the frequency offset sent to the frequency offset removing circuit 264 from this point is stored in the memory 260.

Thereafter, upon receiving an error signal or a signal indicating that the tap coefficient does not converge from the equalizer 266, the power supply control circuit 272 starts supplying power to the frequency offset detection circuit 258, turns off the switch 268, and turns off the memory. Stop supplying power to 260. As a result, the data relating to the amount of frequency offset detected by the frequency offset detection circuit 258 from that time is stored in the frequency offset removal circuit 264.
Will be sent to

Hereinafter, the frequency offset removing circuit 264 receives data on the amount of frequency offset from either the frequency offset detecting circuit 258 or the memory 260 based on the error signal or the convergence result of the tap coefficient from the equalizer 266.

Thus, in the demodulation device of the present embodiment, the memory 260
The reason why the power supply to the frequency offset detection circuit 258 can be stopped by using the following is that the following points are noticed.

That is, the frequency offset mainly occurs due to a difference between the oscillation frequency of the local oscillator and the carrier frequency of the received signal. However, the oscillation frequency of the local oscillator does not fluctuate significantly in a short time. In addition, since the oscillator of the base station has a very high accuracy, the carrier frequency of the received signal varies due to the Doppler shift but does not vary greatly. Therefore, once the frequency offset is corrected, it is not necessary to perform a new correction in a short time, and it is not necessary to operate the frequency offset detection circuit during this period.

Accordingly, in the demodulation device of the present embodiment, the supply of power to the frequency offset detection circuit 258 is stopped during most of the operation period, and the operation is stopped. Therefore, when the demodulation device is applied to a device having a limited power supply capacity, such as a mobile phone or a mobile phone, for example, it is possible to maintain a long power supply life. In addition, the amount of calculation is reduced, and therefore the number of gates is reduced, which contributes to downsizing of the device and LSI.

Next, a specific example of the equalizer 266 used in the above-described embodiment will be described.

FIG. 20 is a diagram showing the structure of the transversal type adaptive automatic equalizer.

The equalizer shown in the figure includes a shift register 274 including four sets of delay units 274a to 274d, multipliers 276a to 276e for multiplying each output of the shift register 274 by tap coefficients, and outputs of the multipliers 276a to 276e. And a decision unit 280 that determines the sign based on the result of the accumulation. The result before the determination by the determiner 280 and the result after the determination are subtracted by the subtractor 282, and the tap coefficient control circuit 284 sequentially updates the tap coefficients according to the subtraction result, that is, the error signal. Algorithms for this update include LMS (Least Mean Square), Zero Forcing, and RM
S (Recursiv Least Square) and the like.

By the way, the received signal transmitted from the base station is in the form of a burst, and one burst is, as shown in FIG. For example, it is composed of a 230-bit data signal.

In the equalizer shown in FIG. 20, the training signal portion of the received signal shown in FIG. 21 is input first, and is shifted by the shift register 274 for each sample.

Then, each output of the shift register 274 is connected to the multipliers 276a to 276-2.
Cumulative addition by 76e and accumulator 278, subtractor
An error signal is output from 282.

Here, at the tenth bit, which is twice the tap coefficient of the multipliers 276a to 276e, the residual signal approaches a constant value. However, if the frequency offset is large, the error signal varies and its absolute value tends to increase.

Therefore, such error signals are observed until the training signal is no longer received from the 10th bit onward, and the average value of these absolute values is obtained.

Then, when the obtained average value exceeds a predetermined threshold value, the power supply control circuit 272 shown in FIG.
Is sent to the effect that the error signal does not converge.

 Next, another embodiment will be described.

FIG. 22 is a diagram showing the configuration of the demodulation device of this embodiment.

The demodulation device shown in FIG. 19 differs from the demodulation device shown in FIG. 19 in that the demodulation unit is a demodulation unit 256 'without a frequency offset removing circuit and the local oscillator is a voltage controlled oscillator 252'.

Then, the voltage-controlled oscillator 252 ′ receives the data on the amount of the frequency offset from either the frequency offset detection circuit 258 or the memory 260, and changes the oscillation frequency so that the frequency offset disappears, thereby removing the frequency offset. I have. That is, the voltage controlled oscillator 252 '
However, they perform the function of the frequency offset removing circuit in the demodulator shown in FIG. As a result, not only the same effect as the demodulation device shown in FIG. 19 can be obtained, but also the number of components can be further reduced.

 Next, another embodiment will be described.

FIG. 23 is a diagram showing the configuration of the demodulation device of this embodiment.

The demodulation device shown in FIG.
Frequency offset detection circuit 258 'composed of CMOS
The demodulation device shown in FIG. 19 is a switch 286 for switching whether or not to supply a clock to the offset detection circuit 258 'instead of the frequency offset detection circuit and the power supply control circuit for controlling the supply of power to the memory. And different.

When the switch 286 receives an error signal or a signal indicating that the tap coefficients do not converge from the equalizer 266, the switch 286 is turned on, and a clock is supplied to the frequency offset detection circuit 258 '. On the other hand, when the error signal or the signal indicating that the tap coefficients have converged is received from the equalizer 266, the signal is turned off, and the clock is not supplied to the frequency offset detection circuit 258 '. As a result, the frequency offset detection circuit 258 'is in the stop state and does not consume current. Therefore, in this embodiment, not only the same effects as those of the demodulation device shown in FIG. 23 can be obtained, but also the number of components can be reduced by the amount corresponding to the power supply control circuit.

 Next, another embodiment will be described.

FIG. 24 is a diagram showing the configuration of the demodulation device of this embodiment.

In the figure, reference numeral 288 denotes an antenna for receiving a digital signal modulated by a carrier wave and converted into a signal in a carrier frequency band.

As shown in FIG. 25, this digital signal is composed of a known training signal on the receiving side, an unknown data signal on the receiving side, and a parity signal for correcting or detecting a code error.

The signal received by the antenna 288 is converted into a signal in the intermediate frequency band by the RF unit 290 and supplied to the demodulation unit 292.

The demodulation unit 292 includes, for example, the equalizer 294 shown in FIG. 20 and compensates for transmission line distortion included in the intermediate frequency band signal, and converts the intermediate frequency band signal into a baseband digital signal. Is supplied to the communication channel decoding unit 296.

Here, the tap coefficient of the equalizer 294 is set to a predetermined initial value until a training signal as a signal in the intermediate frequency band is supplied from the RF unit 290, but the training coefficient as a signal in the intermediate frequency band is set. Each time the signal is sampled and provided, it is updated sequentially using the RLS algorithm. The equalization error signal e (t) generated from the equalizer 294 in this process is generally a complex number, and the operation control unit 29
Supplied to 8.

The operation control unit 298 supplies the training signal from the equalizer 294 for a period from the time when the training signal is received twice as many as the tap coefficient of the equalizer 294 to the time when the training signal is finished. And observe the equalized error signal e (t). Then, the equalization error signal e (t)
If the average of the absolute values of is greater than a predetermined threshold,
It is determined that the received signal does not satisfy the desired reliability, and while the data signal and the parity signal subsequent to the training signal are being received, the operations of the demodulation unit 292 and the channel decoding unit 296 are stopped. On the other hand, when the average value of the absolute values of the equalization error signals e (t) is smaller than a predetermined threshold, it is determined that the received signal satisfies the desired reliability, and the data signal following the training signal is determined. While receiving the parity signal and the parity signal, the operation of the demodulation unit 292 and the channel decoding unit 296 is continued. The operation of the demodulation unit 292 and the communication channel decoding unit 296 can be stopped by shutting off the clock supplied to them when they are constituted by CMOS. When the demodulation unit 292 and the communication channel decoding unit 296 are not configured by CMOS, the power can be supplied by physically shutting off the power supplied to them.

The power supply unit 300 always supplies power to the RF unit 290, but the operation control unit 29 supplies power to the demodulation unit 292 and the communication path decoding unit 296.
Power is supplied via 8.

The channel decoding unit 296, even while receiving the data signal and the parity signal following the training signal, if a signal for continuing the operation is supplied from the operation control unit 298, the parity as a baseband signal. A code error is corrected or detected using the signal. If there is no code error, the digital signal is reproduced and output from the supplied baseband signal. On the other hand, if a correctable code error exists, the digital signal is reproduced and output by correcting the error from the supplied baseband signal. When an uncorrectable code error is detected, a code error detection signal is output.

As described above, in this embodiment, the error signal of the equalizer is observed for a predetermined period, and when the value is larger than a predetermined threshold, it is determined that the received signal does not satisfy the desired quality, and the training signal is determined. While receiving the data that follows,
Since the operations of the demodulation unit and the channel decoding unit are stopped, it is possible to suppress power consumption.

Note that, as a predetermined period for observing the error signal of the equalizer, from the time when the training signal is received to the time when the training signal of twice the number of tap coefficients of the equalizer 294 is received until the time when the training signal is received ends. The period was set for the following reason. That is, since the tap coefficients of the equalizer 294 are sequentially updated using the RLS algorithm, if the transmission path distortion included in the received signal is included in a region that can be equalized by the equalizer, the equalizer is not used. This is because the tap coefficient and the equalization error signal have converged to a substantially constant size from the start of the update of the tap coefficient to the end of the update of the tap coefficient twice the number of taps.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to reduce the bit error rate over the entire region with respect to multipath distortion,
In addition, the time for measuring the bit error rate for use as the threshold can be shortened.

It is also suitable in terms of battery life, miniaturization of the device, and LSI.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a demodulation device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a case where deterioration of a bit error rate due to a multipath delay wave is passed through an equalizer and a case where it is not passed. FIG. 3 is a diagram showing a modification of the demodulation device shown in FIG. 1,
FIG. 4 is a diagram showing a configuration of a demodulator according to another embodiment of the present invention, FIG. 5 is a diagram showing a configuration of an eye opening degree measuring means shown in FIG. 4, and FIG. 6 is a diagram shown in FIG. FIGS. 7 and 8 are views showing a modification of the demodulation device, FIGS. 7 and 8 are diagrams showing a modification of the eye opening degree measuring means in the demodulation device shown in FIG. 4, and FIG.
The figure which shows the modification of the comparator in the demodulation device shown in a figure, FIG.
10 and 11 are diagrams showing a configuration of a demodulation device according to another embodiment of the present invention, FIG. 12 is a diagram showing a received signal used in the demodulation device shown in FIG. 11, and FIG. FIG. 14 is a diagram showing a configuration of a demodulator according to another embodiment of the present invention, FIG. 14 is a diagram for explaining the operation of a matched filter in the demodulator of FIG. 13, and FIG. FIGS. 16 and 17 show a configuration of a detection device, FIGS. 16 and 17 show a configuration of a demodulation device according to another embodiment of the present invention, and FIG. 18 illustrates an operation of the demodulation device shown in FIG. FIG. 19 is a diagram showing a configuration of a demodulation device according to another embodiment of the present invention, and FIG.
FIG. 19 is a diagram showing a configuration of a transversal type adaptive automatic equalizer used in the demodulator shown in FIG. 19, FIG. 21 is a diagram showing a received signal used in the demodulator shown in FIG. 24 are diagrams showing a configuration of a demodulation device according to another embodiment of the present invention, FIG. 25 is a diagram showing a received signal used in the demodulation device shown in FIG. 24, FIG. 26 and FIG. FIG. 2 is a block diagram showing a configuration of a conventional demodulator. 100: distributor, 102: first demodulator, 104: second demodulator, 106: sign comparator, 108: switch, 110
... Switch control unit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Katsumi Sakakibara 1 Tokoba, Komukai Toshiba-cho, Saisaki-ku, Kawasaki-shi, Kanagawa Prefecture (56) References JP-A-64-8750 (JP, A) JP-A-61-167229 (JP, A) JP-A-1-129520 (JP, A) JP-B 64-3406 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04B 3 / 00-3/18 H04L 27/00-27/22 H03H 15/00-17/00

Claims (3)

(57) [Claims] 1. A signal distribution means for distributing a received signal into two parts, and an adaptive automatic equalizer for compensating for transmission line distortion, wherein the first received signal distributed by the signal distribution means is converted into a digital signal. A first demodulation unit; a second demodulation unit that does not have the adaptive automatic equalizer and converts a second received signal distributed by the signal distribution unit into a digital signal; A code comparing means for detecting a sign of an output of the first demodulation means and a sign of an output of the second demodulation means during a reception period of a certain data signal, and calculating a ratio of mismatch between these codes; If the rate of mismatch calculated by the code comparing means is equal to or greater than a predetermined threshold, the output of the first demodulation means is selected as a demodulated signal, and if the rate of mismatch is equal to or less than the threshold, The second restoration A signal selecting means for selecting an output of the adjusting means. 2. A signal distribution means for distributing a received signal into two parts, and an adaptive automatic equalizer for compensating for transmission line distortion, wherein the first received signal distributed by the signal distribution means is converted into a digital signal. A first demodulation unit; a second demodulation unit that does not have the adaptive automatic equalizer and converts a second reception signal distributed by the signal distribution unit into a digital signal; A multipath detecting means for detecting the presence of a multipath from the multipath detecting means, selecting the output of the second demodulating means when the multipath is detected by the multipath detecting means, and selecting the output of the second demodulating means when the multipath is not detected. And a signal selecting means for selecting an output of the demodulating means. 3. A receiver comprising the demodulation device according to claim 1.