JP2892354B2 - Monolithic filter - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial application field) The present invention relates to a monolithic filter, and more particularly, to an improvement in characteristics change due to temperature.

(Prior Art) In recent years, as devices have been downsized, smaller and lighter filters have been required. Conventionally, a switch capacitor filter (hereinafter, referred to as SCF) has been widely used as a small and lightweight monolithic filter that can be integrated on an IC chip as described above. The SCF controls the electric charge of the capacitor with a switch, and thus performs an operation equivalent to a resistance.This constitutes the resistance part of the monolithic filter.Besides its use as a switch, it is used as an active element for an amplifier, for example. MOSFETs with low gm are used. For this reason, the frequency that can be realized as a filter is incredibly low, and only a filter in a voice band is currently in practical use.

Therefore, when considering a filter applicable to a high frequency band such as a video band, a bipolar transistor having a large gm (hereinafter simply referred to as a transistor) is used, so that integration using a transistor is possible. Various filters have been proposed.

FIG. 7 shows a main part of an integration circuit which is a component of the conventional filter. In the figure, Q
₄₁ and Q ₄₂ , Q ₄₃ and Q ₄₄ and Q ₄₅ and Q ₄₆ are npn pair transistors, respectively, 41 and 42 are positive and negative input terminals, respectively.
43 and 44 an output terminal, 45 denotes an emitter degeneration resistance of the resistance value R _E, 46 capacitors ,, capacitance value C _L 47,4
8,49 is the current value each I _D, shows the current down to I _D, I _E. This circuit has a capacitor 46 as a load on the output of current control current reduction (VCVS), and its input terminal
This is an integration circuit in which a transfer function H (s) from 41, 42 to the output terminals 43, 44 is given by the following equation.

H (s) = [1 / (s · _CL · R _E )] · (I _E / I _D ) (1) In the above equation (1), the gain is I _E / (C _L · R _E · I _D ) represents an ideal analysis circuit, but in reality, the frequency characteristics of the transistors that make up the integration circuit are parasitic capacitances, so an ideal integration circuit cannot be obtained, and the phase delay is 90 degrees or more. , The amplitude characteristic deviates from −6 dB / cot, and the frequency characteristic deteriorates. These non-idealities have a large effect on the characteristics of a filter formed using the integration circuit, and specifically lower the upper limit frequency and the Q value that can be realized as a filter.

Therefore, when realizing a high-Q filter in a high-frequency band, how to suppress the deterioration of these frequency characteristics is an important issue in the design of an integrating circuit.

Another important issue in integrating circuit design is how to realize an integrating circuit with accurate gain using current integrated circuit manufacturing technology, in which the absolute accuracy of the built-in element values varies by ± 30%. Is to do it. For this purpose, for example, in the formula (1), leave the value of I _E variable, even when the value of C _L · R _E · I _D is shifted from the exact design value of the I _E By adjusting the value,
Gain I _E / value itself of _{(C L · R E · I} D) , the method that the exact value has been used conventionally.

Considering the above problem with the integrating circuit of FIG. 7, the main cause of the deterioration of the frequency characteristic is the presence of the emitter degeneration resistor 45. Transistor Q ₄₁ by the presence of this, the capacitance between the base and emitter of Q ₄₂ C
A time constant is generated between π and π, thereby deteriorating the frequency characteristics. According to the calculation result, the transistor Q ₄₁ or Q ₄₂
Is lower than the direct current by 3 dB, the frequency c is approximately given by the following equation.

c ≒ 1 / {2π · Cπ · [(R _E / 2] + rb)} ... (2) where, rb is the base resistance of the transistor Q ₄₁ or Q _42. Resistance value of emitter degeneration resistor 45
To clarify the effect of R _E is on the frequency characteristics, will be calculated in a typical each numerical example frequency c of the equation (2). Current standard integrated circuit manufacturing processes use Cπ
The frequency c in the above equation (2) is c ≒ 36 MHz, assuming that 2PF · rb is about 200Ω, for example, R _E 4kΩ. On the other hand, if R _E = 0, c ≒ 398 MHz.

From this, it can be seen that the frequency characteristic is degraded by about one digit when the emitter degeneration is performed as compared with the circuit without the original emitter degeneration (R _E = 0). Therefore, by using a circuit that does not perform emitter degeneration, it is possible to realize a filter that operates in a much higher frequency range.

However, in the conventional integration circuit shown in FIG. 7, the purpose of the emitter degeneration is to linearize the nonlinearity of the emitter junction of the transistor by negative feedback, thereby expanding the linear range of the input. . Therefore, if the emitter degeneration is simply removed, the linearity of the integration circuit will be impaired.

On the other hand, an attempt to improve the non-linearity of the emitter junction, the emitter degeneration resistance than the thermal voltage V _T represented by the following formula needs to be a value such as causing a sufficiently large voltage drop.

V _T = kT / q, (k is Boltzmann's constant, q is the electron charge, T
Is an absolute temperature, and when T = 300 ° K, V _T ≒ 26 mV) Although it is related to the value of the current value I _D of the current source, if it is attempted to improve the nonlinearity to a certain extent, usually R _E must be several kΩ or more. For this reason, the one who specifies the frequency must be sacrificed.

On the other hand, conventionally, a differential amplifier circuit has been proposed in which the non-linearity of the emitter junction is canceled and the linear range of the input is expanded without using the emitter degeneration (JCSchmook: “An Input Stage Transconducta
nce Reduction Technique for High−Slew Rete Operat
inal Amplifiers '', IEEE, J-SSC, SC-10, 6, Dec, 1975, pp
407-411). FIG. 8 shows an integration circuit configured using the differential amplifier circuit.

The differential amplifier circuit is composed of two transistors Q ₄₇ and Q ₄₈ and Q ₄₉ and Q ₅₀ each having an emitter area ratio of 1: 4.
An emitter-coupled pair 51 is constituted the second emitter-coupled pair 52, the first, and the collector of the collect and the transistor Q ₅₀ of the transistor Q ₄₇ is co-continuous in the second emitter-coupled pair 51, 52 And load 5
Connected to 3. Further, the collectors of the transistors Q ₄₉ of the transistor Q ₄₈ is co-continuous, and is connected to the load 53.

54 and 55 is an input terminal, 56 and 57 output terminals, the current value of 58 and 59 is a current source I _Q.

And thus, each of the two transistors Q
₄₇ and Q ₄₈ and Q ₄₉ and the ratio of the emitter area of Q ₅₀ 1: By changing a ratio of 4, first, to the output current of the second emitter-coupled pair 51, 52 1: 4 onset The linearity is improved by adding each output current offset to 1: 4.

61 is a load capacitor volume value C _L for the integration circuit.

The transfer count G (s) from the input terminals 54 and 55 to the output terminals 56 and 57 of the integrating circuit that does not perform the emitter degeneration is given by the following equation.

G (s) = (1 / s · C L) · [25q · I _Q / (8kT)] ... (3) that is, the gain of the integrating circuit is an _{25q · I Q / (8kT ·} C L) , by changing the current value I _Q of the current source 58 and 59, that it can adjust the gain to a desired value is the same as that in the conventional example of the FIG. 7. The difference between the two integrating circuits in FIGS. 7 and 8 is that the former has a wider linear operating range than the latter, whereas the latter operates as an integrating circuit up to a frequency region much higher than the former. Therefore, when a filter is configured using the integration circuit shown in FIG. 8, it is a major issue how to secure a high S / N ratio within a limited linear operation range.

By the way, as described above, a method that can automatically control the gain of the integration circuit to a predetermined value even for unpredictable variations in element values at the time of manufacturing and fluctuations in ambient sound has been conventionally proposed. (For example, Nishio et al., "Automatically tuned high-frequency active RC filter using monolithic integrator", IEICE Technical Report, CAS86-42, 198
6.) In this conventional example, a reference filter including, for example, a band-pass filter is manufactured on the same chip in addition to a main filter originally required. The frequency characteristics of the reference filter are automatically controlled so that, for example, the center frequency of the band-pass filter matches a reference signal frequency given from outside the chip. That is, the vehicle control system that changes the current _{IE of the} current source is built on the chip. On the same chip, a current having a fixed relationship with the current _IE supplied to the reference filter is supplied to the main filter by utilizing the fact that tracking between similar elements is good. By doing so, within the following range of the automatic control system, the characteristics of the main filter are automatically and strictly maintained at predetermined characteristics irrespective of changes in element values and temperatures. Therefore, according to this conventional example, a filter having desired characteristics can be realized automatically without any adjustment by acquisition.

However, this conventional example requires a reference filter and an automatic control system that are not actually used, so that the chip area increases. In particular, when the size of the main filter that is originally required is not so large, there is a problem that the reference filter or the like may be economically disadvantageous because it may occur even when the reference filter occupies a larger area. Furthermore, since the reference signal is used, this is inevitably mixed with the original signal and S / N
There is a problem that the ratio is deteriorated.

In particular, the latter problem is serious when making a filter operating at a high frequency. That is, an integrating circuit having good frequency characteristics and not performing emitter degeneration has a smaller linear area even when linearization is performed, as compared with the case where emitter degeneration is performed. For this reason, if a signal that can be handled is small and a large high-frequency reference signal exists on the same chip, this leaks and the S / N ratio tends to deteriorate. Furthermore, if the above-mentioned automatic adjustment is to be executed strictly with as few errors as possible, it is naturally best to use the same reference filter as that of the main filter, so that the reference signal also has the same frequency as the signal handled by the main filter. I have to make it a obi.

In practice, from an economic point of view, the reference filter is as simple as possible than the main filter, but only the reference signal is in the same frequency band as the signal handled by the main filter. For example, the center frequency of the reference filter and the cutoff frequency of the main filter are made the same. However, in this case, deterioration of the S / N ratio due to leakage of the reference signal becomes a more serious problem.

Therefore, what will happen next unless the automatic tuning method using the above-described reference signal is used is considered. Since the transfer function of the integrating circuit shown in FIG. 8 is given by the above equation (3), the absolute value of the gain can be set to a desired value, or
The problem is the manufacturing variation of the values of C _L and C _Q and their fluctuation due to environmental conditions during use. First, as described above, variations in C _L can be absorbed by controlling the I _Q from outside. However, the (3) includes a absolute temperature T in the denominator in the equation, C _L also changes with temperature. Therefore, when the environmental temperature changes, the gain of the integrating circuit also changes.

Next, the temperature characteristic of the gain of the integration circuit will be considered. As described above, the gain of the integrating circuit in FIG. 7 is I _E / ( _CL · _RE · _ID ). Then, C _L, R _E, IE, although respective values of I _D varies with temperature,殆because in the case of IC tracking homogeneous areas is very good, I _E / I _Q even if the temperature changes It is easy to keep it almost constant. Accordingly, the temperature coefficient of the gain will be determined by the temperature coefficient of C _L and R _E. In a normal IC, C _L having a temperature coefficient of about 500 ppm / deg is R _E
Can be used, and the gain can be set to a temperature coefficient of about several hundred ppm / deg. Therefore, in the filter using the integrating circuit shown in FIG. 7, a change in frequency characteristics of about several percent can be realized even with a temperature change of 100 ° C. This is practically applicable except for a filter whose characteristics are strict, but if possible, it is desirable that the change in the frequency characteristics be lower.

Next, the integration circuit shown in FIG.
From equation, q, k is because a constant value, the temperature coefficient of the gain is determined by the C _L and T. C _L is about 50 ppm / deg, which is no problem, but T has a temperature coefficient of 1/300 = 3333 ppm / deg when the normal temperature is 27 ° C., and controls the overall temperature coefficient. That is, the eighth
The filter constructed using the integrating circuit shown in the figure shows a frequency characteristic change of about 33% with respect to a temperature change of 1000 ° C., and can be used only as a filter with extremely loose specifications. However, if it is possible to vary by comparing the value of I _Q to the absolute temperature T, it can be expected to be suppressed to the temperature coefficient of the overall 50 ppm / deg, is considered to be sufficiently practical.

(Problems to be Solved by the Invention) A conventional integrating circuit having emitter degeneration has good linearity and temperature characteristics but poor frequency characteristics. On the other hand, the contradictory problem that the linearized integration circuit has good frequency characteristics but poor temperature characteristics due to the combination of emitter coupled pairs in which the emitter area ratio is changed at a predetermined ratio without using emitter degeneration. there were.
In addition, the above-mentioned problem is solved automatically by using a reference filter and an external reference signal.
There is a new problem that the N ratio deteriorates and the chip area increases.

The present invention has been made based on the above circumstances, and provides a monolithic filter capable of suppressing a change in frequency characteristics due to a temperature change, having a good S / N ratio, and further reducing a chip area. With the goal.

[Structure of the Invention] (Means for Solving the Problems) To solve the above problems, the present invention comprises a differential amplifier circuit having a plurality of differential input pairs and a load circuit including a capacitive element. In the monolithic filter, a bias circuit that supplies a bias current having a temperature characteristic substantially proportional to absolute temperature to each of the plurality of differential input pairs, and at least a first differential input pair and a second differential input pair Wherein the first differential input pair comprises a first transistor and a second transistor having different emitter areas from each other; the second differential input pair comprises a third transistor and a fourth transistor having different emitter areas from each other; The emitter area ratio of the second transistor is equal to the emitter area ratio of the third transistor and the fourth transistor, and the first transistor and the fourth transistor are the first transistor. Is connected to the force terminal, a second transistor and the third transistor is summarized in that connected to the second input terminal.

(Operation) In the above configuration, since a bias current having a temperature characteristic substantially proportional to the absolute temperature is supplied to each of the plurality of differential input pairs to the differential amplifier, the temperature dependence of the transconductance value of the bias circuit is obtained. Is negated. Therefore,
The gain of each integration circuit constituting the monolithic filter is suppressed from being affected by the temperature change, and the change in the frequency characteristic of the entire filter due to the temperature change is suppressed.

The differential amplifier circuit includes a first transistor and a second transistor.
When the transistors have a predetermined emitter area ratio, the output currents of the first transistor and the second transistor can have an offset of the predetermined emitter area ratio. Similarly, the third transistor and the fourth transistor Make a predetermined emitter area ratio, the output current of the third transistor and the fourth transistor can have an offset of the predetermined emitter area ratio. Therefore, the linearity can be improved.

Then, the temperature characteristics of the filter can be reduced without the need for an automatic adjustment circuit using a reference filter or the like as in the conventional example, and a filter having a good S / N ratio is realized, and the chip area is reduced. And economic advantages.

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 6.

Figure 1 shows the overall configuration of a monolithic filter, the monolithic filter of this embodiment, the temperature compensated differential amplifier circuit 10 _C and its load an integration circuit 10 _A which is a capacitor, 10 3 _B is The band-pass filter is configured as a whole by being connected to each other. Therefore, a temperature-compensated differential amplifier circuit as an element and an integrating circuit configured as a capacitor as a load of the differential amplifier circuit will be described with reference to FIGS.

2 and 3 are block diagrams showing an integrating circuit applied to this embodiment and a current generating means in the integrating circuit, respectively. In FIG. 2, reference numeral 20 denotes a differential amplifier circuit linearized by a combination of a plurality of emitter-coupled pairs, reference numerals 1 and 2 denote input terminals, reference numerals 3 and 4 denote output terminals, and reference numeral 6 denotes the one shown in FIG. , A bias circuit (current generating means) 30 for generating a current proportional to the absolute temperature and supplying this as an emitter bias of the differential amplifier circuit, 7 is a positive power supply line, and 8 is Low-potential power supply line,
A load capacitor 5 is connected between the two output terminals 3 and 4 to form an integrating circuit.

As described above, by using the current generating means 30 for generating a current proportional to the absolute temperature T and reducing the emitter bias current of the linearized differential amplifier circuit 20, the differential amplifier circuit
The 20 transconductances can be made constant with changes in temperature. Therefore, the temperature dependence of the gain of the integrating circuit constituted by using the filter is suppressed, and as a result, a filter having less characteristic fluctuation with respect to a temperature change is realized.

FIG. 3 shows the internal configuration of the current generating means 30 in FIG. 2, and the current generating means 30 comprises a thermal voltage generating means 40 and a voltage / current converting means 50. 9 is a current output terminal.

In a semiconductor device, as a voltage proportional to the absolute temperature T,
A voltage proportional to a so-called thermal voltage (kT / q) can be easily obtained. Therefore, as a reference for generating a current proportional to the absolute temperature T, a thermal voltage generating means 40 using the thermal voltage is used, and an output voltage of the thermal voltage generating means 40 is input to a voltage / current conversion circuit 50, Finally, the current output terminal 9
Output a current proportional to the absolute temperature T.

In such a configuration, in order for the output current of the current output terminal 9 to be proportional to the absolute temperature T, the voltage / current conversion coefficient of the voltage / current conversion means 50 must not change with temperature. In order to convert a voltage into a current, a conversion coefficient having a dimension of (the reciprocal of) a resistance is required, and it is necessary that the conversion coefficient does not change with temperature. As described above, the absolute value of the resistor that can be used in the IC is inaccurate, and the temperature coefficient is about a hundred ppm / deg. Therefore, it is difficult to reduce the temperature coefficient of the gain of the integration circuit with the resistor in the IC. .

Therefore, in order to completely compensate for the temperature dependence of the transconductance of the differential amplifier circuit 20 and to suppress the temperature coefficient of the gain of the component circuit to about 50 pp / deg of the capacitor 5, a resistor having a small temperature coefficient must be used. May be provided outside the IC chip as a reference. Since only one resistor is required, as will be described later, the increase in cost due to this is negligible.

FIG. 4A is a diagram showing a first specific example of the current generating means. Q ₁ , Q ₂ , Q in the thermal voltage generating means 40 _A
3 transistors constituting the current source 14, Q _4, Q _5, the emitter area 1: transistor consisting of the ratio of N, 11 is a differential amplifier. Further, 12 is a small resistance temperature coefficient of the external in the voltage-current conversion unit 50 _A, 13 is a differential amplifier, Q _6,
Q ₇ and Q ₈ are transistors constituting a current source, and 9a and 9b are current output terminals.

Current generating means is configured as described above, now, the transistors Q ₄ and Q _5, when that equal current flows by the action of the current source 14, the transistors Q ₄ and Q ₅
Since the emitter area is 1: N, the total emitter voltages V _BE4 and V _BE5 are as follows.

V _BE4 = V _T · ln (I _O / I _S ) V _BE5 = V _T · ln (I _O / N · I _S ) (4) where _VT is the thermal voltage, I _O is the transistor Q ₄ , the collector current of Q _5, I _S is the saturation current of the transistor Q _4. As shown, because the base voltage of the transistor Q ₄ and Q ₅ are equal, the difference between both the emitter voltage, the voltage which is proportional (kT / q) · ln ( N) ... (5) next, to the difference Removed from the operational amplifier 11. Now, for simplicity, assuming that the differential gain of the differential amplifier 11 is 1, the output voltage becomes the value shown in the above equation (5), where N, R, and q are constants independent of temperature. Therefore, an output voltage proportional to the absolute temperature T is obtained. On the other hand, in the voltage-to-current conversion means 50 _A , the terminal voltage of the non-inverting terminal of the differential amplifier 13 is at the virtual ground potential, so that the output voltage [V _T · ln (N)] of the differential amplifier 11 is
When the resistance value of the resistor 12 is R, a current of (V _T / R) ln (N) flows through the resistor 12. This current, i.e. equal to the collector current of the transistor Q _6, transistors Q _7, Q ₈ to equalize the transistor Q ₆ and the base voltage will eventually _{(V T / R) · ln} (N) proportional to the current flow Te, from the voltage-current conversion unit 50 _a, so that the current of the current value proportional to the absolute temperature T is output.

As is apparent from the above description, by using a resistor having a sufficiently small temperature coefficient as the resistor 12, a current generating means proportional to the absolute temperature T can be realized.

FIG. 4B is a diagram showing a second specific example of the current generating means. The current generating means 30 _B, compared to that of the FIG. 4 (A), a heat voltage generating means and the voltage-current converting means is constructed integrally. In FIG. 4, Q ₉ and Q
₁₀ is a transistor constituting the current mirror circuit 15, Q
₁₁ and the Q _12, emitter area 1: a transistor consisting of the ratio of N.

In this current generator, the collector current of the transistor Q ₁₁ and Q ₁₂ is because it is kept equal by the action of the current mirror circuit 15, the both ends of the resistor 12 of resistance R connected to the emitter of the transistor Q ₁₂ is a transistor it differential voltage of the base-emitter voltage of the transistor Q ₁₂ of Q ₁₁ appears. This voltage, as in the case of the current generating means of the FIG. 4 (A), since the V _T · ln (N), resistor 12
Is (V _T / R) · ln (N), and this current is equal to the collector currents of the transistors Q ₁₁ and Q ₁₂ . On the other hand, the transistor Q ₇ and Q _8, since the transistor Q ₁₁ and the base potential is common, to collectors of the transistors Q ₇ and Q _8, the same current as above, i.e., to obtain a current that is proportional to the absolute temperature T Can be Also in this case, the resistor 12 having a sufficiently small temperature coefficient is used.

Next, FIG. 5 shows a first specific example of the integration circuit. The integrating circuit, the fourth view (B) current generating means 30 shown in _B, the differential amplifier circuit 20 consisting of the following structure _A
And a combination of the above.

That is, the differential amplifier circuit 20 _A, the ratio ratio of the emitter area of the predetermined 1: two transistors Q ₁₃ 4 and Q ₁₄ and Q ₁₅ and Q ₁₆
As a result, a first emitter-coupled pair 1R and a second emitter-coupled pair 18 are formed, and the transistors Q in the first and second emitter-coupled pairs 17 and 18 are formed.
₁₃ and collectors of the transistors Q ₁₆ of are connected. In addition, it is connected to the collector of the transistor Q _14.

The differential amplifier circuit 20 _A is the ratio of the emitter area of the thus each two transistors Q ₁₃ and Q ₁₄ and Q ₁₅ and Q ₁₆ 1:
By changing the output currents of the first and second emitter-coupled pairs 17 and 18 by a ratio of 4, the output currents of the first and second emitter-coupled pairs 17 and 18 have a 1: 4 offset, and the output currents offset by the 1: 4 are added. The linearity has been improved.

Integrating circuit using a differential amplifier circuit 20 _A described above, only a small resistance 12 temperature coefficient in the current generating means to one external, without impairing the frequency characteristics of the original integration circuit, suitable temperature Compensation has been realized. In addition, since the above-described reference signal for temperature compensation is not required, the S / N ratio does not deteriorate as compared with the original value of the integration circuit.

FIG. 6 shows a second specific example of the integration circuit. The integrating circuit is different from the integrating circuit of the Figure 5, the configuration of the differential amplifier circuit 20 _B differ only, configurations of other parts are the same.

The differential amplifier circuit 20 _B in the integrating circuit is constructed as follows.

That is, in FIG. 6, Q ₁₇ and Q ₁₈ and Q ₁₉ and Q ₂₀ are pair transistors having the same emitter area, and the first emitter-coupled pair 21 and the second emitter A coupled pair 22 is configured. First, the common connection point of the emitter of the second emitter-coupled pair 21 and 22, the transistor Q ₇ and Q ₈ are connected at each current generating means.

The first collector a ₁ of the first emitter-coupled pair 21
And the first collector a _{2 of} the second emitter-coupled pair 22
And are connected. Further, a second collector a ₃ of the first emitter-coupled pair 21 and the second collector a ₄ of the second emitter-coupled pair 22 is connected.

In order to improve the linearity, means for giving a required offset to the output currents of the first and second emitter-coupled pairs 21 and 22 having the same emitter area are provided at both input terminals 1 and 2 respectively. Two emitter followers are arranged in parallel as offset DC voltage applying means consisting of two transistors having an area ratio of 1: 4.

That is, one input terminal 1 has an emitter area ratio of 1:
4, two emitter followers 23 and 24 using two transistors Q ₂₁ and Q ₂₂ are arranged in parallel. Each emitter follower 2
Transistors Q ₂₅ and Q ₂₆ as current source loads are connected to the emitter circuits 3 and ₂₄ , respectively. The emitter output point of the emitter followers 23 are connected to the first base b ₁ of the first emitter-coupled pair 21, the emitter output point of the other emitter follower 24 is first base of the second emitter-coupled pair 22 b Connected to ₂ .

Similarly, on the other input terminal 2 side, two emitter followers 25 and 26 using two transistors Q ₂₃ and Q ₂₄ having an emitter area ratio of 1: 4 are provided in parallel. Transistors Q ₂₇ and Q ₂₈ as current source loads are connected to the emitter circuits of the emitter followers 25 and 26, respectively. The emitter output point of the emitter followers 25 are connected to the second base b ₄ of the second emitter-coupled pair 22, the emitter output point of the other emitter follower 26 is the second base of the first emitter-coupled pair 22 b Connected to ₃ .

The differential amplifier circuit 20 _B to form an integrating circuit, which is configured as described above, the transistor Q in the two emitter followers 23, 24 arranged in parallel to one input terminal 1 side
_22, the emitter area has become four times the other transistor Q _21, constant current flows in the same level in the two transistors Q _21, Q _22. Therefore the transistor Q ₂₁ and the respective base-emitter voltage Vbe of the other transistor _{Q 22 V T · ln (I} C / I S) (V) V T · ln (I C / 4I S) (V) ... (6 ) However, I _S: the thermal voltage, and the transistor Q ₂₂ and the voltage difference Vbe of the transistor Q ₂₁ is always _{V T · ln4 (V) ...} (7): saturation current of the transistor, I _C: the collector current, V _T .

As a result, the first base b ₂ of first base b ₁ and the second emitter-coupled pair 22 of the first emitter-coupled pair 21 due to the difference voltage of the base-emitter voltage Vbe for one of the input terminals 1 and between, by which gave DC offset of the required level to the first base b ₁ side of the first emitter-coupled pair 21, a DC voltage offset of the required level to one input section This is equivalent to being applied.

About the other input terminal 2 side, similarly to the above,
By the above second base b ₃ side of the first emitter-coupled pair 21 gave the required level DC offsets in opposite polarities, the DC voltage offset of the required level to the other input portion applied It is equivalent to what was done.

In this way, by giving both inputs a 1: 4 ratio DC offset, the output currents of the first and second emitter-coupled pairs 21, 22 each have a 1: 4 offset, and this By adding output currents offset by 1: 4, the nonlinearity of the bipolar transistor is linearized.

By improving such a differential amplifier circuit portion, the fifth embodiment
The transistors Q _{17 to} Q ₂₀ that determine the upper limit of the frequency characteristic when compared with the differential image circuit 20 _A in the integrating circuit shown in the figure
Since the emitter area can be reduced, it is possible to operate up to higher frequencies. Therefore, it is more suitable for the purpose of this embodiment to provide a filter that can operate at higher frequencies. The transistor Q _{25 in} FIG.
To Q ₂₈ is because it operates as a current source load emitter follower, simply may be any current equal, as shown in the figure, it is not always necessary to the temperature compensation. That is, the base potential of the transistor Q ₂₅ to Q _28, without supplying the current generating means 30 _B, may be normal current supply circuit independent of the current generating means 30 _B.

Monolithic filter of FIG. 1, the integration circuit 10 _A, 1
Operational amplifier circuit with improved linearity without using the emitter degeneration shown in FIG. 6 as 0 _B and 10 _C
It is configured using 20 _B1 , 20 _B2 and 20 _B3 . In FIG.
6 _A , 6 _B , 6 _C are loads, 1 _A to 1 _C , 2 _A to 2 _C are differential amplifier circuits 20 _B1
To 20 _B3 input terminals _{of, 3 A ~3 C, 4 A} ~4 C , each output terminal, 30 _B is the same current generating means to that shown in the FIG. 4 (B), is 28, 29 Input capacitors, 31 and 32 are input terminals of the monolithic filter, and 33 and 34 are output terminals thereof.

In the monolithic filter configured as described above, 10 _A and 10 _B are temperature-compensated integration circuits, and constitute a resonance circuit. On the other hand, the bottom input / output terminal 1 _C
The differential amplifier circuit 20 _B3 to which 3 _C , 2 _C, and 4 _C are connected, respectively,
It operates as a resistor having a reciprocal value of the mutual conductance for damping the above-described resonance circuit, and determines the Q value of the band-pass filter.

Therefore, the monolithic filter of this embodiment has the first
It is necessary that not only the two integrator circuits 10 _A and 10 _B on the upper side of the figure but also the lowermost differential amplifier circuit 20 _B3 be temperature compensated. This is because if the temperature of only the lower differential amplifier circuit _20B3 is not compensated, the Q value of the filter also changes when the temperature changes, which is inconvenient.

In order to obtain the desired filter characteristics by making the variation of the absolute values of the gains of the integration circuits 10 _A , 10 _B , and 10 _C due to the manufacturing error equal to the set value, the current generating means 30 proportional to the absolute temperature is required. _What is necessary is just to adjust the value of the resistor 12 in _B so as to obtain a desired frequency characteristic. For example, adjustment is performed so that the center frequency of the filter matches the design value. If this adjustment is performed at a certain temperature, the current generating means 30 _B
Is proportional to the absolute temperature, and thereafter, even if the temperature changes, the frequency characteristics of the filter hardly change.

[Effects of the Invention] As described above, since a bias current having a temperature characteristic proportional to the absolute temperature is supplied to each of the plurality of differential input pairs to the differential amplifier, each of the plurality of differential input pairs constitutes a monolithic filter. The influence of the temperature change on the gain of the integrating circuit is suppressed, and the change in the frequency characteristic of the entire filter due to the temperature change is suppressed.

The differential amplifier circuit may be configured such that the first transistor and the second transistor have a predetermined emitter area ratio, so that the output current of the first transistor and the second transistor have the predetermined emitter area ratio. An offset can be provided. Similarly, by making the third transistor and the fourth transistor have a predetermined emitter area ratio, the output current of the third transistor and the fourth transistor can be offset by the predetermined emitter area ratio. Can be provided. Therefore, the linearity can be improved.

In addition, the temperature characteristics of the filter can be suppressed to a small value, and a filter having a good S / N ratio can be realized without the need for an automatic adjustment circuit such as a reference filter. Property is obtained.

[Brief description of the drawings]

1 to 6 show an embodiment of a monolithic filter according to the present invention. FIG. 1 is a circuit diagram showing an overall configuration, FIG. 2 is a block diagram of an integrating circuit, and FIG. 3 is a current generating means. FIG. 4 is a circuit diagram showing a specific configuration example of the current generating means, FIG. 5 is a circuit diagram showing an example of a specific configuration of the integration circuit, and FIG. 6 is a circuit diagram showing a specific configuration of the integration circuit. FIG. 7 is a circuit diagram showing another example of the integrating circuit, and FIG. 8 is a circuit diagram showing another conventional example of the integrating circuit. 1,2: input terminal of the differential amplifier _{circuit, 5,5 A, 5 B, 5} C: _{capacitor, 10 A, 10 B, 10} C: integrating circuit, 20,20 _A, 20 _B, 20
_B1, 20 _B2, 20 _B3: a differential amplifier circuit, 21, 22: first, second emitter-coupled pair, 23, 24, 25 and 26: an emitter follower (DC voltage applying means for offset), 30, 30 _B : Current generating means.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03H 11/04-11/14 H03F 3/45

Claims (1)

(57) [Claims] 1. A monolithic filter comprising a differential amplifier circuit having a plurality of differential input pairs and a load circuit including a capacitive element, wherein each of the plurality of differential input pairs is substantially proportional to absolute temperature. A bias circuit for supplying a bias current exhibiting the temperature characteristic described above, and at least a first differential input pair and a second differential input pair, wherein the first differential input pair has a different emitter area from each other.
A third transistor having a different emitter area from each other.
A first transistor and a fourth transistor, wherein an emitter area ratio of the first transistor and the second transistor is equal to an emitter area ratio of the third transistor and the fourth transistor; A monolithic filter connected to one input terminal, wherein the second transistor and the third transistor are connected to a second input terminal.