JP2891189B2 - Protocol converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a protocol converter for performing protocol conversion in a data link layer process of LAPV5 in a communication terminal connected to an ISDN line.

[0002]

2. Description of the Related Art Conventionally, in data link layer processing in a communication terminal or the like connected to an ISDN line, an ETS30
0, 324-1 (V5.1) and ETS 300, 347
-1 (V5.2), the C channel used as a control channel has a data format of a conventional LAPD (Lin
In this example, an area called a 2-octet EF adder is added to the opening flag of the “Access Procedure on the D-Channel” format (ITU-T, Q.921). In addition, the data link layer (LAPV)
5) The processing is also defined as a subset of the LAPD processing.

[0003] The LAPD specification is well known (CCITTI recommendation,
441), and its circuit is formed into an LSI and used as an LAPD transceiver (driver / receiver). V5.1 and V5.2 are new interfaces, and at present, this interface specification is formed into an LSI. Not. Further, since the data format is different from that of the LAPD and the processing is a subset of the LAPD, a commercially available LAPD transceiver cannot be used, so that the HDLC (High Level Data link Control Procedure) is used.
e) Data link layer processing is realized by this firmware using a transceiver.

Japanese Patent Laid-Open Publication No.
Japanese Patent Application Laid-Open No. 175852/1990 "ISDN terminal device" is known. In this conventional example, an outgoing call which needs to be registered in advance and the like is made superior to access contention control on the D channel.

[0005]

As described above, in the former conventional example, since the processing is a subset of the known LAPD, the data format is different, so that a commercially available LAPD transceiver cannot be used. For this reason, it is necessary to perform data link layer processing with firmware using an HDLC transceiver. In this case, there is a disadvantage that the number of design steps increases.

Further, there is a drawback that a period for designing firmware for realizing complicated data link layer processing such as order control and retransmission control and a period for debugging the firmware are increased. Even if the latter conventional example is applied, these problems cannot be solved.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems in the prior art. A commercially available LAPD transceiver is used for data link processing. Another object of the present invention is to provide a protocol conversion device capable of shortening a design period of firmware for realizing complicated data link layer processing such as retransmission control and a debug period.

[0008]

To achieve the above object SUMMARY OF THE INVENTION The protocol conversion device of the invention according to claim 1, LA
A LAPD transceiver for performing PD processing, and the LAPD
Transceiver and serial data transmission line and serial data
With the second HDLC transceiver connected by the data reception line
First connected to V5 control communication device by serial data communication
HDLC transceiver and this first HDLC transceiver
And a control data bus for the second HDLC transceiver
And received by the second HDLC transceiver.
Two octets after the head flag of LAPD format data
V5 format data with Tet EF adder
And sends E to the first HDLC transceiver.
F adder, and the first HDLC trans
Start flag of V5 format data received by the sheaver
Delete the 2-octet EF adder following the
The second HDLC transaction.
EF adder controller that deletes the EF adder sent to the server
And a step .

According to a second aspect of the present invention, there is provided a protocol conversion apparatus comprising:
The configuration is such that the APD transceiver is connected to upper layer processing means for controlling a protocol of Layer 3 or higher.

[0010] A third aspect of the present invention is a protocol converter which is adapted to be applied to data link layer processing in a communication terminal connected to an ISDN line.

In the protocol converter having such a configuration, in the control operation for adding the EF adder, the second HDL
C transceiver receives the LAPD data format from the SAPI and TEI area (V5D in LAPV5)
L adder) to the EF adder area
Transmitting to LC transceiver. In the control operation for deleting the EF adder, the EF adder area of the LAPV5 data format received from the first HDLC transceiver is deleted and transmitted to the second HDLC transceiver.

In this case, a commercially available LAPD transceiver,
Using the HDLC transceiver, a control operation for adding an EF adder and a control operation for deleting the EF adder for simple processing can be realized by firmware. That is, LAPV5
Can be performed, and the number of design steps can be reduced. Furthermore, the design period and the debug period of firmware for implementing complicated data link layer processing such as sequence control and retransmission control are reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a protocol conversion device according to the present invention will be described in detail with reference to the drawings. FIG.
FIG. 1 is a block diagram illustrating a configuration of an embodiment of a protocol conversion device according to the present invention. The protocol conversion device in the example of FIG. 1 includes an upper layer processing unit 1 for controlling a protocol of layer 3 or higher and a LAPD transceiver 2 for performing layer 2 control.
Are connected by a main CPU bus line 14.
The upper layer processing unit 1 includes a main CPU 7, a main first storage unit 8 storing a program for executing each process, and a main second storage unit 9 storing communication data.

The LAPD transceiver 2 and the second HDLC transceiver 3 are connected by a transmission serial data line 15 and a reception serial data line 16. The second HDLC transceiver 3, the EF adder (addr) controller 4 and the first HDLC transceiver 5 are connected to the sub CPU bus line 17
Connected by The EF adder control unit 4 is a sub CPU 1
0 and a sub-first which stores a program for executing the process.
Storage unit 11, sub second storage unit 12 in which communication data of second HDLC transceiver 3 is stored, and sub third storage unit 1 in which communication data of first HDLC transceiver 5 is stored
3. The first HDLC transceiver 5 and the opposite V5 control device 6 are connected by a transmission serial data line 18 and a reception serial data line 19.

Next, the operation of this embodiment will be described. FIG. 2 is a diagram for explaining the operation of this embodiment. First, the transmission procedure will be described. 1 and 2
In FIG. 2, the main CPU 7 of the upper layer processing unit 1 reads a data transmission program from the main first storage unit 8 through the main CPU bus line 14, and transmits transmission data of the data transmission program to the main second storage unit 9 as shown in FIG.
The data is written in the data format A as shown in FIG. When the LAPD transceiver 2 recognizes that the transmission data has been written in the main second storage section 9, the main CP
The transmission data is read through the U bus line 14.

SAPI in the read transmission data
As shown in FIG. 2B, the control fields related to the order control and retransmission control of the data link specified in the TEI field and the TEI field are
Insert between the field. Next, the CRC operation results of all the data fields are added to the FCS field, and then transmitted to the transmission serial data line 15 in a data format B format to which an opening flag and a closing flag are added.

When receiving the data from the transmission serial data line 15, the second HDLC transceiver 3 deletes the opening flag and the closing flag, performs the CRC operation from the SAPI field to the Info field, and performs the FCS as shown in FIG. Compare with field value. If the result of this comparison is normal, the sub CPU
The data is written to the sub second storage unit 12 through the bus line 17 in the data format C.

When the sub CPU 10 recognizes that the data (data format C) has been written to the sub second storage section 12, the sub CPU 10 transmits the data (data format C) from the sub first storage section 11 through the sub CPU bus line 17 as shown in FIG. The program related to the control operation for adding the EF adder is read out, and the data format C stored in the sub second storage unit 12 is read.
The SAPI and TEI fields are added to the head of the data format C and written in the sub third storage unit 13 in the data format D format.

When the first HDLC transceiver 5 recognizes that data (data format D) has been written to the sub third storage section 13, it reads the data through the sub CPU bus line 17. The CRC operation result of this data is
After being added to the S field, an opening flag and a closing flag are added, and the opposite format is used in the data format E, that is, the LAPV5 data format.
5 Transmit to the control device 6 through the transmission serial data line 18.

Next, the receiving procedure will be described. 1st HD
When the LC transceiver 5 receives the format of the LAPV5 data format, that is, the data of the format of the data format E shown in FIG. 2E from the opposite V5 control device 6 through the reception serial data line 19, it sets the opening flag and the progress flag. delete. Next, the leading S
CRC from API field to Info field
Perform an operation and compare with the value of the FCS field.

If the result of the comparison is normal, the data is written in the sub third storage section 13 through the sub CPU bus line 17 in the data format D. Sub CPU10
When recognizing that data has been written to the sub third storage unit 13, the program reads a program related to a control operation for deleting an EF adder from the sub first storage unit 11 via the sub CPU bus line 17. Then, the sub third storage unit 1
3, the first SA of the data format D stored in
The PI and TEI fields are deleted, and the data is written in the sub second storage unit 12 in the format of the data format C shown in FIG.

When the second HDLC transceiver 3 recognizes that data (data format C) has been written in the sub second storage section 12, it reads this data through the sub CPU bus line 17. And CR of this data
After adding the C operation result to the FCS field, an opening flag and a closing flag are added, and FIG.
The data is transmitted to the reception serial data line 16 in the data format B shown in FIG.

When the LAPD transceiver 2 receives data (data format B) from the reception serial data line 16, it deletes the opening flag and the closing flag, performs a CRC operation from the SAPI field to the Info field, and compares it with the value in the FCS field. . If the result of this comparison is normal, the order control and the retransmission control are performed with reference to the data link state specified in the SAPI and TEI fields and the value of the control field.

If the received data is normal, the control field is deleted and the main CPU bus line 1
4 is written to the main second storage section 9 in the format of the data format A shown in FIG. The main CPU 7 stores data (data format A) in the main second storage unit 9.
, The program is read from the main first storage unit 8 through the main CPU bus line 14, and the upper layer processing is executed.

In this embodiment, the main first storage section 8 and the main second storage section 9 in the upper layer processing section 1 are individually configured, but may be configured using the same storage element. Similarly, in the EF adder control unit 4, the sub first storage unit 11, the sub second storage unit 12, and the sub third storage unit 13 are individually configured, but are configured using the same storage element, and the same as the above. Processing may be performed.

[0026]

As is apparent from the above description, according to the protocol conversion apparatus of the present invention, the L level received by the second HDLC transceiver during the control operation for adding the EF adder is obtained.
In the control operation of copying the SAPI and TEI areas from the APD data format to the EF adder area and transmitting the copied data to the first HDLC transceiver, and deleting the EF adder, the LAP received from the first HDLC transceiver is controlled.
The EF adder area of the V5 data format is deleted and transmitted to the second HDLC transceiver.

As a result, a commercially available LAPD transceiver,
Using the HDLC transceiver, a control operation for adding an EF adder and a control operation for deleting the EF adder for simple processing are realized by firmware. Therefore, LAPV
5, the data link layer processing is performed, the design man-hour can be reduced, and the design period of the firmware for realizing complicated data link layer processing such as order control and retransmission control and the debug period can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a protocol conversion device of the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Upper layer processing unit 2 LAPD transceiver 3 Second HDLC transceiver 4 EF adder control unit 5 First HDLC transceiver 6 Counter V5 control device 7 Main CPU 8 Main first storage unit 9 Main second storage unit 10 Sub CPU 11 Sub first storage unit 12 Sub second storage unit 13 Sub third storage unit 14 Main CPU bus line 15, 18 Transmit serial data line 16, 19 Receive serial data line 17 Sub CPU bus line

Claims (3)

(57) [Claims] 1. An LAPD transaction for performing LAPD processing
, The LAPD transceiver, a serial data transmission line,
Second HDLC transceiver connected by serial data reception line
Server and the opposite V5 control communication device by serial data communication
A first HDLC transceiver, the first HDLC transceiver and the second HDLC transceiver;
Connected to the control data bus of the transceiver and the second HD
LAPD format data received by the LC transceiver
A 2-octet EF adder is added after the head flag of the data
To generate V5 format data, and the first HDL
Add an EF adder to be sent to the C transceiver,
And the V5 format received by the first HDLC transceiver.
-2 octets of EF following the start flag of the mat data
Delete the adder, generate LAPD format data,
EF adder for transmitting to the second HDLC transceiver
EF adder control means for performing deletion is provided.
Protocol converter. 2. The protocol conversion device according to claim 1, wherein the LAPD transceiver is connected to upper layer processing means for controlling a protocol of Layer 3 or higher. 3. A protocol converter, wherein the protocol converter according to claim 1 or 2 is applied to data link layer processing in a communication terminal connected to an ISDN line.