JP2888832B2 - Low-pass filter device in charge transfer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay element such as a CCD (Charge Coupled Device) and a low-pass filter device in a charge transfer device provided in a signal output portion of a solid-state imaging device. B. Summary of the Invention In a low-pass filter device provided in a signal output portion of a charge transfer device such as a delay element and a solid-state imaging device, a buffer circuit in which both terminals of an active filter circuit have a constant DC level and a gain of approximately 1 is provided. Are connected to each other to operate sufficiently even under a low voltage, and to have an easy configuration such as a circuit design. C. Prior Art Generally, in a circuit configuration of a charge transfer device such as a solid-state imaging device and a delay element formed of a CCD or the like, an amplification circuit having a predetermined amplification function is provided at an output unit. 6 and 7 show a conventional delay element and an output circuit in a solid-state imaging device, respectively. FIG. 6 shows an example of an inverter circuit configuration, and FIG. 7 shows a source follower circuit. It is an example of a structure. Here, these output circuits will be briefly described with reference to the drawings. First, the output circuit of FIG.
An input signal is inputted to the gate of the MOS transistor 82, and the input signal is inputted from the connection point between the MOS transistor 81 whose gate and drain are connected so as to be an active load and the drain of the MOS transistor 82. The inverter circuit configuration is such that an output signal is taken out. Next, the output circuit of FIG.
And a transistor 92.
It has a source follower circuit configuration in which a signal is input to the gate of the S transistor 91 and an output signal is extracted from the source of the MOS transistor 91. D. Problems to be Solved by the Invention Incidentally, there is a case where a low-pass filter circuit is connected to an output circuit having an inverter circuit configuration or an output circuit having a source follower circuit configuration as described above, and in such a case, Has the following problems. First, the conventional output circuit involves a change in DC level. That is, if the input DC level does not match the output DC level and a low-pass filter (LPF) circuit is connected to the output circuit of these inverters or source followers, it is necessary to increase the power supply voltage due to the fluctuation of the DC level. And the circuit design becomes complicated. Second, in the output circuit having the source follower circuit configuration, the gain is 0 dB or less, and the gain is further reduced when connected in multiple stages. Third, in the output circuit of the inverter circuit configuration,
There is a problem such as a change in the threshold voltage depending on the conditions of the manufacturing process, and it becomes difficult to perform an accurate operation when the threshold voltage changes. Finally, conventionally, signals handled by a delay element composed of a CCD or the like and a solid-state imaging device are analog signals, and a sufficient power supply voltage is used as compared with a semiconductor device such as a memory using many MOS transistors to ensure sufficient operation. However, the recent trend for lowering the voltage demands that the delay element and the solid-state imaging device, such as a CCD, be driven at a low voltage similar to a memory. In the case of such a low voltage, particularly, the margin on the level becomes small, and it becomes difficult to perform an accurate operation due to the fluctuation of the DC level as described above, and the circuit design thereof is also easy. Not. In view of the above-described problems, the present invention provides a delay element and a solid-state imaging device that can operate sufficiently even under a low voltage and can easily perform circuit design and the like, and that are resistant to manufacturing variations. It is an object of the present invention to provide a low-pass filter device in a charge transfer device. E. Means for Solving the Problems The low-pass filter device according to the present invention has a low-pass filter circuit, and a Barton circuit connected to at least the input side and the input side of the low-pass filter circuit. A Burton circuit, an operational amplifier that amplifies the difference between the input signal and the negatively fed-back feedback signal,
A source follower circuit or an inverter circuit to which the output of the operational amplifier is supplied, and a feedback signal is taken out from the output of the source follower circuit or the inverter circuit and is negatively fed back to the operational amplifier to obtain a DC level. Is constant and the gain is substantially 1. F. Action By connecting a Barton circuit with a constant DC level and a gain of about 1 to at least the input side of the low-pass filter circuit, it is possible to suppress the level fluctuations at each part of the circuit, and a single DC level The circuit design can be easily performed with reference to the equation (1), and this is particularly effective when the voltage is reduced or the function is increased. G. Embodiment A preferred embodiment of the present invention will be described with reference to the drawings. First Embodiment As shown in FIGS. 1 and 3, a low-pass filter device in a charge transfer device such as a delay element and a solid-state imaging device according to a first embodiment of the present invention has a low-pass filter circuit as a low-pass filter circuit. A Barton circuit, which is a buffer circuit having a constant DC level and a gain of approximately 1, is connected to both the input side and the output side using an active filter. First, the basic configuration will be described with reference to FIG. 1. For example, a source follower circuit 10 to which an output signal output from a floating gate of a CCD is input, and a Barton circuit 20 to make an output DC level constant are provided. An active low-pass filter circuit 50 is connected to the output side of the Barton circuit 20, and a Barton circuit 60 is connected to the output side of the active low-pass filter circuit 50. Here, with reference to FIG.
To explain, the Burton circuit 20 is an operational amplifier 20
A and a source follower circuit 20B. The output of the source follower circuit 20B is negatively fed back to the operational amplifier 20A. The whole Burton circuit 20 functions as a voltage follower, has a high input impedance, and has a low output impedance. Therefore, fluctuations in the DC level of the delay element and the low-pass filter device of the solid-state imaging device configured as described above are suppressed, and effective driving can be achieved even when various signal processing circuits are provided in the next stage. The Barton circuit 60 has the same configuration, and has a function of making the DC level constant and facilitating circuit design. The source follower circuit 10 and the Burton circuit 20
The source follower circuit 20B and the source follower circuit of the Burton circuit 60 may each be an inverter circuit.In particular, when an inverter circuit is used for the Burton circuits 20 and 60, the inverter circuit is a circuit in a feedback loop. For this reason, even when there is a change in transistor characteristics or the like due to process conditions, the influence on the circuit operation is small. Further, the source follower circuit 10 need not be provided, and a low-pass filter device having a configuration in which the Burton circuit 20, the active low-pass filter circuit 50, and the Burton circuit 60 are arranged in series may be used. Such a low-pass filter device in the delay element and the solid-state imaging device according to the present embodiment includes a Barton circuit 20, in which the DC level is constant and the gain is substantially 1, not only on the input side but also on the output side of the active low-pass filter circuit 50. Since 60 is provided, it is possible to suppress the fluctuation of the DC level and maintain the gain, and to simplify the circuit design. In addition, by providing the Barton circuit 60 on the output side, it is possible to cut off the influence on externally connected equipment and the influence from externally connected equipment, and realize stable operation. Even when a different externally connected device is used, the optimum operation can be performed without changing the internal circuit by simply changing the characteristics of the Burton circuit 60 in accordance with the characteristics of the externally connected device. FIG. 3 shows a specific example of such a low-pass filter device of the present embodiment. First, a source follower circuit is shown.
10 in series between the supply voltage and the ground voltage
An NMOS transistor 11 and an NMOS transistor 12 are provided. The gate of the NMOS transistor 11 is connected to, for example, a floating gate FG of a CCD and operates upon receiving an input signal, and an output signal is supplied from the source of the NMOS transistor 11 to the gate of the NMOS transistor 21 of the next-stage Burton circuit 20. You. The NMOS transistor 12 is used as a load. Next, the Burton circuit 20, which is a buffer circuit having a constant DC level and a gain of approximately 1, includes NMOS transistors 21 and 22 forming a differential transistor pair, PMOS transistors 23 and 24 connected to a current mirror, and a constant current. It comprises an operational amplifier circuit comprising an NMOS transistor 25 as a source, and a source follower circuit comprising NMOS transistors 26 and 27 arranged in series between a power supply voltage and a ground voltage. The output signal of the operational amplifier circuit extracted from the drain of the NMOS transistor 22 is output from the NMOS transistor 26.
The output signal of the source follower circuit which is input to the gate of the NMOS transistor 26 and taken out from the source of the NMOS transistor 26 is input to the gate of the negative input NMOS transistor 22 to form a negative feedback loop. Then, the above-mentioned NMOS which is the output section of this Burton circuit 20
An active low-pass filter circuit 50 is connected to the source of the transistor 26 as a low-pass filter circuit. The active low-pass filter circuit 50 is connected to a MOS transistor 51a functioning as a resistor, and the other end is connected to a capacitor 52a in a positive feedback loop and a MOS transistor 51b functioning as a second resistor.
A second capacitor 52b is connected to the other end of the S transistor 51b. The time constant characteristics of the active low-pass filter circuit 50 can be determined by the MOS transistors 51a and 51b and the capacitors 52a and 52b. An operational amplifier circuit is further connected from the other end of the MOS transistor 51b. The operational amplifier circuit includes NMOS transistors 53 and 54 forming a differential transistor pair and a PMOS transistor 55 connected to a current mirror. , 56 and an NMOS transistor 57 as a constant current source. The output of this operational amplifier circuit is the NMOS transistor
It is taken out from the drain of 54 and the source follower circuit
NM which is connected to the gate of the NMOS transistor 58 and is a load
The NMOS transistor which is a connection point of the OS transistor 59
From the source of 58, the NMOS transistor 54 of the above operational amplifier circuit
A negative feedback loop connected to the gates of the gates is formed. And the NMOS transistor with the negative feedback loop formed
The positive feedback loop having the capacitor 52a is taken out from the source of 58, and further from there, the next-stage Barton circuit
It is configured to be connected to 60. Subsequent to the active low-pass filter circuit 50, a Burton circuit 60, which is a buffer circuit having a constant DC level and a gain of approximately 1, is connected. The Barton circuit 60 is, similarly to the Barton circuit 20, operated by NMOS transistors 61 and 62 forming a differential transistor pair, PMOS transistors 63 and 64 connected to a current mirror, and an NMOS transistor 65 as a constant current source. It comprises an amplifier circuit and a source follower circuit comprising NMOS transistors 66 and 67 arranged in series between a power supply voltage and a ground voltage. The output signal of the operational amplifier circuit extracted from the drain of the NMOS transistor 62 is
A negative feedback loop is provided which is input to the gate of the NMOS transistor 66 and is input from the source of the NMOS transistor 66 to the gate of the NMOS transistor 62 having a negative input. And the above NM
An output signal is further extracted from the source of the OS transistor 66, and this output signal is transmitted to another signal processing device as an output signal of the low-pass filter device having the active low-pass filter. In the delay element and the low-pass filter device in the solid-state imaging device according to the present embodiment having the above-described configuration, the active low-pass filter circuit 50 includes the Barton circuit 20 and the Barton circuit 60 having a constant DC level and a gain of approximately 1. It is sandwiched between them. That is, DC is
The active low-pass filter circuit without level fluctuation
50 are arranged, and by arranging the barton circuit in this way, the low-pass filter device itself can be multifunctional without difficulty in circuit design. Also, since the DC level can be kept constant, CCD
Even when the power supply voltage of the low-pass filter device is set to a low voltage according to the trend of low voltage, etc., a large level margin can be ensured, and a sufficient dynamic range is taken to ensure sufficient operation. can do. Also, the Barton circuit has a feedback system, and even if the characteristics of the transistors constituting the feedback system fluctuate due to process conditions, the Barton circuit operates not in the transistor for direct driving but in the feedback system. As a result, it is possible to sufficiently reduce adverse effects due to variations in manufacturing process conditions. The NMOS transistors 11, 12, 26, 27, 58, 59, 66, 67 having the above-described source follower configuration may each have an inverter configuration.
And a circuit configuration in which the Barton circuit 20, the active low-pass filter circuit 50, and the Barton circuit 60 are connected in series. Second Embodiment As shown in FIGS. 4 and 5, the second embodiment of the low-pass filter device in the delay element and the solid-state imaging device has a circuit having a source follower configuration as an amplifier circuit, and has a DC level. Is connected to a circuit having a Barton circuit configuration as a buffer circuit having a constant and gain of approximately 1, a sample-and-hold circuit is connected thereto, and a buffer circuit having a constant DC level and a gain of approximately 1 is connected thereto, and , A low-pass filter circuit and a buffer circuit are arranged on the output side. First, the basic configuration will be described with reference to FIG. 4. For example, an output signal output from a floating gate of a CCD is output to a source follower circuit 10 which is input.
A Barton circuit 20 for keeping the DC level constant is connected. The output side of the Burton circuit 20 is connected to a sample-and-hold circuit 30 that operates while holding the level for a certain period of time.
A Burton circuit 40 is connected as a buffer circuit having a constant level and a gain of about 1. This Burton circuit
An active low-pass filter circuit 50 is connected to the output side of 40, and a Barton circuit 60 is connected to the output side of the active low-pass filter circuit 50. In the delay element and the low-pass filter device in the solid-state imaging device according to the present embodiment, the source follower circuit 10, the sample-and-hold circuit 30, and the active low-pass filter circuit 50 have a constant DC level and a gain of about 1 respectively. The Barton circuits 20, 40, and 60 divide the DC level and suppress the fluctuation of the DC level, maintain the gain, and simplify the circuit design. That is, since the Barton circuits 20, 40, and 60 each have high input and low output impedance, it is possible to ensure sufficient level margin and operate satisfactorily even with a Barton circuit configuration designed to reduce the voltage. Become. FIG. 5 is a specific example of such a delay element and a low-pass filter device in a solid-state imaging device,
First, an NMOS transistor 11 and an NMOS transistor 11 are connected in series between the power supply voltage and the ground voltage so as to constitute the source follower circuit 10.
A transistor 12 is provided. NMOS transistor 11
The gate of, for example, is connected to the floating gate FG of a CCD and operates by receiving an input signal, and its NMOS transistor
The output signal from the source 11 is the NMOS of the next-stage Burton circuit 20
The signal is supplied to the gate of the transistor 21. The NMOS transistor 12 is used as a load. Next, a Burton circuit 20, which is a buffer circuit having a constant DC level and a gain of about 1, includes NMOS transistors 21 and 22 forming a differential transistor pair and PMOS transistors 23 and 24 connected to a current mirror and a low constant voltage. NMO as a current source
An operational amplifier circuit comprising an S transistor 25, and NMOS transistors 26 and 2 arranged in series between a power supply voltage and a ground voltage.
7 and a source follower circuit. The output signal of the operational amplifier circuit extracted from the drain of the NMOS transistor 22 is input to the gate of the NMOS transistor 26, and the output signal of the source follower circuit extracted from the source of the NMOS transistor 26 is a negative input NMOS. The signal is input to the gate of the transistor 22 to form a negative feedback loop. Then, the above-mentioned NMOS which is the output section of this Burton circuit 20
The sample and hold circuit 30 is connected to the source of the transistor 26 in this embodiment. This sample and hold circuit 30
Is composed of a switching transistor 31 for transmitting a sample link signal to a gate, and a sample and hold capacitor 32. The operation of the sample-and-hold circuit 30 is such that the switching transistor 31 is turned on and off in response to a sample-and-hold pulse supplied to the gate of the switching transistor 31, and a certain level of a signal is applied to the sample-and-hold capacitor 32 by the operation. Stored. Next, a barton circuit 40, which is substantially the same as the barton circuit 20, is connected to the output side of the sample hold circuit 30. The Burton circuit 40 allows the sample-hold circuit 30 and the next active low-pass filter circuit
DC level fluctuations between 50 and 50 are suppressed, and there is no decrease in gain. The Burton circuit 40 includes NMOS transistors 41 and 42 forming a differential transistor pair, PMOSs 43 and 44 connected to a current mirror, and an NMOS transistor 4 as a constant current source.
5 and a source follower circuit including NMOS transistors 46 and 47 arranged in series between the power supply voltage and the ground voltage. The output signal of the operational amplifier circuit extracted from the drain of the NMOS transistor 42 is input to the gate of the NMOS transistor 46, and the output signal of the source follower circuit extracted from the source of the NMOS transistor 46 is a negative input NMOS. The signal is input to the gate of the transistor 42 to form a negative feedback loop. Next, as for the active low-pass filter circuit 50 arranged on the output side of the Burton circuit 40, the NMOS of the Burton circuit 40 is similar to that of the second embodiment.
The source of the transistor 46 is connected to the MOS transistor 51a functioning as a resistor, the other end is connected to the capacitor 52a in the positive feedback loop and the MOS transistor 51b functioning as the second resistor, and the other end of the MOS transistor 51b is connected to the other end. , And the second capacitor 52b are connected. These MOS transistors 51a and 51b and the capacitor 52
a, 52b, the active low-pass filter circuit 5
A time constant characteristic of 0 can be determined. And the above MOS
An operational amplifier circuit is further connected from the other end of the transistor 51b. The operational amplifier circuit includes NMOS transistors 53 and 54 forming a differential transistor pair, and PMOS transistors 55 and 56 connected to a current mirror and a constant current amplifier. It comprises an NMOS transistor 57 as a current source. The output of this operational amplifier circuit is taken out from the drain of the NMOS transistor 54, connected to the gate of the NMOS transistor 58 of the source follower circuit, and from the source of the NMOS transistor 58 that is the connection point of the load NMOS transistor 59. A negative feedback loop connected to the gate of the NMOS transistor 54 of the operational amplifier circuit is formed. And
A positive feedback loop having the capacitor 52a is taken out from the source of the NMOS transistor 58 in which the negative feedback loop is formed, and further connected therefrom to the next-stage Burton circuit 60. Subsequent to the active low-pass filter circuit 50, a Burton circuit 60, which is a buffer circuit having a constant DC level and a gain of approximately 1, is connected. The Barton circuit 60 is, similarly to the Barton circuit 20, an arithmetic operation including NMOS transistors 61 and 62 forming a differential transistor pair, PMOS transistors 63 and 64 connected to a current mirror, and an NMOS transistor 65 as a constant current source. It comprises an amplifier circuit and a source follower circuit comprising NMOS transistors 66 and 67 arranged in series between a power supply voltage and a ground voltage. The output signal of the operational amplifier circuit extracted from the drain of the NMOS transistor 62 is
A negative feedback loop is provided which is input to the gate of the NMOS transistor 66 and is input from the source of the NMOS transistor 66 to the gate of the NMOS transistor 62 having a negative input. And the above NM
An output signal is further extracted from the source of the OS transistor 66, and this output signal is transmitted to another signal processing device as an output signal of the low-pass filter device having the active low-pass filter. In the delay element and the low-pass filter device in the solid-state imaging device according to the present embodiment having such a configuration, the sample-and-hold circuit 30 and the active low-pass filter circuit 50 have a constant DC level and a gain of approximately 1 respectively.
And are arranged between the Burton circuits 20, 40, and 60. Therefore, in each of these Burton circuits 20, 40, 60
Variations in DC level can be effectively suppressed, and the sample-hold circuit 30 and the active low-pass filter circuit 50 can be arranged without difficulty in circuit design. In addition, even when the power supply voltage of the low-pass filter device is set to a low voltage in accordance with the trend of lowering the voltage of a CCD or the like, a large level margin can be secured, and sufficient operation can be performed by increasing the dynamic range. In addition, even if the characteristics and the like of the transistor fluctuate due to the process conditions, in the feedback system, the adverse effect due to the fluctuation of the manufacturing process conditions can be sufficiently reduced. Further, the Barton circuit configuration of each of the Barton circuits 20, 40, 60 and the low-pass filter circuit 50 has the same circuit configuration, which is convenient for circuit layout work and handling in a process. Each of the NMOS transistors 11, 12, 26, 27, 46, 47, 58, 59, 66 and 67 having the above-described source follower configuration may have an inverter configuration, and may have a configuration without the source follower circuit 10. It is good. Further, in the above-described embodiment, a low-pass filter circuit in which a Barton circuit is connected as a buffer circuit and a sample-and-hold circuit is added has been described. However, the present invention is not limited to this. It is also possible to adopt a configuration in which the DC level is held between buffer circuits having a constant DC level and a gain of about 1. H. Effects of the Invention The low-pass filter device in the charge transfer device such as the delay element and the solid-state imaging device of the present invention uses a buffer circuit having a constant DC level and a gain of approximately 1, and this buffer circuit allows the DC level to be reduced. Variations can be suppressed, the level margin can be increased, and the dynamic range of the low-pass filter device can be increased. For this reason, it is possible to easily design a circuit even when the voltage is reduced, which is advantageous when a multi-function is achieved. In particular, by providing a buffer circuit on the output side,
In addition to blocking the effects on external devices and the effects of external devices, stable operation can be achieved, and the buffer circuit on the output side can be used for external devices that vary in characteristics or have different characteristics. The optimum operation can be performed only by changing the characteristics without changing the internal circuit. Further, even if the characteristics of the transistor in the feedback system fluctuate, the low-pass filter device of the present invention can sufficiently reduce the adverse effect on the process.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a delay element and a low-pass filter device in a solid-state imaging device according to a first embodiment of the present invention, and FIG. 2 is a specific configuration of a Barton circuit of the low-pass filter device. FIG. 3 is a circuit diagram showing a circuit configuration of the low-pass filter device according to the first embodiment, and FIG. 4 is a second embodiment of the low-pass filter device in the delay element and solid-state imaging device according to the present invention. FIG. 5 is a block diagram according to an example, and FIG. 5 is a circuit diagram showing a circuit configuration of a low-pass filter device according to the second embodiment. FIG. 6 is a circuit diagram showing an example of a conventional delay element for explaining a problem and an output circuit in a solid-state imaging device. FIG. 7 is an output circuit of the conventional solid-state imaging device for explaining a problem. FIG. 9 is a circuit diagram showing another example of the embodiment. 10 Source follower circuit 20 Barton circuit 30 Sample hold circuit 40 Barton circuit 50 Active low-pass filter circuit 60 Barton circuit

Continuation of front page    (72) Inventor ▲ Shin ▼ Yasuhito Castle               6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo So               Knee Co., Ltd.                (56) References JP-A-61-49565 (JP, A)                 JP-A-50-81452 (JP, A)

Claims (1)

(57) [Claims] A low-pass filter device in a charge transfer device, comprising: a low-pass filter circuit; and a Barton circuit connected to both an input side and an output side of the low-pass filter circuit and having a constant DC level and a gain of approximately 1. 2. The Barton circuit includes an operational amplifier that amplifies a difference between an input signal and a negatively fed-back feedback signal, and a source follower circuit or an inverter circuit to which an output of the operational amplifier is supplied, and the source follower circuit or the inverter circuit. 2. A low-pass filter device in a charge transfer device according to claim 1, wherein a feedback signal is taken out from the output of said first amplifier and negatively fed back to said operational amplifier so that its gain is made substantially 1. 3. 2. The low-pass filter device according to claim 1, wherein the charge transfer device is a charge-coupled device. 4. A low-pass filter circuit; and a barton circuit connected to an input side of the low-pass filter circuit, wherein the barton circuit amplifies a difference between an input signal and a negative-feedback feedback signal;
A source follower circuit or an inverter circuit to which the output of the operational amplifier is supplied, and a feedback signal is extracted from the output of the source follower circuit or the inverter circuit and is negatively fed back to the operational amplifier.
A low-pass filter device in a charge transfer device, wherein the DC level is constant and the gain is substantially 1. 5. The low-pass filter device according to claim 4, wherein the charge transfer device is a charge-coupled device.