JP2886838B2 - Apparatus and method for parallel decoding of variable length instructions in super scalar pipelined data processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to a superscalar processor utilizing variable length instructions. More particularly, the present invention relates to a memory and method for storing and utilizing instruction boundary information within a sequence of instructions stored in a cache memory to enable parallel decoding of multiple variable length instructions.

[0002]

2. Description of the Related Art Stored program controlled digital computers typically include a main memory for storing program instructions and data. The main memory supplies program instructions and data to functional units such as an arithmetic logic unit (ALU) and a floating point unit (FPU) in a central processing unit (CPU) for execution. Reduced instruction set computer (RISC) CPUs typically utilize fixed length instructions. On the other hand, a compound instruction set computer (CIS)
The CPU of C) is, for example, a CI of x86 architecture.
In the case of the SC type CPU, a variable length instruction of 1 to 12 bytes is used (unless the prefix code is counted).

[0003] Cache memories are often connected to CPUs and other functional units to take advantage of the spatial and temporal localization of instruction reference locations. The spatial locality of a reference is the tendency of instructions to be stored sequentially in the same order as the order of execution. Temporal locality of reference is the tendency of functional units to repeatedly access the same instruction.
Temporal localization of the reference location is caused by program flow control instructions such as loops, branches and subroutines that cause the functional unit to repeatedly execute certain instructions that were executed last. Thus, functional units tend to repeatedly access instructions stored at the same location in memory.

In order to take advantage of the spatial and temporal locality characteristics of instruction execution and storage, an entire sequence of localized instructions is copied from main memory to cache memory. Generally speaking, a data word (e.g., typically a byte sized unit) is structured into a continuous data line of, for example, 64 data words. When an instruction is fetched (fetched), the entire data line storing the instruction (or the entire plurality of data lines if the instruction connects a large number of data lines) is read from the main memory and the cache memory is read. Is written to the storage location of the cache line. Thus, when the entire sequence of instructions is loaded (entered) into the cache memory, the cache memory may store the same instruction as the previously accessed instruction, or (data whose future accesses are already stored in the cache memory). The likelihood of achieving future access to an instruction that has not yet been accessed (for other instructions corresponding to the line) increases.

[0005] The use of the cache memory improves the system performance because the access time of the cache memory, ie, the time to fetch an instruction, is shorter than that of the slow main memory. However, an instruction that does not exist in the cache memory may be requested. In this case, a so-called “cache miss” occurs. In the case of a cache miss, the requested instruction must be obtained from main memory. However, in most cases, due to temporal and spatial localization,
The requested instruction is in the cache memory and a so-called "cache hit" occurs. A cache hit means that the requested instruction is obtained from a high speed cache memory. In digital computer systems, the ratio of "cache hits" to instructions in cache memory can be on the order of 90% due to the locality of references.

In the genealogy of CPU development, CPU
Initially, the functional unit receives a sequence of instructions,
Designed to execute instructions. Such CPUs
It is called a "scalar" processor because it executes only one instruction at a time. The operating speed of conventional scalar processors has been pushed to the limit by advances in circuit technology, computer architecture, and computer architecture. However, with each new generation of computing devices, there is a need to find new acceleration mechanisms for conventional scalar machines.

[0007] Modern processors generally use a technique known as pipelining to increase performance. The pipeline method is an instruction execution technique similar to an assembly line. The execution of instructions often involves fetching the instructions from memory, decoding the instructions into their respective operations and operands, fetching the operands of the instruction, and applying the decoded operations to the operands (hereinafter, the instruction "Execute"),
It is envisioned to include a series of steps for storing the result in a memory or register. According to the pipelined technique, a series of steps of execution processing are overlapped between subsequent instructions. For example, while the CPU stores the result of the first instruction in the instruction sequence, the CPU simultaneously
, Fetches the operand of the third instruction in the sequence, decodes the fourth instruction in the sequence, and fetches the fifth instruction in the sequence. Pipelining thus reduces the execution time for a sequence of instructions.

Another technique for improving performance involves executing two or more instructions in parallel, ie, simultaneously. Processors utilizing this technique are commonly referred to as superscalar processors. Such processors are somewhat arbitrary and incorporate additional technology in which the sequence of instructions is executed in a different order than the strictly sequential order in which the sequence of instructions is stored, and the results of the instructions are stored. There is. This technique is referred to as out-of-order issue and out-of-order completion, respectively.

[0009] The ability of a superscalar processor to execute two or more instructions simultaneously depends on the particular instruction being executed. Similarly, the flexibility to issue or complete instructions out of order depends on the particular instruction to be issued or completed. There are three types of instruction dependencies, referred to as resource conflicts, procedural dependencies, and data dependencies. Resource conflicts occur when two instructions executing in parallel compete for access to the same resource, for example, the system bus. Data dependencies are number one
Occurs when the value stored in a register or memory subsequently accessed is changed by a second instruction that is completed later.

Data dependencies include "true data dependencies", "opposite dependencies" and "output data dependencies".
Are classified into three types. In this regard, Mike Johnson's "Superscalar Micropr
ocessor Design) ", pages 9-24 (1991). An instruction that uses a value calculated by a previous instruction has a" true "(or data) dependency on the previous instruction. An example of a dependency relationship is that the first and second sequential instructions both assign the same register or memory location to different values, and the third instruction following the first and second instructions stores the same in the register or memory. Occurs on an out-of-order completion using the stored value as an operand.
The third instruction is not allowed to complete after the later (second) instruction, otherwise the third instruction will take the wrong value.
One example of an opposite dependency occurs during an out-of-order execution, where an instruction executed out of order and before the preceding instruction destroys the value used by the preceding instruction. As an example of a true dependency, an output dependency, and an opposite dependency, the following sequence of instructions: (1) R3: = R3 Operation R5 (2) R4: = R3 + 1 (3) R3: = R5 + 1 (4 R7: = R3 Assume operation R4. Instruction (2) has a true dependency on instruction (1) because the value stored in R3 to be used as the operand of instruction (2) is determined by instruction (1). Instruction (3) changes the contents of register R3,
Instruction (3) has the opposite dependency on instruction (2). If instruction (3) were executed before instruction (2) in a disturbed order, instruction (2) would have the wrong value stored in register R3, especially the value as modified by instruction (3). Use Instructions (1) and (3) have output dependencies. Instruction (1) is not allowed to be performed after instruction (3) in a disturbed order. Since the resulting value as determined by instruction (3) must be the last value stored in register R3 and not the resulting value as determined by instruction (1), instruction (4) ) Indicates the register R
3 for the correct operand value stored in Erroneous dependencies are eliminated using register renaming techniques and reordering buffers.

A procedural dependency occurs when the execution of a first instruction depends on the result of the execution of a preceding instruction, such as a branch instruction. See Mike Johnson, "Superscalar Microprocessor Design," pages 57-77 (1991) in this regard. It is difficult to know for sure whether a particular branch will be taken. For simplicity, it is assumed that the branch instruction is an instruction that continues execution at some pre-specified non-sequential address or that continues execution sequentially with the immediately following instruction. In the former case, so-called branching is performed, and in the latter case, so-called branching is not performed. Branch instructions are complicated by including indexed branch instructions in which the address at which execution continues at the time of the branch changes dynamically according to the value stored in the memory or register. However, a description of such an indexed branch instruction is not particularly made. Therefore, it is difficult to reliably know the sequence of instructions to be executed after the branch instruction. Nevertheless, to predict whether or not a branch will be taken, a number of branch prediction techniques are used which can provide an accuracy of about 90%. By using branch prediction techniques, a prediction is made as to whether a branch will be taken. A sequence of instructions to be executed if the prediction is correct is fetched and executed. However, any result of such an instruction is only treated as "indeterminate" until the branch instruction is actually executed. When the branch instruction is executed, a determination is made as to whether the prediction is correct. If the conclusion of the branch instruction is correctly predicted, the above "uncertain result" is accepted. However, if a branch is incorrectly predicted, a recovery phase of the prediction failure is performed by recovering / discarding the indeterminate result and fetching the sequence of instructions for correct execution.

A number of techniques are used to make branch predictions using software and / or hardware. For example, by using a software compiler, a prediction can be made from the original source code that is related to whether a branch is taken. The prediction can be static (does not change during execution) or dynamic (changes during execution). Two dynamic hardware branch prediction schemes use a 2-bit counter, such as a Pentium® processor, or a dual-level counter, such as a Pentium Pro® processor. Use a branch target buffer. According to the simple branch target buffer technique, it is estimated that each branch instruction does not take a branch at first. When a branch is taken, each branch instruction is executed, so the address at which the execution branches is stored, for example, in a branch target buffer operated as a queue. Next, each branch instruction is identified during an instruction fetch cycle. It is predicted that the branch for each instruction starts from the address of the head address of the branch target buffer queue. In this way, at least one instruction provided at the address starting from the address specified at the head of the branch target buffer queue is fetched. If the branch is not taken when the branch instruction is executed, the prediction is wrong. In such a case, branch prediction failure recovery is performed and the branch target buffer queue is not updated. Or,
If the branch is taken when the branch instruction is taken, and if the address at which the execution branch did not match the head address of the branch target buffer queue, the branch prediction is again incorrect. In such a case, the new address is stored in the branch target buffer queue (at the tail), and branch prediction recovery is performed. On the other hand, if a branch is taken and the branch address of the execution matches the head address of the branch target buffer queue, the branch is correctly predicted. The address is removed from the head of the branch target buffer queue and stored at the tail.

The instruction set of a CISC processor contains instructions of variable length. Once packed end-to-end in memory, the start and end of an individual CISC instruction cannot be easily identified without any prior knowledge or indication of the boundaries of each instruction. . Therefore,
A finite amount of time is consumed in separating variable length instructions during an instruction fetch operation. Since the start of an instruction cannot be determined until the length (and end) of the immediately preceding instruction has been determined, the finite time can be easily determined by overlapping the instruction separation stage with other instruction execution stages. I can't recover. This disadvantage becomes more pronounced as the complexity of the instruction set architecture increases (eg, as the number of allowed instruction lengths increases).

As processor design trends shift from single-issue scalar to high-performance, pipelined, superscalar systems, the need for parallel decoding of multiple instructions arises. Since the next instruction cannot be decoded until the length of the preceding instruction is known, it is difficult to decode many variable-length instructions in parallel. This problem is important in superscalar CISC architectures, but not in superscalar RISC architectures, which use fixed-length instructions so that the start and end locations of each instruction can be determined in a simple manner.

In the CISC architecture, an instruction cache is used to receive instructions from memory and hold the instructions until a functional unit can easily accept the instruction. Thus, instructions are fetched earlier for input to the decoder. The decoder decodes the instruction before entering the functional unit for execution. The advent of superscalar (eg, multi-function unit) microprocessors, such as Intel® Pentium Pro®, utilizes each functional unit for as many clock cycles as possible (functional units are Should not be unnecessarily dormant). This has led to the development of several schemes for decoding variable length instructions in a superscalar pipelined environment.

A prefetcher is provided for fetching instructions from cache or main memory. The contents of the prefetcher typically indicate the starting address of the cache where the next instruction is to be fetched. The design of the prefetcher takes into account the use of fixed length instructions or variable length instructions, as is the case in certain systems. In prior art processors utilizing variable length instructions, when the instruction cache is first loaded, the prefetcher or instruction cache has no way of knowing the word array, ie, where any instruction starts and ends. Thus, when the prefetcher requests an instruction, the instruction cache needs to fetch a large contiguous (consecutive) sequence of data words from the cache. The above sequence must be large enough to achieve the maximum achievable instruction length to ensure that all data words in the desired instruction are included in the sequence. Unfortunately, this means that the prefetcher cache probes the sequence of data words provided by the cache memory and discards data words prior to the desired instruction before transferring the instruction to other elements of the system. Means that you need to.
This is a significant limitation in superscalar systems. The reason is that the prefetcher must use several clock cycles to determine the exact start and end of the desired instruction.

Several prior art techniques have been considered to address this problem. Advanced Micro Device (registered trademark)
AMD5K86 (R), Intel (R)
The Pentium (R) and Pentium Pro (R) processors use various schemes to decode a large number of variable length instructions in parallel. AMD5
K86® decodes (pre-decodes) x86 instructions in advance when they are fetched from memory and written to the instruction cache. During pre-decoding, the pre-decoder writes
Add 5 bits to each byte. These bits are mainly used to indicate the status of the byte in the instruction. The status specifically records whether a byte is at the beginning or end of an instruction. A disadvantage of the predecoding technique is that the predecode bits significantly increase the size of the instruction cache. Extra hardware is required to accommodate and process the large number of predecode bits in the AMD5K86® scheme. In this regard, M. Slater says, “AMD's K5 Design is designed to go beyond Pentium.
ed to Outrun Pentium) ", Microprocessor Report, Vol. 8, No. 14, Pages 1, 6-11, 1994.
See October, 2010.

On the other hand, Pentium (registered trademark) records an instruction boundary inside each line of the instruction cache. The boundaries are recorded to maintain split line accesses that allow instructions to extend line boundaries to be fetched in a single clock cycle. When an instruction is first decoded, the length of the instruction is sent back to the instruction cache. Each instruction cache directory entry marks an instruction boundary inside the line. However, how such directory entry marks are maintained and used,
That is, it is not completely clear how many bits are used for marks, whether they are allocated based on data lines, data words or instructions, where they are stored, etc. . In this regard, D. Anderson's Pentium Processor System Architecture (Pen
tium Processor System Architecture) ", 2nd edition, 1
Published in 995, Intel's "Pentium Pro (R) Processor Microarchitecture Journey (A Tou
r of the Pentium Pro Processor Microarchitecture)
”, (Http://intel.com/procs/ppro/info/p6 white / in
dex.htm) and L. Gwennap, "Intel's P6 Uses Decoupled Superscalar Desig
n) ", Microprocessor Report, Vol. 9, No. 2,
See pages 9-15, published February 1995.

[0019]

Another decoder scheme for superscalar systems is disclosed in US Pat.
No. 2,967, No. 5,337,415, No. 5,45
No. 9,844 and 5,488,745. All of the above patents provide pre-decoding or storage of boundary information for variable byte length instructions,
Includes important additional hardware components. Therefore, in order to maximize parallel processing at a reduced hardware cost, there is a need for a technique for decoding a large number of variable-length instructions in parallel using the minimum additional hardware components.

[0020]

These and other objects are achieved by the present invention. According to one embodiment, a method is provided for determining the start and end of each instruction of a variable length instruction set. The data line is stored in a first storage area that is, for example, an instruction cache. Each data line is
Construct a sequence of data words stored at sequential addresses in main memory. The data line contains a number of encoded variable length instructions stored adjacent to main memory. A number of indicators, including an indicator associated with each data word of the data line stored in the first storage area, are stored in the second storage area. Each indicator indicates whether the associated data word is the first data word of a variable length instruction.

According to another embodiment, a sequence of data words is fetched from at least one sequential data line stored in a cache. The sequence of fetched data words includes the starting data word and at least the number of data words in the maximum allowable length instruction.
A plurality of indicators (ie, a vector of indicators) are fetched from a second storage area containing an indicator associated with each data word of the fetched sequence. By using the indicator as a delimiter of the sequence of instructions to be decoded, at least one non-overlapping sub-sequence in the sequence of data words is identified, wherein each sub-sequence of the data word is different Included in instructions to be decoded sequentially. Each subsequence of the data word is decoded as a separate instruction.

For example, the length of each instruction is determined separately and simultaneously without using delimiter indicators. These lengths are compared to the indicia to determine if they match. The instruction sequence is output for distribution to one or more functional units. The sequence of instructions comprises a first instruction beginning with a start data word of the fetched sequence of data words, and one or more sequentially following the first data, wherein the vector of the fetched indicator matches the determined length. And each of the other instructions preceded by only that instruction.
For example, a vector of replacement markers is generated from the determined length. By using the replacement indicator vector, each variable length instruction preceded by at least one instruction whose fetched indicator vector does not match the determined length is reparsed from the fetched sequence of data words ( Structural analysis) and re-decode.

According to another embodiment, a method for updating an indicator is provided. At least one sequence of instructions to be decoded is identified from the sequence of data words fetched from the cache using a vector of indicators fetched from the second storage area. The identified sequence of instructions to be decoded is decoded. Simultaneously with decoding the instructions, the first and last data words of each instruction in the sequence of instructions to be decoded are located without using an indicator. The length is used to verify the accuracy of the fetched instruction. A replacement indicator is generated according to the first and last data words thus placed and stored in the second storage area instead of the obtained indicator.

For example, the processing system is realized together with the first and second storage areas. The prefetcher receives a sequence of data words containing instructions to be decoded from a first storage area and receives a vector of indicators from a second storage area. The prefetcher uses indicators as delimiters to parse one or more variable length instructions for simultaneous output to multiple decoders. The prefetcher further outputs the indicator vector and the parsed instruction to the instruction length collator. The instruction length collator performs many tasks simultaneously while the decoder decodes the instruction. The instruction length collator determines the length of each instruction without using an indicator. For example, an instruction length checker traverses a sequence of data words to determine the length of each instruction (ie, the first and last data words). The instruction length collator can simultaneously determine the length of multiple instructions in a single cycle. The instruction length collator outputs a vector of the indicator determined from the length to be stored in the second storage area.
The instruction length checker also causes re-parsing and re-decoding of the instruction word preceded by one or more instructions whose indicator did not match the instruction length. this is,
A suitable signal containing the newly determined vector of signs,
This is achieved by outputting to a prefetcher and a decoder.

[0025]

BRIEF DESCRIPTION OF THE DRAWINGS A better understanding of the present invention may be obtained by reading the following detailed description with reference to the accompanying drawings, in which: FIG. As shown in FIG. 1, the superscalar pipeline data processing system 10 includes, for example, an instruction cache 30, an instruction prefetcher 50, an instruction length collator 70,
It is composed of M (M> 1) decoders 80 and N (N> 1) functional units 100. Processing system 1
0 may include other components such as a data cache (not shown). Functional unit 100 controls a portion of processing system 10 based on the instructions received. Examples of the functional unit 100 are an ALU and an FPU, but the functional unit may be any device that executes instructions.

For example, the processing system 10 further includes an instruction boundary memory 20 and a tag memory 40. The instruction boundary memory 20, the instruction cache 30 and the tag memory 40 are provided in a storage area of a single memory structure or the instruction boundary memory 20.
And the instruction cache 30 and the tag memory 40 are realized as storage areas of a memory circuit that can be accessed separately. For example, the instruction cache 30 is structured into fixed length cache line locations, each consisting of the same number of bytes, for example, 16 bytes. The tag memory 40 has an array of tags including one tag element corresponding to each cache line storage location in the instruction cache 30. Each tag element includes an indicator (bit) indicating whether the corresponding storage location contains invalid data, unmodified valid data, modified valid data, and the like. A description of the operation of "dominance" of cache and data lines, write-forward schemes and memory integrity is beyond the scope of the present invention, but transfers data between an I / O device and main memory. Memory-consistent prior dominance method and system (Memor
y Consistent Pre-Ownership Method and System forTr
ansferring Data Between an I / O Device and a Main M
emory) "in U.S. patent application Ser. No. 08 / 071,721. Instruction boundary memory 20 is described in further detail below. In addition, branch target buffer 60 is connected to prefetcher 50. Branch The target buffer 60 estimates the outcome of the branch instruction and allows additional parallelization of the instruction under certain circumstances.

1. Instruction Boundary and Instruction Cache Array Structure For example, instruction cache 30 has a V × U two-dimensional byte array 300 of data words (eg, bytes), as shown in FIG. Instruction cache array 3
00 has U data line storage locations with a line size of V data words (eg, bytes).
The most significant data word in each cache line of instruction cache array 300 is byte V-1 (310).
The least significant data word in each cache line of instruction cache array 300 is byte 0 (301). The uppermost cache line of the instruction cache array 300 is the line U-1 (359). Instruction cache array 30
The least significant cache line of 0 is line 0 (351).

The instruction reads the entire data line or the data line containing the instruction from main memory (assuming the instruction potentially extends to more than one data line) and stores the data line in the cache line of the instruction cache. Loaded by writing to the location. For example, assume that the instruction is 1 to 6 data words long, each address is 16 bits long, and the size V of the data line is 16 bytes. Address 0001 0000 0000 0010 That is, 409
Assume that instruction 8 is to be executed, but that instruction does not exist in instruction cache 30. In this case, the data line 40 including the data words 4096 to 4111
The entirety of 96 is read from main memory and stored, for example, in cache line X of instruction cache 30. It is known in advance that the first data word of the instruction is the third data word of the data line stored in the instruction cache array 300. However, the first data word of the successively following instructions has addresses 4099, 4100, 4101, 4101
Whether it begins at 102, 4103 or 4104 is unknown until the length of the instruction starting at address 4098 (ie, the last data word) is determined.

For this purpose, the instruction boundary memory 20 has a two-dimensional array 400 of V × U indicators as shown in FIGS. 5 and 7 to 9. For example, each indicator may be implemented with a single bit. Each indicator in the instruction boundary memory 400 corresponds to a unique data word location in the instruction cache array 300. For example, 0 ≦ u ≦ U and 0 ≦ v ≦
When V, the indicator u = 0, v = 0 corresponds to the data word stored in cache line 0 at position 0 of instruction cache array 300, and the indicator u = 0, v = 1 corresponds to the instruction cache. Corresponds to the data word stored in cache line 0 at position 1 of array 300, and so on. For an 8-kiloword instruction cache array 300, a one kilogram indicator (1 kilobit) is required in the indicator array 400 to hold the necessary boundary information. Each indicator in indicator array 400 has a corresponding instruction cache array 30
Used to specify whether the data word in 0 is the first or first data word of the instruction. If the data word is the first data word in the instruction, the corresponding indicator bit in indicator array 400 is set to, for example, one, otherwise the indicator bit in indicator array 400 is set to zero. You.

The instruction boundary memory 20 is a prefetch unit 50
Is in the form of a vector of indicators including one indicator bit corresponding to each data word in the sequence of data words transferred by the instruction cache 30 to the prefetcher 50. The vector of indicators is comprised of a sequence of "0" indicator bits and "1" indicator bits, the first "1" indicator bit being the first data word of the instruction in the data line output by instruction cache 30. Corresponds to the location. The length of the current instruction is (first of current instruction
An indicator labeled "1" for the current instruction (indicating the first data word of the next instruction) and a "1" for the truly next instruction (indicating the first data word of the next instruction). Corresponds to a partition with an indicator bit. The prefetcher 50 receives the indicator vector from the instruction boundary memory 20 and uses the indicator vector to identify the currently requested instruction boundary. For example, the prefetcher 50
Parses the vector of beacons to place the beacon bits given the first value "1". The indicator bit given the first value "1" corresponds to the first or first data word of the very next instruction to be executed. The prefetch unit 50 then outputs the second occurring value “1”.
Places the beacon bits given the beacon vector in the beacon vector indicating the first data word of the immediately following instruction as stored on the data line. Using such information, the prefetcher 50 can determine the length of the instruction and, more importantly, the last or last data word. After the head and tail storage locations have been identified, the data words that make up the complete instruction are known. For example, the prefetcher 50 can parse a number of variable length instructions simultaneously (ie, in parallel) in each cycle.

2. Operation of Instruction Boundary Memory The process of executing an instruction and updating the instruction boundary memory 20 is described with reference to the flowcharts of FIGS. In step 202, prefetcher 50 requests a sequence of data words (including two or more instructions) from instruction cache 30. If there has been a "read miss", the cache controller (not shown) sends a 2 including the sequence of data words requested from main memory (not shown).
Take out more than one data line. Instruction cache 30
If there was a "read hit," then in accordance with step 204 of FIG. 2, instruction cache 30 causes sequence of adjacent data words in instruction cache array 300 to be large enough to ensure that the entire instruction is contained. Fetch. Such a sequence includes all data words from a particular offset within a cache line of the instruction cache 30 and more than one of the first few data words of the immediately following cache line. here,
“Next” is determined with respect to the address of the data line,
It does not necessarily have to be adjacent to the instruction cache array 300. The consumption rate of the data word by the decoder 80 is
It should be noted that the rate of data word creation by the prefetcher 50 need not match. In such a case, the prefetcher 50 has a buffer in which the data words of the previously fetched instruction are stored while presented for decoding. In one embodiment, the prefetcher 50 fetches a fixed number of data words from the instruction cache 30 when the occupancy of the data words in the buffer of the prefetcher 50 drops below a certain level. The prefetcher 50 places the first data word of the immediately following instruction and, to ensure that the sequence of data words output for decoding by the decoder 80 are contiguous, e.g. "Rotate" and pack. The sequence of fetched data words is, for example, at least as long as the instruction of the maximum allowable length. At the same time that the data word is fetched, the instruction boundary memory 20 stores the data in step 2 of FIG.
To complete 04, the boundary information is output to the prefetch unit 50 in the form of a vector of indicators.

In step 206 of FIG. 2, the prefetcher 50 parses and outputs two or more variable-length instructions from a sequence of data words at the same time. In performing its operation, the prefetcher 50 examines the vector of indicators to split the obtained information into separate instructions. As described above, the prefetcher 50 is provided with the first and second occurring values "1" to determine the first data word of the immediately next instruction to be executed and the immediately following instruction. Look up the sign looking for the indicated sign bit. The information output by parsing the data word corresponds to the first instruction. Similarly, the prefetcher 50 searches for an indicator bit given a third occurring value "1" to determine the end or last data word of the immediately following instruction, and so on. Such "searching" is not performed, for example, linearly, but rather by inputting the vector of indicators into a suitable logic circuit which extracts / parses the sequence of data words into a sequence of two or more separate instructions. Done. The above circuits are within the skill of those in the art and will not be reviewed here for simplicity. The instructions thus parsed are output to the respective decoders 80. For example, if there are four decoders 80, a sequence of four data words is parsed and output. All instructions thus parsed or split are output to the instruction length collator 70 along with a vector of indicators. As shown, decoding by the decoder 80 and collation of the instruction length (more specifically, the accuracy of the indicator vector) by the instruction length collator 70 are performed in parallel.

In step 208 of FIG. 2, each decoder 80 attempts to decode the instruction provided by prefetcher 50. In step 209, which is performed in parallel with step 208, the instruction length collator 70 collates the correct instruction length for the instruction supplied by the prefetcher 50. In particular, the instruction length collator 70 extracts each instruction from the sequence of data words and records the first or first data thus extracted. Instruction length collator 70
Can match the length of multiple instructions simultaneously (ie, in parallel). For example, if there are four decoders 80, the prefetcher preferably parses a subsequence of four data words. The four subsequences are received in parallel by an instruction length collator 70 that simultaneously determines the length of each instruction included in the data word subsequence. The lengths of the instructions thus determined identify the boundaries of each instruction. The collated instruction information generated by the instruction length collator 70 is formed in the form of a marker vector similar to the marker vector output by the instruction boundary memory 20. The accurate boundary information after collation is written from the instruction length collator 70 to the instruction boundary memory 20. In order to reduce the number of times of writing, the instruction length collating unit 70 sets the instruction boundary memory 20 only when the indicator received from the instruction boundary memory 20 includes an error.
Rewrite the sign of.

From the instruction boundary memory 20 to the prefetcher 5
Note that there is no guarantee that the vector of indicators initially fetched at 0 will indicate exactly whether the corresponding data word is the first data word of the instruction contained in the sequence of fetched data words. is necessary. Such uncertainties occur in several situations. The first situation is
This is the case when the instruction data word is not required to maintain its state during execution (eg, a self-modifying code). The second situation is when the cache line storage location for a data line in the instruction cache 30 is overwritten from another data line (ie, another location in main memory) according to a rewrite or cache flushing scheme. In such a case, the corresponding indicator vector is reset, i.e., each indicator bit associated with the cache line storage location in the instruction cache 30 has the value "0".
Is reset to In any case, the instruction boundary information is not available for newly written data lines. Therefore,
There is no doubt that the current value of the indicator bit will accurately reflect the boundary of the instruction contained in the cache line location of the cache. The third situation is when the indicator stored in array 400 is reset when CPU 10 is initialized. The cache flushes or rewrites the data based on the data lines, while the sequence of data and the vector of indicators provided to the prefetcher 50 are aligned within each data line, or the instruction cache 30. It should be noted that the above scheme can be very complex because it does not need to be completely contained within a single cache line storage location. Further, it should be noted that the branch target buffer 60 constantly outputs the prediction result of the executed branch instruction. Such a prediction, even if it is rare, will cause the execution to branch to a data line that has been invalidated, for example, by being flushed from the instruction cache 30 or overwritten by another data line. May indicate an increase in the occurrence of the situation.

It should be noted that the start and end data words of the instruction need not be aligned with data line boundaries. This is a function of the tight packing of variable length instructions and of branch instructions that result in a branch to an instruction beginning at every data word in the data line. As mentioned above,
Prefetcher 50 may fetch a discontinuous sequence of data words starting in the middle of a data line. When the prefetcher 50 operates in such a manner, the prefetcher 50 needs to record the starting data word position of such a data line. After the instruction length collator 70 determines the boundary indicator vector, the boundary indicator vector rewrites the instruction boundary memory 20 using the starting data word position stored in the prefetcher 50. If the sequence of fetched data words extends over two or more data lines, for example, a multiple write consisting of a single write for each data line on which the sequence of fetched data words extends to rewrite the vector of the boundary indicator is necessary. Assume that multiple decoders 80 can increase the length of the sequence of fetched data words, ie, the number of data lines over which the sequence of fetched data words extends. This increases the number of write operations performed by the instruction length collator 70 when rewriting the indicator vector. If multiple writes are required to store the vector of indicators and the instruction boundary memory 20 is not fast enough to perform each pending write operation, the buffer leaves the writes pending. There must be. Of course, even if buffering
Even if the possibility of parallel decoding is reduced, no error occurs. Similarly, if the obtained boundary indicator vector is verified to be accurate by the instruction length collator 70, there is no need to update the instruction boundary memory 20. This has the advantage of reducing the number of writes performed on the instruction boundary memory 20.

It should be further noted that the output vector of markers contains only the markers corresponding to a part of the data line obtained for decoding, rather than all the markers corresponding to the complete data line. It is. For example, a circuit capable of performing such a partial update is provided. According to step 210, the instruction length collator 70 converts the boundary information provided by the prefetcher 50 (ie, the vector of indicators initially provided by the instruction boundary memory 20) into
The instruction length is compared with the confirmed instruction length as determined by the instruction length collator 70. First, consider the case where the collated instruction length confirms the boundary information supplied by the prefetch unit 50. For example, consider the case where the first data word and the instruction length as determined by the instruction length collator 70 match the first data word specified by the indicator vector first output by the instruction boundary memory 20. In such a case, the instruction length collator 70 may determine whether the first decoded instruction or an instruction whose instruction length determined by the instruction length collator 70 matches the indicator used to parse the decoded instruction. Only output an enable signal to each decoder 80 that receives the preceding decoded instruction. The enable signal is
Decoder 80 for transferring the decoded instruction to dispatch logic 90 in accordance with step 214
To a usable state.

Next, it is assumed that the instruction length determined by the instruction length collator 70 does not adapt or match the boundary information fetched from the instruction boundary memory 20. That is, the boundary information is missing, incomplete, or incorrect. In such a case, the instruction length collator 70 receives each instruction preceded by two or more instructions parsed using an indicator that does not match the length determined by the instruction length collator 70, according to step 212. Decoder 8
A disable (use disabled state) signal is output to 0.

It should be noted that the first data word of the first sequence of data words is the first data word to which the sequence of data words has been parsed. Thus, the first data word of the first instruction formed from the first data sequence is always exactly aligned. Therefore,
The first instruction is a decoder 80 that receives the first data sequence.
Is always decoded. Furthermore, it is possible that the first data word in the second sequence of data words following the first sequence is exactly aligned with the start of the second instruction. In such a case, the first and second instructions are decoded by respective decoders 80, and so on. Generally speaking,
The first sequence of unaligned data words is identified by the instruction length collator 70. Note that the first sequence of unaligned data words cannot be the first sequence of parsed data words. The instruction length collator 70 then decodes the sequence of unaligned data words and receives each of the parsed sequence of data words after the first sequence of unaligned data words. The decoder 80 and the decoder 80 are disabled. This is because the sequence of all data words parsed after the first unaligned sequence is also considered unaligned.

The disabling of the appropriate decoder 80 can be accomplished in a number of ways. For example, the parsed instruction word is output to a series of decoders 80.
If one of the decoders 80 is to be disabled because it has received a sequence of unaligned data words, then each decoder 80 that receives the sequentially parsed data words is also disabled. State. For example, this may include a sequentially following decoder 80 (receiving a sequence of successive data words) with a disable signal.
Is achieved by the decoder 80 which is disabled. Such a disable signal propagates from the decoder to the next decoder 80 that has received a successive instruction, and so on. The instruction length collator 70 further reparses the instruction from the sequence of data words using the (updated) boundary information by the prefetcher 50 and outputs the reparsed information to the decoder 80. Let them be done at the same time. Note that the exact boundary information is transferred to the prefetcher by the instruction length collator 70 in this step.

At step 216, it is assumed that the boundary information is correct, valid instructions have been decoded by decoder 80, and the instructions decoded at step 214 have been written to dispatch logic 90. In step 216, the dispatch logic 90
Functional unit 100 to execute each decoded instruction
Is determined. Certain functional units are utilized depending on the above instructions, such as instructions for performing floating point operations, instructions for performing branch condition tests and address rules, and the like. The superscalar processor includes at least one functional unit 100. In that case, at least one functional unit 100 is simultaneously selected, if possible, to execute the instructions in parallel. The plurality of functional units 100 can maintain the same function, or can maintain a subset of functions in which a certain subset of the functional units 100 overlaps. It is advantageous for two or more functional units 100 to execute frequently used instructions simultaneously, thereby increasing instruction level execution parallelism. After the functional unit 100 is selected, the dispatch logic 90 transfers the decoded instruction to the functional unit 100. According to step 218,
Functional unit 100 executes the decoded instruction.
In step 220, the above process is repeated until all requested instructions have been executed.

Although steps 202 through 220 are shown sequentially, they may be performed by respective units in parallel according to the paradigm of pipelined processing.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The best example of the structure, function and updating of the instruction boundary memory 20 will be described below. A. At power-up or replacement of the instruction cache data line All valid labels in the data line tag array 40 and the label array 400 are reset to "0" (ie, "clear") after power-up. The cleared label sequence is shown in FIG.
And the cleared data line tag sequence is shown in FIG. Further, when an instruction cache line, such as instruction cache line 359, is replaced or marked invalid, the corresponding indicator vector, such as row 459 of the corresponding indicator array, is reset to "0". You.

B. Initial Fetching of Instructions and Initial Loading of Indicator Array In this example, the instruction cache array 300 is loaded with instructions as shown in FIG. Various instructions are shown in lines 351, 354-356 of the cache array of FIG. The cache line 359 in FIG.
No orders are accommodated. This is to indicate that the valid / invalid bit in the corresponding data line tag array 40 is cleared, indicating that cache line 359 contains invalid data. The cache line 359 can theoretically store any invalid and meaningless data. For clarity and simplicity, cache line 359
Indicates a case where the value 0 includes only the given data. Each instruction is contained in a data word in one or more adjacent cache lines of the cache array 300.
For example, instructions are shown to be sequentially ordered and occupy adjacent lines 355,356. For example, in FIG. 6, one 5-data word instruction is a data word v = V−2 of data line u = X (355).
Starting from (309), the data line u = X + 1 (35
6) End with data word v = 2. The preceding instruction,
That is, the instruction that appears before the above five data word instruction is:
The data word v = V− of the data line u = X (355)
3 (308), data line u = X (355)
From the data word v = 1 (302). 5 above
The instruction following the data word will cause the data word v = 3 on line u = X + 1 (356), as shown in FIG.
(Not shown), and the line u = X + 1 (35
The processing ends with the data word v = V−2 (309) in 6).
However, this is not the only or typical way for instructions to be cached. Rather, data lines containing a sequence of instructions may also be located in non-sequential or non-contiguous cache line storage locations in the instruction cache 300, depending, inter alia, on the structure of the cache (eg, set-association) and the manner of replacement. I do not care.

When the execution is started, the prefetch unit 5
0 is supplied only with the memory address of the first data word of the current instruction to be executed (available from a program counter not shown). No information is provided about the number of data words, or the address of the last data word of the immediately following instruction, and no information is available about the address of the first data word of any subsequent instructions. Thus, the prefetcher 50 includes the first data word and the number of data words following the first data word such that at least the maximum number of data words that can be provided in the instruction is fetched. By requesting a sequence of data words, only five data word instructions are obtained. In this case, the series is the cache line X
It is considered to include data words from (355) data word V-2 (309) to cache line X + 1 (356) data word 3 (not shown).

At the same time that the instruction cache 30 transfers the instruction to the prefetcher 50, the instruction boundary memory 20
Instruction cache array 3 transferred to prefetcher 50
Transfer the vector of indicators corresponding to each data word in 00. However, in the case of the above example, the label sequence 400
The state at the time of power-on in which all the signs are set to “0” or the cleared state is maintained. Thus, in the above example, all the indicator bits (from the indicator of bit V-2 of row X (455) to the indicator of bit 3 (not shown) of row X + 1 (456)) are currently set to "0". Is set,
Indicates that boundary information cannot be obtained for the requested instruction.

As mentioned above, the prefetcher 50 cannot determine whether it has the correct information. On the contrary, the indicator bit is provided to the logic circuit,
So, despite the error in the case of the above example, the indicator is marked where the instruction ends (for multiple instructions,
Extract the requested instruction from the sequence of data words received as a delimiter for (where they begin). The incorrectly parsed desired instruction data word is output to one of the decoders 80. However, it should be noted that the first data word in the first instruction is known. Thus, the primary decoder 80, which receives a subsequence of data words starting from the first data word, can decode the first instruction as described above, even if the indicator is wrong.

While the decoder 80 is decoding the instruction, the instruction length collator 70 determines whether the instruction provided by the prefetcher 50 was correctly parsed by determining the length of the instruction in the instruction boundary in the indicator bit. Judge by comparing with information. Therefore, the instruction length collator 70
The instructions and indicators output to each decoder 80 are received. If the instruction length collator 70 determines that the indicator correctly delimits the instruction based on a distinct instruction length collation, the instruction length collator 70 outputs the decoded instruction to the dispatch logic 90. Therefore, all the decoders 80 are made usable. In this case, the indicator does not accurately indicate the length of the instruction decoded by decoder 80. Thus, the instruction length collator 70 outputs a disable signal to the decoder 80 supplied with a sequence of data words that are not aligned with the first data word of the instruction, except for the primary decoder 80 that receives the first instruction. On the other hand, the primary decoder 80
Is the first data word aligned with the first data word of the first instruction.
Is provided. If the primary decoder 80 is provided with a sequence of data words equal in length to the maximum length instruction, the primary decoder 80 can always decode the first instruction, regardless of whether the indicator is correct. Similarly, assume that the length of the first instruction is verified as correct and the length of the second instruction is not verified as correct. In this case, the sequence of data words of the second instruction is nevertheless aligned with the beginning of the second instruction (even though the sequence of data words of the third instruction is not aligned with the third instruction). Can be The first and second instructions are both decoded by respective decoders 80, and so on.

The disabled decoder 80 stops outputting the decoded instruction to the dispatch logic circuit 90. The instruction length collator 70 includes a sign array 400
The correct indicator vector for storage into the instruction boundary memory 2
Output to 0. The corrected beacon bits, together with a signal that causes the prefetcher 50 to reparse the instruction preceded by at least one undecoded instruction that the instruction length collator 70 cannot verify the length, along with the prefetcher 50 Is output to

An instruction to start a data word location;
After receiving the appropriate indicator bit vector from the instruction length collator 70, the instruction boundary memory 20 stores the indicator bit vector in an appropriate location. In this case, the indicator bits v = V-1 (410) and V-2 (40) on row u = X (455)
9) and the indicator bit v on line u = X + 1 (456)
= 0 to v = 2 (not shown) are changed to '01' and '000', respectively. In other words, the indicator is updated to reflect that the first instruction is 5 data words long. The instruction length collator 70 performs the above update based on, for example, one cache line at a time. Thus, the indicator bit subsequence '01' determined for the two most significant bytes of cache line X is updated immediately. This is shown in FIG. However, the instruction length collator 70 defers updating the indicator bit subsequence '000' until, for example, all data words to be processed in the cache line X + 1 are decoded and the indicator bits are obtained. . This is shown in FIG. For example, the update of the indicator bit is deferred until the last data word of the cache line is decoded, or until a branch to an instruction in another cache line is made. In any case, decoding of the data word in a particular cache line is stopped. Until such time, when the indicator bits are generated, they are concatenated by the instruction length collator 70 to the not yet updated indicator bits to form a sequence of vector bits for the cache line.

During instruction re-parsing, the prefetcher 50 uses the exact boundary information as provided by the instruction length collator 70. Thus, subsequent comparisons by the instruction matcher 70 indicate that the instruction is correct.
In that case, the instruction length collator 70 instructs each decoder 80 whose respective decoded instruction length has been collated to output the re-decoded instruction to the dispatch logic circuit 90 for subsequent execution by the functional unit 100. I do.
At the same time, the instruction length collator 70 makes the prefetch unit 70
Indicates that the current instruction is valid and will process the next instruction.

In the process of fetching and re-fetching various instructions from the instruction cache 30, the instruction length collator 7
"0" gradually updates the instruction boundary memory 20. Note that for simplicity in the above description, only a single instruction is fetched and decoded. Advantageously, multiple instructions are fetched and decoded by prefetcher 50 simultaneously. In this way, incremental determination of boundary information is obtained very quickly. If all instructions in instruction cache 30 have been fetched and their lengths have been determined at least once by instruction length collator 70, all boundary information for the above instructions is available in instruction boundary memory 20. FIG. 9 shows the instruction cache array 3 shown in FIG.
An indicator array 400 is shown that includes boundary information for each instruction stored at 00. As mentioned above, the invention very advantageously exploits the spatial and temporal localization of the reference properties of the instructions. "Hit" in the processor's instruction cache 30
Given the fact that the rate is typically greater than 90%, the success rate using the present invention for parallel decoding of multiple instructions is very high.

C. Executing Instructions Using Instruction Boundary Memory Information In this example, the instruction cache array 300 remains unchanged from the previous example. Instruction cache array 3
The contents of 00 are shown in FIG. However, since each instruction in instruction cache 30 has been fetched at least once, the boundary information in boundary information array 20 accurately reflects the start (and end) of each instruction in the corresponding instruction cache array. . The instruction boundary information of the indicator array 400 is shown in FIG. The exact context of the information placed in the beacon array 400 typically results from the temporal and spatial localization of the reference characteristics of the instructions in a superscalar processing system.

As noted above, various instructions are stored in the cache array data line locations 351, 354 through 35 of FIG.
6 is shown. Instructions are not contained in data line location 359 of FIG. Each instruction is in cache array 3
00 are contained in adjacent data words in one or more data line locations. For example, in FIG.
The five data word instructions have data line locations X +
1 (356) ends at data word 2 (303), and data word V-2 at data line storage location X (355).
It starts from (309). The instruction preceding the five data word instruction above terminates at data word V-3 (308) at data line storage location X (355), and terminates at data line X (3
55) starting at data word 1 (302). The instruction following the five data word instruction above ends at data word V-2 (309) at data line location X + 1 (356) and begins at data word 3 (not shown) at data line X + 1 (356).

As in the previous example, the prefetcher 50
When requesting a data word instruction, the prefetcher 50
By requesting a sequence of data words from data word 3 (not shown) at data line storage location X + 1 (356) to, for example, data word V-2 (309) at data line storage location X (355). Make that request. This ensures that the longest instruction word can be extracted from the fetched data word.

At the same time that the instruction cache 30 outputs an instruction to the prefetcher 50, the instruction boundary memory 20
The prefetcher 50 retrieves a vector of indicators corresponding to the sequence of data words output from the instruction cache array 300.
Output to In this example, the indicator vector array 400 whose contents are shown in FIG. 9 includes two “1” bits indicating the head of the requested instruction and the head of the immediately following instruction. The prefetcher 50 uses the vector of indicators, in particular, the relative position of the "1" indicator bits, to parse the next instruction from the sequence of data words. By using the boundary information provided by the instruction boundary memory 20,
If multiple instructions are to be fetched in parallel, the time required to obtain the requested instruction and provide it to decoder 80 is significantly reduced. Assume that the vector of indicators indicates the delimiter of each instruction in the subsequence and can be used to parse or split each instruction simultaneously.

While the decoder 80 decodes the instruction parsed by the prefetcher 50, the instruction length checker 70 checks the length of the instruction given by the prefetcher 50 against the vector of the indicator. An instruction whose preceding length is such that the corresponding length, as determined independently by the instruction length collator 70 (only from the sequence of data words), matches an instruction boundary as specified by the vector of indicators. , The instruction length collator 70 calculates
The decoder 80 that has received the instruction is enabled to output the decoded instruction to the dispatch logic circuit 90. It should be noted that the above example describes the case where a single instruction is parsed, decoded, and matched. The instruction length collator 70 can simultaneously collate the length of the sequence of each parsed data word output by the prefetcher 50 in an arbitrary cycle.

The above is a description of the arrangement and operation of one embodiment of the present invention. The scope of the present invention is intended to include the above embodiments, as well as other embodiments that would be apparent to those skilled in the art.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a digital processing device of the present invention.

FIG. 2 is a flowchart showing the operation of the digital processing device of the present invention.

FIG. 3 is a flowchart showing the operation of the digital processing device of the present invention.

FIG. 4 is a table showing an array of data line tags stored in a tag array in a clear (power-on) state.

FIG. 5 is a chart showing an array of indicators stored in an instruction boundary memory in a clear (power-on or refresh) state.

FIG. 6 is a chart representing an array of data words stored in the instruction cache after the instruction has been written to the instruction cache.

FIG. 7 is a diagram representing an array of indicators stored in the instruction boundary memory after an instruction has been loaded into the instruction cache.

FIG. 8: After the boundary information for an instruction is determined,
5 is a chart showing an arrangement of indicators in an instruction boundary memory.

FIG. 9 is a chart representing an array of indicators in an instruction boundary memory after boundary information has been determined for all instructions in the instruction cache.

[Description of Signs] 10 Superscalar pipelined data processing device 20 instruction boundary memory 30 instruction cache 40 tag memory 50 instruction prefetcher 60 branch target buffer 70 instruction length collator 80 decoder 90 dispatch logic circuit 100 functional unit 300 byte array 400 Indicator sequence

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/38 G06F 9/32

Claims (24)

(57) [Claims] 1. A method for determining the start and end of each instruction in a processor which decodes and executes a number of instructions of variable length in a single cycle, comprising: (a) storing a sequential address in a main memory; Storing, in a cache, each data line comprised of a sequence of stored data words and including a plurality of encoded variable length instructions stored contiguously in said memory; Storing in memory a plurality of indicators associated with each data word, including an indicator indicating whether the associated data word is the first data word of a variable length instruction. And (c) said indicator stored in said memory in response to initialization of said processor, so as not to indicate that any data word is the first data word of a variable length instruction. 2. The method of claim 1, further comprising the step of resetting. 3. fetching a sequence of adjacent data words of one or more data lines of said cache;
Fetching a vector of indicators including an indicator associated with each data word of the fetched subsequence; and Parsing the subsequence into one or more variable length instructions in parallel, wherein the method is used as a data word delimiter. And (e) simultaneously decoding the parsed sequence of each variable-length instruction; and (f) simultaneously performing the step (e) without using the vector of the indicator. Simultaneously determining the length of each of said variable length instructions to determine whether said indicator vector matches said determined length; and (g) distributing to at least one functional unit.
A first instruction beginning with the first data word of the sequence of fetched data words, and at least one instruction that sequentially follows the first instruction and whose vector of indicators matches the determined length; Outputting an instruction sequence including each of the other instructions preceded by: 5. A step of: (h) generating a vector of replacement indicators from the determined length; and (i) using the vector of replacement indicators to fetch the fetched data word from the subsequence of the fetched data words. 5. The method of claim 4, further comprising the step of reparsing and re-decoding each of said variable length instructions preceded by at least one instruction whose vector of indices does not match said determined length. (H) distributing each of the simultaneously output decoded instructions to at least one of the plurality of functional units; and (i) decoding each of the decoded instructions. Executing the instructions in parallel on the at least one functional unit to which the instructions have been distributed. 7. E) determining the length of each instruction without using the indicator; f) generating a vector of replacement indicators from the determined length; Instead of the fetched indicator vector above,
Storing the vector of replacement markers in the memory. 8. The step (g) comprises: (g1) assigning the vector of the indicator to each of the data lines of the data line and each of the vectors associated with a data word of the corresponding data line. 8. The method of claim 7, comprising: dividing into a first plurality of marker sub-sequences including markers; and (g2) storing the respective marker sub-sequences during separate storage stages. 9. (g3) Until the steps (c), (e) and (f) are performed on data lines other than the data line corresponding to the subsequence in which the step (g2) is postponed, the portion of each marker (G4) deferring the step (g2) for the sequence; (g4) performing a step (c) on the second sequence of data words to obtain a vector of the second indicator and a subsequence of the second plurality of indicators; Performing (e), (f) and (g1); and (g5) concatenating the marker subsequences from the first and second plurality of subsequences corresponding to the same data line. The method of claim 8, further comprising: (C) overwriting or overwriting the data line in the cache memory so as not to indicate that the data word of the overwritten or invalidated data line is the first data of the variable length instruction; The method of claim 1, further comprising resetting each indicator associated with each data word of the overwritten or invalidated data line in response to invalidating the data line in the cache memory. 11. A method of decoding one or more instructions in a processor that decodes and executes multiple instructions of variable length in a single cycle, comprising: (a) starting with the first data word, Fetching a sequence of data words of one or more data lines stored in a cache, including a sequence of at least a maximum number of data words in an acceptable instruction; and (b) each of the sequences of the fetched sequence. Fetching from the cache a plurality of indicators pertaining to data words, including an indicator of whether each of the data words is the first data word of an instruction; and (c) separate sequential decoding. Said sequence of instructions to be decoded, constituted by instructions, identifying one or more non-overlapping subsequences in said sequence of data words. And (d) decoding the data words of each subsequence as separate instructions. 12. A method for decoding and executing one or more instructions in a processor that decodes and executes multiple instructions of variable length in a single cycle, the method comprising: (a) decoding each data word of a series of data words; Related,
Utilizing a plurality of indicators obtained from the memory including an indicator indicating whether the relevant data word is the first data word of the instruction, the data in the cache including each data word of the sequence of instructions to be decoded. Identifying a sequence of one or more instructions to be decoded from the sequence of words; (b) decoding the identified sequence of instructions to be decoded; and (c) the step (b). Locating the first and last data words of each instruction in the sequence of instructions to be decoded without using the indicator and verifying the accuracy of the indicator at the same time while performing (D) generating a replacement indicator according to the first and last data words located in step (c), and replacing the obtained indicator with the replacement indicator instead of the obtained indicator. The method comprising the step of storing the directory. 13. A processor for decoding and executing a number of instructions of variable length in a single cycle and determining the first and last data words of each instruction, comprising: (a) a sequential address of main memory; A first cache memory area comprising a series of data words stored in the first cache memory area for storing each data line including a number of encoded variable length instructions stored contiguously in the memory; A second memory area associated with each data word of the data line and storing a plurality of indicators including an indicator indicating whether the associated data word is the first data word of a variable length instruction. 14. In response to initialization of the processor, the second memory area has therein no data word indicating that it is the first data word of a variable length instruction. 14. The processing device according to claim 13, wherein the stored marker is reset. 15. (c) Fetching a sequence of adjacent data words of one or more data lines of the cache and fetching a vector of indicators including an indicator associated with each data word of the fetched subsequence. And prefetching using the indicator of the vector as a delimiter for adjacent data words included in the fetched data word subsequence to parse the subsequence into one or more variable length instructions in parallel. 14. The processing apparatus according to claim 13, further comprising a vessel. 16. (d) a plurality of decoders for individually decoding separate instructions in each of the parallel parsed variable length instructions; and (e) the decoder decodes the parsed variable length instruction words. At the same time, without using the vector of the indicator, simultaneously determine the length of each instruction,
An instruction length checker for determining whether the vector of the indicator is equal to the determined length; the decoder comprising: a first instruction starting from a first data word of the sequence of fetched data words; And decoding each of the instruction sequences successively following the first instruction and including each other instruction preceded by at least one instruction whose vector of indicators is equal to the determined length; 16. The processing device according to claim 15, further comprising: receiving from the instruction length collator an enable signal for enabling the decoder to output decoded instructions for distribution to one of the functional units. . 17. The instruction length collator generates a vector of replacement indicators from the determined length, and the prefetcher generates a vector of the fetched indicator from the subsequence of the fetched data words. Uses the vector of permutation indicators to reparse each of the variable length instructions preceded by at least one instruction that does not match the determined length, wherein the decoder converts the reparsed instruction to 17. The processing device according to claim 16, wherein re-decoding is performed in parallel. 18. The method according to claim 17, wherein each of the simultaneously output decoded instructions comprises at least one of a plurality of functional units.
17. The processing apparatus according to claim 16, further comprising: a dispatch logic circuit provided to one of the functional units; and (g) a plurality of functional units that execute the decoded instructions in parallel. (D) an instruction length collator for determining the length of each of the instructions without using the indicator, and generating a vector of a replacement indicator from the determined length; 16. The processing device according to claim 15, wherein the memory area stores the vector of the replacement marker in the memory instead of the vector of the fetched marker. 20. The instruction length checker corresponds to the vector of the indicator to a separate one of the data lines and includes each indicator of the vector associated with a data word of the corresponding one of the data lines. 20. The processing device according to claim 19, wherein the processing is divided into a first plurality of marker sub-sequences, and the sub-sequences of the respective markers are stored during separate storage steps. 21. The instruction length collator may generate a replacement indicator vector for at least one instruction in a data line other than the data line corresponding to the subsequence whose storage is postponed. Deferring the storage of the sub-sequence of each sign, the instruction length collator acquires the vector of the second sign and the sub-sequence of the second plurality of signs, and 21. The processing device according to claim 20, wherein the sub-sequences of the signs from the first and second plural sub-sequences are connected. 22. The second memory area, wherein the data word of the overwritten or invalidated data line does not indicate that it is the first data of a variable length instruction.
In response to the first memory area overwriting the data line therein or disabling the data line therein, each of the first memory area associated with the respective data word of the overwritten or invalidated data line. 14. The processing device according to claim 13, wherein the sign is reset. 23. A processing device for decoding and executing a number of variable-length instructions in a single cycle and decoding one or more instructions, comprising: (a) a plurality of variable-length instructions stored adjacently; And (b) indicating whether each of the data words in the data line stored in the cache is the first data word of a variable length instruction. (C) one or more sequential data lines stored in the cache, including: (c) a first data word, and at least a number of data words in the longest allowable instruction. Fetching from the cache a plurality of indicators associated with each of the data words of the fetched sequence; A prefetch comprising instructions to be loaded and using the indicator as a delimiter of the sequence of instructions to be decoded to identify one or more non-overlapping subsequences in the sequence of data words. And (d) a plurality of decoders including a decoder for decoding the data words of each subsequence as separate instructions. 24. A processor for decoding and executing multiple instructions of variable length in a single cycle, comprising: (a) associated with each data word of a sequence of data words;
Utilizing a plurality of indicators obtained from the memory including an indicator indicating whether the relevant data word is the first data word of the instruction, the data in the cache including each data word of the sequence of instructions to be decoded. A prefetcher for identifying from the sequence of words one or more sequences of instructions to be decoded; (b) a plurality of decoders for decoding each instruction in the identified sequence of instructions to be decoded; (C) While the decoder is decoding the instructions in the sequence, at the same time, without using the indicator, locate the first and last data words of each instruction in the sequence of instructions to be decoded. An instruction length checker that checks and verifies the accuracy of the indicator and generates a replacement indicator according to the first and last data words; Processing apparatus comprising a memory for storing the replacement indicator instead of identification.