JP2885254B2 - Baud timing extraction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a baud timing extracting circuit for extracting a baud timing from a .pi. / 4 shifted QPSK signal whose phase has been shifted by .pi. / 4.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, for example, a baud timing extraction circuit of this kind inputs a π / 4-shifted QPSK signal a in which the phase has been previously shifted by π / 4, and
A baud rate extraction unit 1 that extracts a clock having the same cycle as the 4-shift QPSK signal a and outputs it as a baud rate clock b, a delay element 6 for fixedly delaying the baud rate clock b, and a state where the signal has passed through the delay element 2 And the π / 4 shift Q
The PSK signal a is input, the phase of the π / 4 shift QPSK signal a is measured based on the measurement timing determined by the measurement timing clock c, and the phase difference of the π / 4 shift QPSK signal a between adjacent measurement timings is measured. Is output as phase shift amount information.

[0003] Such a baud timing extraction circuit includes a baud rate clock b output from a baud rate extraction unit 1.
And the π / 4 shift QPS input to the phase shift amount measurement circuit 3
The phase difference from the K signal a is measured in advance, and the delay amount of the delay element 6 with respect to the baud rate clock b is fixedly determined based on the characteristics of the phase difference.

[0004] Further, π /
When band limitation is performed on the 4-shift QPSK signal a, as shown in FIG.
It is interposed between the K signal a and the phase shift amount measurement circuit 3 to obtain phase shift amount information d in a band-limited state.

[0005]

In the above-mentioned baud timing extraction circuit, the baud rate clock b is fixedly delayed by the delay element 6, so that if the delay amount of the delay element 6 varies, the phase shift amount The information d also varies, and as a result, the baud timing extraction circuit cannot be uniformly commercialized. In other words, since the delay amount of the delay element 6 needs to be matched with the phase difference characteristic between the π / 4 shift QPSK signal a and the baud rate clock b, the configuration of the baud rate extraction unit 1 and the phase shift amount measurement circuit 3 If there is variation in the electronic components, adjustment in the manufacturing process of the baud timing extraction circuit, and the manufacturer must select a delay element 6 having a delay amount that matches the variation. The operation of selecting the delay element 6 is extremely complicated for the adjustment and the manufacturer.

Further, if there is an amplitude change in the π / 4 shift QPSK signal “a” or a deviation in the baud rate clock “b”, the baud timing extraction circuit must be configured so as not to increase the error fluctuation of the phase difference. However, at present, realization of such a baud timing extraction circuit is viewed as a challenge.

In addition, when the band is limited using the filter 7 as shown in FIG.
The phase of the shift QPSK signal a is likely to vary. In such a case, the amount of delay of the delay element 6 must be adjusted for each baud timing extraction circuit, and the operation of selecting the delay element 6 becomes complicated as in the case described above.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and its technical problem is to minimize the error fluctuation of the phase difference without using a delay element, and to achieve an accurate measurement. Another object of the present invention is to provide a baud timing extraction circuit capable of obtaining information on a large amount of phase shift.

[0009]

According to the present invention, a π / 4 shifted QPSK signal having a phase shifted by π / 4 is input,
A baud rate extraction unit that extracts a clock having the same cycle as the π / 4 shift QPSK signal and outputs the same as a baud rate clock, and inputs a measurement timing clock generated by fixedly delaying the π / 4 shift QPSK signal and the baud rate clock. Π / 4 shift QPSK based on the measurement timing determined by the measurement timing clock.
A phase shift amount measurement circuit for measuring the phase of the signal and outputting the phase difference between the π / 4 shifted QPSK signals between adjacent measurement timings as phase shift amount information. A variable delay circuit that inputs a delay control signal, variably delays the baud rate clock based on the predetermined delay control signal, and outputs the result as a variable measurement timing clock; A timing error detection circuit that detects a shift between a variable measurement timing and a baud timing generated when measuring a phase difference in a circuit and outputs the shift as a shift detection signal, and a delay amount that generates a predetermined delay control signal based on phase shift amount information And a control circuit, the delay amount control circuit generates a predetermined delay control signal based on the shift detection signal, The variable measurement timing clock in the variable delay circuit is controlled, and the phase shift amount measurement circuit inputs the π / 4 shift QPSK signal and the variable measurement timing clock, and based on the variable measurement timing determined by the variable measurement timing clock, A baud timing extraction circuit is obtained which measures the phase of the / 4 shift QPSK signal and obtains the phase shift amount information from the phase difference of the π / 4 shift QPSK signal between adjacent variable measurement timings.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the baud timing extraction circuit of the present invention will be described in detail with reference to embodiments. FIG. 1 is a block diagram showing a basic configuration of a baud timing extraction circuit according to one embodiment of the present invention.

A baud timing extracting circuit receives a π / 4 shifted QPSK signal a, extracts a clock having the same period as the π / 4 shifted QPSK signal, and outputs it as a baud rate clock b. A variable delay circuit 2 that receives the signal f, variably delays the baud rate clock b based on the predetermined delay control signal f, and outputs the baud rate clock b as a variable measurement timing clock c ′;
A π / 4 shift QPSK signal and a variable measurement timing clock c ′ are input, and the variable measurement timing clock c ′ is input.
Π / 4 based on the variable measurement timing determined by
A phase shift amount measuring circuit 3 for measuring the phase of the shifted QPSK signal a, measuring the phase difference between the π / 4 shifted QPSK signals a between adjacent variable measurement timings, and outputting it as phase shift amount information d. .

The baud timing extracting circuit inputs the phase shift amount information d and detects a shift between the variable measurement timing and the baud timing generated when the phase shift amount measuring circuit 3 measures the phase difference. A timing error detection circuit 4 that outputs a signal e, a predetermined delay control signal f is generated based on the shift detection signal e from the timing error detection circuit 4, and a variable measurement timing clock (delay clock) in the variable delay circuit 2. And c) a delay amount control circuit 5 for controlling c ′.

The phase shift amount information d output from the phase shift amount measurement circuit 3 is used as data decoding information. If the variable measurement timing matches the baud timing, ± π / Take a value corresponding to any of 4, ± 3π / 4. However, if the variable measurement timing deviates from the baud timing, the phase shift amount information d is mixed in adjacent baud sections and deviates from four values of ± π / 4, ± 3π / 4. The timing error detection circuit 4 is for detecting the deviation at this time.

The baud timing extraction circuit having such a configuration provides the phase shift amount information d output from the phase shift amount measurement circuit 3.
, The deviation between the variable measurement timing and the baud timing that occurs when the phase difference is measured is detected by the timing error detection circuit 4, and the variable measurement timing clock c 'is controlled by the delay amount control circuit 5. At this time, the delay amount of the variable measurement timing clock c ′ is increased or decreased by the predetermined delay control signal f from the delay amount control circuit 5 so that the timing error of the deviation detection signal e is minimized. Here, the delay amount control circuit 5 holds the delay control signal f sent to the variable delay circuit 2 for a predetermined time. As a result, the baud timing extraction circuit of the present invention suppresses the error variation of the phase difference in the phase shift amount information d to a minimum, so that accurate phase shift amount information d can be obtained. The present invention is not limited to the embodiment, since a filter can be inserted in the baud timing extraction circuit shown in FIG.

[0015]

As described above, according to the baud timing extraction circuit of the present invention, the baud rate clock having the same period as the π / 4 shift QPSK signal extracted by the baud rate extraction unit is input to the variable delay circuit. And outputs a variable measurement timing clock variably delayed based on the delay control signal of the π / 4 shift QPSK signal based on the variable measurement timing determined by the variable measurement timing clock in the phase shift amount measurement circuit. To measure the phase shift amount information between adjacent variable measurement timings.
In addition to obtaining the phase difference of the / 4 shift QPSK signal, the timing error detection circuit outputs a deviation detection signal that detects the deviation between the variable measurement timing and the baud timing generated when measuring the phase difference of the phase shift amount information. Along with
By using a configuration in which a predetermined delay control signal for controlling the variable measurement timing clock from the delay amount control circuit is increased or decreased so that the timing error of the deviation detection signal is minimized, the delay element is not used. Since it is possible to obtain accurate phase shift information while minimizing phase difference error fluctuations in phase shift amount information, accurate phase shift information is always obtained, and some Even if there is variation,
The effect can be eliminated. As a result, the regulation of the baud rate extraction unit can be relaxed, and the filter can be freely inserted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a baud timing extraction circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional baud timing extraction circuit.

FIG. 3 is a block diagram showing another example of the conventional baud timing extraction circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Baud rate extraction part 2 Variable delay circuit 3 Phase shift amount measurement circuit 4 Timing error detection circuit 5 Delay amount control circuit 6 Delay element 7 Filter

Claims (1)

(57) [Claims] 1. A π / 4 shift Q having a phase shifted by π / 4.
A baud rate extractor which receives a PSK signal, extracts a clock having the same cycle as the π / 4 shift QPSK signal, and outputs the clock as a baud rate clock;
A K signal and a measurement timing clock generated by fixedly delaying the baud rate clock are input, and the phase of the π / 4 shift QPSK signal is measured based on the measurement timing determined by the measurement timing clock. A baud rate extraction circuit comprising: a phase shift amount measurement circuit for outputting a phase difference of the π / 4 shifted QPSK signal between matched measurement timings as phase shift amount information; A variable delay circuit that variably delays the baud rate clock based on the predetermined delay control signal and outputs the baud rate clock as a variable measurement timing clock, and the phase shift amount information, and the phase shift amount measurement circuit Detects the difference between the variable measurement timing and the baud timing that occur when measuring the phase difference A timing error detection circuit that outputs the predetermined delay control signal based on the phase shift amount information, wherein the delay amount control circuit includes: And the variable delay circuit controls the variable measurement timing clock in the variable delay circuit, and the phase shift amount measurement circuit controls the π / 4 shift QP
An SK signal and the variable measurement timing clock are input, and the π / 4 shift QPSK is performed based on the variable measurement timing determined by the variable measurement timing clock.
A baud timing extraction circuit for measuring a phase of a signal and obtaining the phase shift amount information from a phase difference of the π / 4 shift QPSK signal between adjacent variable measurement timings.