JP2881804B2 - Camera signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Field of application in industry B Outline of the invention C Conventional technology (FIG. 5) D Problems to be solved by the invention (FIG. 5) E Means for solving the problems F Function G Example (1st embodiment) The present invention relates to a camera signal processing circuit, and is particularly suitable for being applied to a digital video camera.

B. Summary of the Invention The present invention relates to a camera signal processing circuit, which obtains video data corresponding to the type of imager, by adjusting the sampling frequency to the type of imager at the previous stage of the modulation circuit. As a result, a camera signal processing circuit having a simpler configuration can be realized.

C. Prior Art A conventional digital video camera uses a video signal generating circuit 1 as shown in FIG.

That is, for example, the image processing unit 3 samples and holds the image signal S1 obtained from the imager 2 having a CCD (charge coupled device) corresponding to each pixel in the sampling processing circuit unit 3 and performs the AGC process, thereby horizontalizing the image information of each pixel. And an analog / digital conversion circuit 4 as a time-series image processing signal S2 formed by vertical scanning.
Is converted to digital data.

The digital image processing signal S3 thus obtained in the analog / digital conversion circuit 4 is supplied to the camera signal processing circuit 5, and is supplied to a standard television system (for example, NTSC).
Sampling frequency (ie, 4
f _SC) luminance signal S _Y and the chroma signal S _C comprising modulated into sampled and predetermined transmission Fuomatto in is sent from the video signal generating circuit 1 as a video data DATA.

D Problem to be solved by the invention However, in the conventional digital video camera,
As the imager 2, first, a type corresponding to the type of the television standard system (for example, the NTSC system or the PAL system) is prepared, and second, the imager 2 having a different number of pixels in terms of resolution (for example, 760H, 510H, etc.), and it is necessary to prepare a camera signal processing circuit 5 suitable for each type of imager.

In particular, if the type of the television system and the type of the number of pixels are different, the clock frequencies for processing the digital image processing signal S3 are different from each other. In practice, the conventional configuration corresponds to the type of the imager 2. The camera signal processing circuit 5, which is a dedicated IC circuit, is prepared.

However, in this case, there is a problem that complicated work for manufacturing a plurality of types of camera signal processing circuits 5 and managing products according to the type of the imager 2 is required.

As a method of solving this problem, it is considered to prepare a camera signal processing circuit 5 that can be shared by preparing one type of IC in common for different types of imagers.

In this method, a sin-ROM and a multiplier are prepared in advance in a modulation circuit, and when data sampled at a sampling frequency determined based on a type of an imager in a pre-stage circuit is modulated into transmission data in the modulation circuit.
The sampling frequency of the transmission data is matched by changing the frequency at which the n-ROM is read.

However, since the circuit scale of a sin-ROM is actually large,
There is a problem that the configuration of the entire camera signal processing circuit 5 becomes large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a camera capable of matching an optimum sampling frequency of transmission data by using a common simple circuit configuration for each type of imager. It is intended to propose a signal processing circuit.

Means for Solving E Problem In order to solve such a problem, in the first invention,
In the camera signal processing circuit for transmitting a digital primary color signal S11 formed in accordance with the output of the image Ya 2 modulating the chroma signal S _C of the specified transmission method, image Layer 2 the sampling frequency is the use of the input data S13 A first sampling frequency conversion circuit 17 for converting at a conversion ratio determined by the standard television system adopted by the first embodiment and transmitting the converted data as output data S14. Signal S11
Image Layer 2 of the sampling frequency is used the sampling frequency 4f _SC corresponding to the standard television system adopted, so as to modulate the chroma signal S _C of the specified transmission method after transfer to 1135F _H of.

In the second invention, in the camera signal processing circuit for transmitting a digital primary color signal S11 formed in accordance with the output of the image Ya 2 modulating the chroma signal S _C of the specified transmission method, the sampling frequency of the input data S13 Is converted at a conversion ratio determined by the standard television system adopted by the imager 2 used, and the output data is converted.
First sampling frequency conversion circuit 1 to be transmitted as S14
7 and a second sampling frequency conversion circuit 15 for converting the sampling frequency of the input data S11 at a conversion ratio determined by the number of pixels of the imager 2 used and transmitting the converted data as output data S12. The digital primary color signal S11 is output by the second sampling frequency conversion circuits 17 and 15.
Image Layer 2 of the sampling frequency is used so as to modulate the chroma signal S _C of the specified transmission method after transfer to a sampling frequency corresponding to a standard television system adopted in.

F operation When the standard television system is different, or when a plurality of imagers having different standard television systems and different numbers of pixels are used, the sampling frequency of the input data is changed to the standard television system or the standard television system. By providing the first sampling frequency conversion circuit 17 or the first and second sampling frequency conversion circuits 17 and 15 for outputting as conversion designation output data at a conversion ratio determined by the number of pixels, predetermined transmission is achieved. for chroma signal S _C of the method for obtaining the modulation circuit, by which may avoid the need to frequency transfer to the transmission sampling frequency in the modulation circuit may further simplify the configuration of the modulation circuit.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 in which parts corresponding to FIG. 5 are denoted by the same reference numerals, is classified as an imager 2 from the category of the television standard system into the types of the NTSC system and the PAL system. The 760H type used for each type is used. Thus, there are four types of imagers, that is, 510H imagers in the NTSC system (this is referred to as the NTSC imager).
SC-510H), an imager of 510H in the PAL system (this is expressed as PAL-510H), an imager of 760H in the NTSC system (this is expressed as NTSC-760H), and an imager of 760H in the PAL system ( This is referred to as PAL-760H).
This shows an embodiment that can be applied to these four types of imagers in common.

In this case, the video signal generating circuit 1 is a digital image processing signal obtained from the analog / digital conversion circuit 4.
Camera signal processing circuit 5 of IC configuration receiving S3 at input terminal T1
The digital image signal S3 is received by a low-pass filter composed of 1H delay circuits 11 and 12 connected in cascade with each other, and a vertical correlation digital image processing signal S10 is supplied to a primary color signal circuit 14.

The primary color signal circuit 14 includes a white balance adjustment circuit, a gamma correction circuit, and a primary color separation circuit. As shown in FIG. 4A, the RGB data (... D ₀ , D ₂ , D ₄ , D ₆ …) and BG data (……)
D ₁ , D ₃ , D ₅ , D ₇ ...) Are interleaved with each other and sent to the first-stage sampling frequency conversion circuit 15.

The first-stage sampling frequency conversion circuit 15 converts the sampling frequencies of the RG data and BG data of the digital primary color signal S11 into values corresponding to the types of the number of pixels of the imager 2 (that is, 510H and 760H). The converted output signal S12 is supplied to a second-stage sampling frequency conversion circuit 17 via a gain control circuit 16 to convert the converted input signal S1.
Entered as 3.

The second stage sampling frequency conversion circuit 17 converts the data of the conversion input signal S13 into a frequency corresponding to the type of the television standard system of the imager 2 (that is, the NTSC system and the PAL system). S14, chroma signal output terminal optimum transmission sampling frequency is converted into a digital transmission data with (i.e. if 1135F _H when 4f _SC and the PAL system to the NTSC system) the rice and predetermined the format as chroma signal S _C in the modulation circuit 18 T2
Sent from.

In addition to this, the 1H delay digital image processing signal S15 obtained at the output end of the 1H delay circuit 11 is
9 and the luminance signal S from the luminance signal output terminal T3.
_Dispatched as _Y.

In the above configuration, the primary color signal circuit 14, the first stage sampling frequency conversion circuit 15,
The gain control circuit 16, the second-stage sampling frequency conversion circuit 17, and the modulation circuit 18 are provided in the frequency signal generation circuit 21 based on the television system designation signal NTSC / PAL and the pixel number designation signal 510H / 760H. Second and third
The clock signal frequency is selectively changed and controlled by the frequency signals S21, S22 and S23, thereby controlling to change the sampling frequency of the data signal.

The first frequency signal S21 is supplied to the primary color signal circuit 14 and the first stage sampling frequency conversion circuit 15 as a clock signal for data processing, so that the supplied vertical correlation digital image processing signal S10 is frequency-converted by the primary color signal circuit 14. After processing at the data processing speed of the signal S21, the signal is taken into the first stage sampling frequency conversion circuit 15.

The second frequency signal S22 is supplied to a first-stage sampling frequency conversion circuit 15, a hi-gain adjustment circuit 16, and a second-stage sampling frequency conversion circuit 17, where the first-stage sampling frequency conversion circuit 15 outputs a first-stage frequency conversion output signal S1.
After performing the frequency conversion process of changing the data transmission speed of the frequency signal 2 from the frequency of the frequency signal S21 to the frequency of the frequency signal S22, thereafter, the hi-gain adjustment circuit 16 uses the data processing speed determined by the frequency of the frequency signal S22. The gain control process is executed, and the output is
The second stage sampling frequency conversion circuit 17 takes in the stage frequency conversion input signal S13.

Further, the third frequency signal S23 is supplied to the second-stage sampling frequency conversion circuit 17 and the modulation circuit 18, whereby the sampling frequency of the second-stage frequency conversion output signal S14 sent out in the second-stage sampling frequency conversion circuit 17 is changed to the second frequency. From the frequency of the second frequency signal S22 to the third frequency signal S23
After that, the modulation circuit 18 performs the modulation process at the frequency of the third frequency signal S23.

Thus, the sampling frequency of the vertical correlation digital image processing signal S10 taken into the primary color signal circuit 14 is
First and second sampling frequency conversion circuits 15 as needed corresponding to the type of imager 2 currently used.
In steps 17 and 17, the frequency transfer process is executed in two stages.

In the case of this embodiment, the frequency signal generation circuit 21 determines the type of the imager 2 (ie, NT) as shown in FIG.
SC-510H, PAL-510H, NTSC-760H and PAL-760H) according to the first, second and third frequency signals S21, S22 and S23.
Is generated in response to the television system designation signal NTSC / PAL and the pixel number designation signal 510H / 760H.

That is, when the type of the imager 2 to be used is NTSC-510H, the frequency signal generation circuit 21 outputs the frequency 8f _SC / 3, 4f _SC and 4f
_{The SC} frequency signals S21, S22 and S23 are input to the input terminal T21, respectively.
1, input to the camera signal processing circuit 5 through T221 and T231.

At this time, the first stage sampling frequency conversion circuit 15 converts the sampling frequency from 8f _SC / 3 to 4f _SC to a frequency 1.5 times higher, and the second stage sampling frequency conversion circuit 17 converts this sampling frequency 4f _SC as it is. Instead, the converted output signal S14 having the same frequency is transmitted (effectively so-called through), thereby transmitting the converted output signal S14 having the optimum transmission sampling frequency 4f _SC in the NTSC system.

The use image frequency signal generating circuit 21 when type is PAL-510H of Layer 2, the frequency 1816f _H / 3,908f _H and 1135f
_H frequency signals S21, S22 and S23 are input to input terminal T21, respectively.
3, supply to T222 and T232.

As this time, the first-stage sampling frequency converting circuit 15 to frequency conversion so as to increase the sampling frequency of the digital primary color signal S11 obtained in the primary color signal circuit 14 from 1816f _H / 3 only 1.5 to 908 f _H, the second stage The sampling frequency conversion circuit 17 determines the sampling frequency 908f _H
Is converted to 1135f _H by a frequency 1.25 times higher, and thus PA
It sends the converted output signal S14 having the optimum transmission sampling frequency 1135F _H in L scheme.

Further, when the type of the used imager 2 is NTSC-760H, the frequency signal generation circuit 21 outputs the frequency 4f _SC , 4f _SC and 4f _SC
Is supplied to input terminals T212, T221 and T231.

At this time, the first stage sampling frequency conversion circuit 15 converts the sampling frequency 4f _SC of the digital primary color signal S11 obtained from the primary color signal circuit 14 into a frequency 4f without performing frequency conversion processing.
At the same time as outputting to the gain control circuit 16 as _SC ,
The second-stage sampling frequency conversion circuit 17 also has a second-stage frequency conversion input signal S1 obtained from the hue gain adjustment circuit 16.
A second stage frequency converted output signal S14 having the same sampling frequency 4f _SC as the third sampling frequency 4f _SC ,
Thus, the converted output signal S14 having the optimal transmission sampling frequency 4f _SC in the NTSC system is transmitted.

Further, when the type of the use imager 2 is PAL-760H,
Frequency signal generating circuit 21 is frequency 1816f _H / 3,1816f _H / 3 and
1135f _H frequency signals S21, S22 and S23 are applied to input terminals T213 and T213.
223 and T232.

At this time, the first-stage sampling frequency converting circuit 15 is the primary color signal circuit 14 of the digital primary color signal S11 of sampling frequency 1816f _H / 3 of the same sampling frequency regardless of the frequency converter first stage frequency converting an output signal S12 Hiyugein adjusting circuit 16 simultaneously with the delivery to the second stage sampling frequency converting circuit 17 and the second of the sampling frequency 1816f _H / 3
The sampling frequency of the stage frequency conversion input signal S13 is 1135f
Perform a frequency conversion operation to increase _H by 1.875 times, thereby obtaining the optimal sampling frequency 1135f in the PAL system.
_The conversion output signal S14 having _H is transmitted.

In the case of this embodiment, the first stage sampling frequency conversion circuit 15 is configured as shown in FIG.

That is, a digital primary color signal S11 (FIG. 4 (A)) composed of RG and BG data transmitted alternately sequentially is supplied to an RY and BY latch circuit 31 and 3 through an input terminal T31.
When the frequency signal S21 is supplied to the clock input terminal CK through the input terminal T32 while the enable signal is supplied to the enable terminal EN and the logic "L" level is supplied to the enable terminal EN, the latch operation is performed.

Here, the primary color signal circuit 14 (FIG. 1) is a first frequency signal.
Since the data processing is executed by S21, the frequency signal S21 applied to the clock input terminals of the RY and BY latch circuits 31 and 32 is synchronized with the digital primary color signal S11. Yields RY and BY
The latch circuits 31 and 32 are used for the RY and BY of the primary color signal S11.
Latch data reliably.

In addition, the frequency signal S21 is supplied to a 1/2 frequency divider circuit 33, and the frequency divided output S31 is directly input to an enable terminal of a BY latch circuit 32, and the RY latch circuit is connected via an inverter 34. The RY and BY latch circuits 31 and 32 are input to the enable terminal of the circuit 31 so that the primary color signal S11
By alternately performing a latch operation at a cycle corresponding to the two data cycles of (1) and (2), the BY and RY data (FIG. 4 (A)) sequentially and alternately arriving as the digital primary color signal S11 are changed to BY and R. -The latches are sequentially and alternately latched to the Y latch circuits 32 and 31. Thus, as shown in FIGS. 4 (B1) and 4 (B-2), the BY data is supplied from the BY and RY latch circuits 32 and 31, respectively. _{(...... D -1, D 1,} D 3, D 5 ......) and R-
Y Data 1/2 compared to _{(...... D -2, D 0,} D 2, D 4, D 6 ......) are separated, respectively the digital primary color signal S11 at the same time
Latch output data S32 and S transmitted at the data transmission speed of
33 is supplied to intermediate latch circuits 33 and 34.

The intermediate latch circuits 33 and 34 receive the output and the Q output of the latch control circuit 35 having the D flip-flop configuration at the enable input terminal EN, respectively, and the output and the Q output are logic "L".
When the clock signal is received at the clock input terminal CK when the frequency signal S22 applied to the input terminal T33 falls to the level, the latch operation is performed.

The latch control circuit 35 receives the frequency signal S22 and the frequency-divided output S31 at the clock input terminal CK and the data input terminal D, respectively, and sequentially and alternately latches the intermediate latch circuits 33 and 34 in synchronization with the frequency signal S22.

As a result, as shown in FIGS. 4 (C1) and (C2), the intermediate latch circuits 33 and 34 output BY and BY output as latch outputs S32 and S33 of the BY and RY latch circuits 32 and 31, respectively. The RY data is supplied to the switching input terminal P1 of the switch circuit 36 and
Send to P2.

The switch circuit 36 outputs latch outputs S34 and S34 supplied to the switch input terminals P1 and P2 at a period twice as long as the frequency signal S22 in response to a switch control signal S36 sent from the switch control circuit 37.
35 are alternately drawn to an output latch circuit 38.

The output latch circuit 38 receives the frequency signal S22 as a clock signal and repeats the cycle of the frequency signal S22, thereby obtaining latch outputs S34 and S35 as shown in FIG.
BY data (…… D ₋₁ , D ₁ , D ₃ , D ₅ ……)
, And RY data (... D _-2 , D ₀ , D ₂ , D _4, ...) Are sequentially and alternately arranged in time series to obtain a latch output. As the first-stage frequency conversion output signal S12.

According to the configuration of FIG. 3, the data of the digital primary color signal S11 having the sampling frequency corresponding to the frequency in synchronization with the frequency signal S21 is converted into the first data having the sampling frequency corresponding to the frequency by the frequency signal S22. The sampling frequency of the data output as the stage frequency conversion output signal S12 and transmitted by the first stage sampling frequency conversion circuit 15 can be changed.

Thus, if the frequency of the frequency signal S21 used for capturing data and the frequency of the frequency signal S22 used for outputting data are selected to be the same frequency, the first stage sampling frequency conversion circuit 15 The data taking-in speed and the data sending-out speed become equal to each other, whereby the same function as the first-stage sampling frequency converting circuit 15 can be realized.

The second-stage sampling frequency conversion circuit 17 uses the frequency signal S22 as the data acquisition signal, assuming that the input data is the first-stage frequency conversion input signal S13 and the output data is the second-stage frequency conversion output signal S14. In addition, it has exactly the same configuration as the first-stage sampling frequency conversion circuit 15, except that the frequency signal S23 is used to output data.

Therefore, the second stage sampling frequency conversion circuit 17 can obtain exactly the same effects as those obtained in the first stage sampling frequency conversion circuit 15.

According to the above configuration, in order to obtain the video data DATA including the chroma signal having the optimum transmission sampling frequency for the imager 2 having a plurality of types of specifications, the sampling frequency based on the difference in the number of pixels of the imager 2 is obtained. The sampling frequency can be changed so that the matching can be performed in the first-stage sampling frequency conversion circuit 15, and the sampling frequency matching based on the difference in the type of the standard television system is performed in the second-stage sampling frequency conversion circuit. With the circuit 17, it is possible to eliminate the necessity of matching the sampling frequency in the modulation circuit to obtain digital data of a predetermined transmission method in the modulation circuit 18, as in the conventional case. It is necessary to provide a ROM and a circuit for multiplying the output and the data signal Instead, modulated data can be obtained by a simple configuration such as an exclusive OR circuit.

The first and second sampling frequency conversion circuits 15
And 17 are passed through as needed, so that matching of a plurality of types of sampling frequencies can be realized by a simple configuration using a common configuration.

In the above embodiment, the imager 2 is classified as
As described with reference to NTSC-760H (FIG. 3) (ie,
First and second stage sampling frequency conversion circuits 15 and 17
Although the digital primary color signal S11 having a sampling frequency is formed and then changed to the transmission sampling frequency, the sampling frequency of the digital primary color signal S11 is not limited to this. The same effect as in the above case can be obtained by selecting an arbitrary value as needed.

H Advantageous Effects of the Invention As described above, according to the present invention, in order to obtain video data corresponding to a plurality of types of imagers, a television system adopted by the imagers in a stage preceding the modulation circuit,
Since data sampled at a sampling frequency matching the number of pixels can be obtained, a camera signal processing circuit with a simpler overall configuration can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a camera signal processing circuit according to the present invention, FIG. 2 is a table showing frequency signals used in the sampling frequency conversion circuit, and FIG. FIG. 4 is a connection diagram showing a detailed configuration of the second-stage sampling frequency conversion circuit, FIG. 4 is a data array diagram for explaining the operation thereof, and FIG. 5 is a block diagram for explaining a conventional camera signal processing circuit. 1. Video signal generating circuit, 2. Imager, 3.
Sampling processing circuit section, 4 ... Analog / digital conversion circuit, 5 ... Camera signal processing circuit, 14 ... Primary color signal circuit, 15 ... First stage sampling frequency conversion circuit, 16 ...
... Hue gain adjustment circuit, 17 ... Second stage sampling frequency conversion circuit, 18 ... Modulation circuit, 21 ... Frequency signal generation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H04N 9/04-9/09 H04N 9/64-9/65 H04N 11/06

Claims (2)

(57) [Claims] 1. A camera signal processing circuit for modulating a digital primary color signal formed based on an output of an imager into a chroma signal of a predetermined transmission system and transmitting the same, wherein the imager using a sampling frequency of input data is used. A first method of converting data at a conversion ratio determined by the standard television system adopted and transmitting the converted data as output data.
The sampling frequency of the digital primary color signal is changed by the first sampling frequency conversion circuit to a sampling frequency corresponding to a standard television system adopted by the imager used. A camera signal processing circuit for modulating the signal to a chroma signal of the predetermined transmission method. 2. A camera signal processing circuit for modulating a digital primary color signal formed based on an output of an imager into a chroma signal of a predetermined transmission system and transmitting the same, wherein the imager using a sampling frequency of input data is used. A first method of converting data at a conversion ratio determined by the standard television system adopted and transmitting the converted data as output data.
And a second sampling frequency conversion circuit for converting the sampling frequency of the input data at a conversion ratio determined by the number of pixels of the used imager and transmitting the converted data as output data. After changing the sampling frequency of the digital primary color signal to a sampling frequency corresponding to the standard television system adopted by the imager used by the first and second sampling frequency conversion circuits, the predetermined transmission system is used. A camera signal processing circuit that modulates a chroma signal.