JP2880493B2 - Charge pump circuit and logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit, and more particularly, to a charge pump circuit in a semiconductor integrated circuit for generating a power supply stepped up or down with respect to a power supply voltage supplied from the outside.

[0002]

2. Description of the Related Art A DRAM or a flash memory requires a step-up power supply or a step-down power supply structurally or for speeding up. It is important to efficiently generate the step-up / step-down power supply by the internal power supply circuit in order to increase the added value of the chip.

As a method of generating a step-up / step-down power supply on a chip, a charge pump circuit is generally used. In a charge pump circuit on an integrated circuit, a transistor is usually used as a rectifier.

Conventionally, a charge pump circuit as disclosed in, for example, Japanese Patent Application Laid-Open No. 6-14529 has been disclosed. Hereinafter, this conventional technique will be described with reference to the drawings.

FIG. 18 is a circuit diagram of a charge pump circuit (boost circuit) described in the above publication. FIG.
FIG. 5 is a diagram showing operation waveforms of the charge pump circuit of FIG. The charge pump circuit includes rectifying transistors Q1 and Q2,
It includes precharge transistors Q3 and Q4 and capacitors C1 and C2.

The signal φ1 having the first drive voltage and the second
The rectifier transistor Q1, the precharge transistor Q3, and the rectifier transistor Q2 and the precharge transistor Q4 operate in a complementary manner in response to the signal φ2 having the drive voltage, so that the power supply voltage Vdd becomes the output voltage V
pp.

When the voltage of signal φ1 rises, the potential of node N1 rises by capacitor C1. Node N1
Is connected to the gate of the transistor Q1. The charge generated at the node N1 is kept at 2 Vdd while the signal φ1 is at the H level (Vdd in this case), and the potential of the gate of the transistor Q1 is sufficiently increased. As a result, the charge at node N1 is transferred to output node Npp.

[0008]

However, for the precharge transistor Q3, for example, the charge generated at the node N2 is output to the output node Npp, so that the node N3
The potential of No. 2 decreases over time. In particular, when the power supply voltage Vdd is low, the precharge transistor Q3
Rise of the gate potential becomes insufficient. Therefore, precharge transistor Q3 cannot precharge node N1 to Vdd. Therefore, even if the capacitor C1 is driven next, the potential of the node N1 becomes 2 Vd
Does not rise to d. As a result, the charge pump circuit can output less electric charge than in an ideal state, causing a problem that the loss in voltage conversion increases.

Further, even if the charge pump circuit operates ideally, the potential amplitude of the gates of the transistors Q1 to Q4 is Vdd (the potential of the gates is Vdd to 2Vdd).
Range)). For this reason, under a low voltage condition in which the power supply voltage Vdd is lower than 1 V, the current difference between on and off of the transistors Q1 to Q4 becomes small. As a result, there arises a problem that charges stored in capacitors C1 and C2 cannot be transferred to output node Npp at high speed.

Further, with respect to the timing control circuit TMG for driving the charge pump circuit and the driver circuits IV1 and IV2, the charge pump circuit having a large load can be driven at high speed under the condition that the power supply voltage Vdd is lower than 1V. Can not. Therefore, there arises a problem that a sufficient current cannot be taken out from the charge pump circuit.

The present invention has been made to solve the above problems.

An object of the present invention is to provide a charge pump circuit having a small loss in voltage conversion.

Another object of the present invention is to provide a charge pump circuit which can supply a boosted / decreased voltage with high efficiency at high speed even when a low power supply voltage of 1 V or less is used.

[0014]

According to the present invention, there is provided a charge pump circuit comprising: a first switching element having a first control terminal; a second switching element having a second control terminal;
A charge pump circuit including a first pump including a node connected to the first and second switching elements, wherein the charge pump circuit includes the first and second switching elements.
Operate in a complementary manner in response to the first and second drive voltage signals, thereby converting an input voltage to an output voltage, outputting the output voltage via an output terminal,
The first control terminal and the second control terminal are connected to the node
And the output terminal . This achieves the object of the present invention.

[0015] The first switching element includes first and second rectifying transistors, and the first control terminal includes:
The first switching element includes first and second precharge transistors, the second switching element includes first and second precharge transistors, the second control terminal includes first and second precharge control terminals, Nodes are first and second
A first node connected to a first and a second capacitor, and in a first state, the first rectifying transistor outputs a charge stored in the first capacitor to the output of the first capacitor. And the second precharge transistor supplies the input voltage to the second capacitor, and in the second state, the second precharge transistor supplies the input voltage to the second capacitor.
The rectifying transistor supplies the charge stored in the second capacitor to the output terminal, the first precharge transistor supplies the input voltage to the first capacitor, and connects the first node to the second precharge transistor. The charge control terminal, and the second node and the first precharge control terminal may be electrically isolated.

The charge pump circuit further includes a second pump for driving the first and second control terminals, wherein the second pump includes first and second sub-transistors and first and second sub-capacitors And the first and second sub-transistors have first and second sub-transistors.
A first group of control terminals including a first rectification control terminal, a second precharge control terminal, and a second sub control terminal; A second control terminal group that receives a drive voltage signal and includes the second rectification control terminal, the first precharge control terminal, and the first sub-control terminal is connected to the second drive voltage signal via the second sub-capacitor. May be received.

The first control terminal group and the second control terminal group may receive a voltage having an amplitude that is larger than the amplitude of the input voltage.

The second pump further includes means for generating a first voltage sufficiently close to a predetermined voltage so as to ensure that the first and second switching elements are turned off, and the first control terminal. The group receives the second voltage higher than the input voltage in the first state, receives the first voltage in the second state, and receives the first voltage in the first state. In the second state, the second voltage may be received.

The second pump further includes means for generating a first voltage sufficiently close to a predetermined voltage so as to ensure that the first and second switching elements are turned off, and wherein the first control terminal is provided. The group receiving the second voltage lower than the ground potential in the first state, receiving the first voltage in the second state, the second control terminal group receiving the first voltage in the first state; In the second state, the second voltage may be received.

The first group of control terminals receives a first voltage higher than the input voltage in the first state, and receives a second voltage substantially equal to the input voltage in the second state. The terminal group is connected to the second group in the first state.
Receiving a first voltage in the second state.

The first group of control terminals receives a first voltage lower than a ground potential in the first state, and receives a second voltage substantially equal to the input voltage in the second state;
The second group of control terminals may receive the second voltage in the first state, and may receive the first voltage in the second state.

The first switching element includes a rectification transistor, the first control terminal includes a rectification control terminal, the second switching element includes a precharge transistor, and the second control terminal includes a precharge transistor. A control terminal, wherein the node is connected to a capacitor, and in a first state, the rectifying transistor supplies a charge stored in the capacitor to the output terminal;
In the second state, the precharge transistor
The input voltage may be supplied to the first capacitor, and the node and the precharge control terminal may be electrically isolated.

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a charge pump circuit according to the present invention will be described with reference to the drawings. In the specification and drawings, the same reference numeral indicates the same component.

(Embodiment 1) FIG. 1 is a circuit diagram of a charge pump circuit according to Embodiment 1 of the present invention. The charge pump circuit includes a main pump 1a and a sub pump 2a.

The main pump 1a includes a main capacitor C
1a and C2a, rectifying transistors Q1a and Q2
a, precharge transistors Q3a and Q4a. Sub-pump 2a has sub-capacitors SC1a and SC2a, and transistors SQ1a and SQ2a.

Main pump 1a and sub pump 2a
Have a 180 ° phase difference (ie, are out of phase)
It receives signals φ1 and φ2 which are square waves and is driven by these signals.

The sub-pump 2a outputs to the main pump 1a signals SN1a and SN2a having phases synchronized with the signal φ1 having the first driving voltage and the signal φ2 having the second driving voltage, respectively. A positive voltage Vdd which is a power supply voltage is applied to the node Ndd.

FIG. 2 is a diagram showing operation waveforms of the charge pump circuit of FIG. The operation of the charge pump circuit according to the first embodiment of the present invention will be described with reference to FIGS.

The signal φ1 rises and the first pump period T1
, The capacitor C1 driven by the signal φ1
The potential of the node N1a increases due to the capacitance of a. The node N2a is connected to the voltage Vdd by the transistor SQ1a.
Has been precharged. Therefore, when the signal φ1 rises and the sub-capacitor SC1a is driven, the signal SN2
The potential of a rises from Vdd to substantially 2Vdd.

The gate G4a of the precharge transistor Q4a is turned on during the first pump period T1, that is, during the period when the precharge transistor Q4a is on.
There is no connection to the node N1a as in the related art. For this reason, 2Vd which is the first voltage higher than the input voltage Vdd
The voltage of d is applied to the precharge transistor Q4a without dropping. As a result, the precharge of the node N2a can be sufficiently performed.

The potential of 2 Vdd is also applied to the gate G1a of the rectifier transistor Q1a throughout the first pump period T1. Therefore, the charge appearing at the node N1a is output to the output node Npp without loss.

The first pump period T1 ends when the voltage of the signal φ1 drops. When the voltage of signal φ1 drops, gates G of transistors Q1a and Q4a
A voltage Vdd, which is a second voltage substantially equal to the input voltage Vdd, is applied to 1a and G4a. For this reason,
Transistors Q1a and Q4a are turned off.

After the transistors Q1a and Q4a are completely turned off, a predetermined period MG (that is, an off / on margin) is applied and the voltage of the signal φ2 rises so that the backflow of charges does not occur. 2 pump period T
It becomes 2.

Even if the off / on margin is zero or less than zero (ie, transistors Q1a and Q4
Although the on-period of “a” and the on-periods of the transistors Q2a and Q3a overlap) and the boosting efficiency (the ratio of the output charge to the input charge) itself decreases, the boost operation itself is possible.

When the signal φ2 rises, the capacitor C2a
And SC2a are driven. Nodes N2a and SN
1a rises and transistors Q2a and Q3
a turns on. The charge appearing at the node N2a is supplied to the output node Npp through the rectifying transistor Q2a.

Node N1a is precharged to Vdd level through precharge transistor Q3a. The second pump period T2 also ends when the voltage of signal φ2 drops. After an off / on margin, the signal φ1 rises again to enter the first pump period T1.

In the charge pump circuit described above with reference to FIG. 18, gates G3 and G4 of precharge transistors Q3 and Q4 are connected to output node Npp via nodes N2 and N1. Therefore, the potentials of the nodes N2 and N1 drop from about 2 Vdd to Vpp with time. Therefore, when the power supply voltage Vdd is low,
Node N1 by precharge transistors Q3 and Q4
And the precharge of N2 becomes insufficient. As a result,
Cannot boost pressure with high efficiency.

On the other hand, in the first embodiment, the sub pump 2a is connected to the rectifier transistor Q1a of the main pump 1a.
, And gates G1a and G2a of Q2a and gates G3a and G4a of precharge transistors Q3a and Q4a.

According to the first embodiment, the transistor Q1
a, G2a, Q3a and gates G1a, G2 of Q4a
a, G3a and G4a can be isolated from the nodes N2a and N1a and the output node Npp. Therefore, the gates G1a, G2a, G3a and G4 of the transistors Q1a, Q2a, Q3a and Q4a
The potential of a does not substantially decrease with the passage of time. As a result, a highly efficient boosted power supply can be provided even in a low-voltage operation in which the power supply voltage Vdd is low.

The sub-pump 2a only needs to have a smaller driving force than the main pump 1a. For example, sub-capacitors SC1a and SC2a are connected to main capacitor C
It is sufficient that the capacitor has a capacity of about 1/10 of 1a and C2a.

The waveform shown in FIG. 2 is a waveform at the time when the output current of the charge pump circuit and the load current output from output node Npp are balanced. Unlike the equilibrium state, the potential of the output node Npp becomes lower than the equilibrium state when the circuit rises or when the load increases. Therefore, in such a case, nodes N1a and N1a
The waveform of 2a shifts to a lower potential.

FIG. 3 is a circuit diagram showing a modification of the charge pump circuit of FIG. The charge pump circuit of FIG.
It has a configuration of only one side of the charge pump circuit of FIG.

In the charge pump circuit of FIG. 1, the main pump 1a has two capacitors C1a and C2a, and the two capacitors C1a and C2a are driven complementarily.

On the other hand, in the charge pump circuit shown in FIG. 3, the main pump 1b is connected to one main capacitor C1.
b, and one main capacitor C1b is driven. The main pump 1b further includes one rectifying transistor Q1b and one precharge transistor Q1.
3b.

FIG. 4 is a diagram showing operation waveforms of the charge pump circuit of FIG. In the charge pump circuit of FIG.
As shown in FIG. 4, a precharge period PC is provided between two consecutive pump periods T1. Therefore, the potential fluctuation at the output node Npp is larger than that of the charge pump circuit of FIG.

FIG. 5 is a circuit diagram of a charge pump circuit according to the present invention for implementing a step-down operation. FIG. 6 is a diagram showing operation waveforms of the charge pump circuit of FIG.

The difference from the charge pump circuit described above with reference to FIG. 1 is that (1) rectifying transistors Q1c and Q2c,
In addition, a PMOS transistor is used instead of an NMOS transistor as the precharge transistors Q3c and Q4c, and (2) the supplied power supply voltage is Vss instead of Vdd.

Here, an example is shown in which Vss is substantially at the ground potential. The ground potential is usually ground. However, the voltage is not limited to the ground, and may be a predetermined voltage.

Transistors Q1C, Q4C, SQ2C
Receives a voltage -Vdd, which is a first potential lower than the ground potential Vss, when the signal φ1 falls, and receives a voltage Vss, which is a second voltage substantially equal to the input voltage Vss, when the signal φ1 rises.

As shown in FIG. 5, in the embodiment described below, if the polarities of the transistors (NMOS and PMOS) and the polarities of the supplied power supply voltages (Vdd and Vss) are changed, instead of the booster circuit, A step-down circuit is obtained.

(Embodiment 2) FIG. 7A is a circuit diagram of a charge pump circuit according to Embodiment 2 of the present invention. In the charge pump circuit according to the first embodiment described above with reference to FIG. 1, the voltage (Vdd to 2Vd) generated by the sub-pump
The amplitude of (range d) is Vdd. Therefore, the gates G1a and G1 of the rectifier transistors Q1a and Q2a
2a and precharge transistors Q3a and Q4a
The voltage amplitude at gates G3a and G4a is also Vd.
There is only d. Therefore, the supplied power supply voltage Vdd is 1
If the voltage is much smaller than V (for example, Vdd is 0.5 V), the charge cannot be transferred to the output node Npp at high speed.

In the second embodiment, as shown in FIG. 7A, the rectifying transistor Q is
In order to surely turn off the 1a and Q2a and the precharge transistors Q3a and Q4a, the first voltage Vss sufficiently close to the predetermined voltage to the second voltage 2Vdd higher than the input voltage are generated.

The rectifier transistors Q1d and Q2d, the precharge transistors Q3d and Q4d, and the sub-transistors SQ1d and SQ2d receive a voltage having an amplitude Vss to 2Vdd which is larger than the amplitude of the power supply voltage Vdd. The voltage Vss as the first voltage is supplied to the rectifier transistors Q1d and Q2d, the precharge transistors Q3d and Q3d.
The voltage is sufficiently close to a predetermined voltage so as to ensure that 4d and the sub-transistors SQ1d and SQ2d are turned off.

Here, an example is shown in which the voltage Vss as the first voltage is substantially the ground potential. The ground potential is usually ground. However, the voltage is not limited to the ground and may be a predetermined voltage.

As a result, the rectifier transistors Q1d, Q2
d, the voltage amplitude of the gate potential of the precharge transistors Q3d and Q4d and the sub-transistors SQ1d and SQ2d is expanded to 2Vdd.

The source potentials of the rectifier transistors Q1d and Q2d and the precharge transistors Q3d and Q4d are at least Vdd or higher. Therefore, when Vss is applied to the gate, the gates and sources of the transistors Q1d, Q2d, Q3d and Q4d, which are NMOS transistors, are reverse-biased. As a result, transistors Q1d, Q2d, Q3d and Q4d are completely turned off.

The transistor leakage current (subthreshold current) is expressed by the following equation.

I _leak = r (W / L) * 10- ^{(VT / S)} where, r: constant W: transistor gate width L: gate length S: slope factor (V in the sub-threshold region)
Vt: threshold value.

The value of the slope factor S is 70 to 100
mV (however, in the case of a PMOS transistor, the value becomes a negative value).
The leakage current increases by one digit or more.

The driving current Ids is represented by the following equation.

Ids = β (Vgs−Vt) The ^α drive current Ids is a so-called saturation current, and does not apply to the sub-threshold region.

Specifically, the leakage current of the transistor is
It is determined by the value of (Vgs-Vt) at the time of off. Sub pump 2
If the Vss potential can be generated at d, the off-state Vss
gs becomes -Vdd. Therefore, the transistor Q1
The threshold value Vt of d, Q2d, Q3d and Q4d can be set to a value lower by Vdd than in the case of FIG. 1 (Vgs = 0V at this time).

As described above, according to the second embodiment,
The threshold voltages of the rectifier transistors Q1d and Q2d and the precharge transistors Q3d and Q4d can be set significantly lower. When the transistor is on, (Vgs-Vt) becomes larger by Vdd than in the case of FIG. As a result, high-speed charge transfer becomes possible.

7A receives signals φ1 and φ2, and outputs subpump output signals SN1d and SN2d for controlling the gates of rectifier transistors Q1d and Q2d and precharge transistors Q3d and Q4d of main pump 1d. The sub-pump 2d includes precharge transistors SQ1d and SQ
2d, transistors SQ4d and SQ3 isolating nodes N1d and N4d, and N2d and N3d, respectively.
d and the voltages of the signals SN1d and SN2d to Vss
Transistors SQ5d and SQ6d that discharge the currents.

The structure of the main pump 1d is the same as that of the main pump 1a of the first embodiment described above with reference to FIG. 1, except that the transistors Q1d, Q2d, Q3d and Q4d have low thresholds.

FIG. 7B is a diagram showing operation waveforms of the charge pump circuit of FIG. 7A. When the signal φ1 rises after the signal φ2 falls, the voltage of the node N3d precharged to the voltage Vdd rises to 2Vdd. At this time, the gate potential of the transistor SQ3d is at Vdd. For this reason, the electric charge at the node N3d is
It is transmitted to the node N6d through 3d. As a result, the potential of the node N6d increases.

When the potential of the node N6d rises, the transistor SQ6d turns on, and the potential of the node N5d becomes V
ss. Since the potential of the node N5d becomes Vss,
The transistor SQ5d is turned off, and the potential of the node N6d substantially rises to 2Vdd.

There is a time difference between when the potential of the node N6d rises and when the transistor SQ5d turns off. Therefore, it is conceivable that the potential of the node N6d does not rise to 2Vdd.

However, if the threshold value of the transistor SQ5d is high to some extent, the node N6
The boost loss of d can be ignored. This is because the potential of the node N5d has dropped to near Vdd because the voltage of the signal φ2 has dropped, and a low-voltage operation such as Vdd = 0.5V is being performed.

Even when the voltage Vdd is higher than 0.5 V, the boosting loss of the node N6d is small if the driving ability of the transistor SQ5d is small with respect to the amount of charge appearing at the node N3d and the amount of charge lost through the transistor SQ5d is small. . The sub pump 2d is a main pump 1d
Of the transistors Q1d, Q2d, Q3d, and Q4d, the loss due to the time lag until the transistor SQ5d is turned off is large in the efficiency of the entire charge pump circuit of FIG. 7A. Has no effect.

When signal φ2 rises after signal φ1 falls, the potential of node N5d rises. Transistor S
Q5d is turned on, and the potential of node N6d is reduced to Vss. Since the potential of the node N4d rises to 2Vdd, the transistor SQ3d turns off. Nodes N6d and N3d are electrically isolated. The potential of the node N3d does not fall below the precharge potential Vdd.

As described above, according to the second embodiment, P
The voltage between the gate and source of MOS transistors Q3d and Q4d becomes ΔVdd in the on state and Vdd in the off state, so that the voltage amplitude of the gate potential expands to 2Vdd. Therefore, a low threshold transistor can be used. As a result, high-speed charge transfer becomes possible.

The PMOS transistors Q3d and Q3d
With respect to the source-drain voltage of 4d, the potential of the node N6d
The potential of 3d is higher, and the potential of the node N4d is higher than the potential of the node N5d. Therefore, if the well potentials of PMOS transistors Q3d and Q4d are equal to the potentials of N3d and N4d, respectively, latch-up does not occur.

As described above, Vss-
By generating a voltage of 2 Vdd, the power supply voltage V
It is possible to boost the voltage with high efficiency even under the condition that dd is low voltage.

FIGS. 8A to 8C are circuit diagrams showing variations of the sub-pump of the charge pump circuit according to the present invention. 8A to 8C, signals SN1d and SN2d are, for example, main pump 1 (not shown), respectively.
d is a sub-pump output signal that controls the gates of the rectifying transistors Q1d and Q2d and the gates of the precharge transistors Q3d and Q4d.

In FIG. 8A, transistors SQ1g and SQ2g are precharge transistors, and transistors SQ3g and SQ4g are transistors for holding the lower limit voltages of nodes N5d and N6d at Vdd, and transistors SQ5g and SQ6g
Is a transistor for discharging the signals SN1d and SN2d to Vss.

When the voltage of signal φ1 rises, node N3
g rises from the precharge voltage Vdd by Vdd, and 2
Vdd. At the same time, the voltage of signal φ2 drops, and node N4g attains precharge potential Vdd. Therefore, transistor SQ3g is turned on, and 2Vd is applied to node N5d.
d appears. The gate of the transistor SQ5g is connected to the node N5d.

The source of transistor SQ5g is connected to signal φ2. Therefore, the transistor SQ
The electric charge of the node N6d connected to the drain of 5g is V
It is discharged to ss, and the potential of the node N6d becomes Vss.

At this time, the transistor SQ in the off state
The potential Vss of the node N6d is applied to the gate of the transistor 6g, and the signal φ is applied to the source of the transistor SQ6g.
2 potential Vdd is applied. For this reason, the gate
A reverse bias is applied to the source-to-source voltage Vgs. As a result, it is possible to suppress the leakage current even if SQ5g and SQ6g are low threshold transistors. Therefore, the output signals SN1d and SN2d are quickly switched to Vss even under a low voltage condition where the power supply voltage Vdd is 1 V or less.
It is possible to discharge up to.

FIGS. 8B and 8C are circuit diagrams showing modifications of the sub-pump shown in FIG. 8A. In each case, the signal S
The transistors SQ5h and SQ6h or SQ5i and SQ6i for applying Vss to N1d and SN2d have a reverse bias Vd in the off state.
d is applied.

Therefore, these transistors SQ5
h, SQ6h, SQ5i, and SQ6i can be reduced in threshold value. Therefore, a high-speed boosting operation can be performed even when the power supply voltage Vdd is as low as 1 V or less.

In the structure of FIG. 8B, sub-capacitors SC1h and SC2h of sub-pump 2h are driven by signals φ1 and φ2 via a driver (here, an inverter). As for the potentials of the nodes N5d and N6d, the time of falling to Vss is earlier than the time of rising to 2Vdd.

Therefore, transistors SQ3h and S
After Q4h is turned off, the capacitors SC1h and S1
The off / on margin until C2h is driven is extended. Further, transistors SQ1h and SQ3h,
And SQ2h and SQ4h are not simultaneously turned on. As a result, there is no leakage from the output node Npp (not shown) to the power supply voltage Vdd. These are the same for the configuration of FIG. 8C.

Similarly, when the potentials of nodes N5d and N6d fall to Vss, nodes N3h and N3d
This is earlier than the time when the potential of 4h drops to Vdd. Therefore, the PMOS transistors SQ3h and SQ4h
Are connected to nodes N3h and N4h, respectively, so that the well potential does not become lower than the source and drain potentials. As a result, the latch-up resistance also increases.

FIG. 8D is a circuit diagram showing a variation of the sub-pump of the charge pump circuit according to the present invention.
FIG. 8E is a diagram showing operation waveforms of the sub-pump of FIG. 8D.

The above-described sub-pump uses a PMOS transistor to separate the precharge node from Vss. However, if a PMOS transistor is used in a configuration in which both the well potential and the source potential change, latch-up may occur. Therefore, a configuration that does not use a PMOS transistor is desirable.

In the sub-pump 2m shown in FIG. 8D, by precharging and discharging to Vss with a time difference, precharging of Vdd and discharging to Vss are performed only by NMOS transistors.

Referring to FIG. 8E, the operation of the sub-pump 2m will be described. Immediately before the signal φ1 falls, the node N6m
Are at the H level, the node N5m is at the L level, the transistor SQ8m is on, and the transistor SQ7m is off. Signal φ1
Falls (ie, when signal φ2 rises), Vdd is applied to node N5m through transistor SQ8m. In response, the transistor SQ7m is turned on, and the potential of the node N6m becomes Vss.

When the potential of the node N6m becomes Vss, the transistor SQ8m is turned off, so that the potential of the node N5m rises only to about the threshold value Vt. Thereafter, the signal SD2m delayed by the delay circuit 22m rises,
The node N5m rises to (Vt + Vdd). Even if the signal SD1m falls, Vss is applied to the node N6m.

According to this structure, Vss- (V
dd + Vt). For this reason, boosting can be performed without causing latch-up.

(Embodiment 3) According to Embodiment 2 described above, it is possible to operate the charge pump circuit itself efficiently even when the power supply voltage Vdd is low. However, it is difficult to operate a control circuit and a driver circuit for generating the signals φ1 and φ2 at a low voltage of about Vdd = 0.5 V at high speed. Therefore, a large current cannot be extracted from the charge pump circuit. This is because the output current of the charge pump circuit depends on the capacitance value of the pump capacitor and the driving frequency of the pump.

FIG. 9 is a circuit diagram of a third embodiment of the charge pump circuit according to the present invention. FIG. 10 is a diagram showing operation waveforms of the charge pump circuit of FIG. The charge pump circuit according to the third embodiment includes pump drivers 3e and 4e in addition to the configuration of the second embodiment in order to solve the above problem.

The pump driver 3e comprises a complementary transistor 31e having a gate and a drain connected to each other.
And 32e. The pump driver 4e has complementary transistors 41e and 42e each having a gate and a drain connected. Pump driver 3e
And 4e receive signals SN1d and SN2d, respectively, and drive main capacitors C1d and C2d.

According to the third embodiment, signals φ1 and φ2 need only drive sub-capacitors SC1d and SC2d, and main capacitors C1d and C2d
There is no need to drive. Therefore, as compared with the second embodiment, there is an effect that the load on the driver generating signals φ1 and φ2 is greatly reduced.

As described in the second embodiment, the output signals SN1d and SN2d of the sub-pump 2d oscillate substantially in the range of Vss to 2Vdd. On the other hand, the pump drivers 3e and 4e have delay times inevitable for semiconductor devices.

Therefore, capacitors C1d and C2
When signals SN1d and SN2d are input to pump drivers 3e and 4e, respectively, for driving d, times T101 and T103 at which the gate potentials of rectifier transistors Q1d and Q2d and precharge transistors Q3d and Q4d of main pump 1d are determined, and node N1
Times T102 and T10 at which the potentials of d and N2d change
4, the timing margins MG101 and MG102 from turning off the transistors Q3d and Q4d to driving the capacitors C1d and C2d are automatically secured.

As a result, a charge pump circuit that performs boosting with a smaller loss than in the second embodiment can be realized without complicated control.

Further, since signals SN1d and SN2d oscillate substantially in the range of Vss to 2Vdd, as shown in FIG. 9, NMOS transistors Q1d, Q2d,
The effect is obtained that the threshold values of Q3d and Q4d may be low. This is because, even when the threshold value of the NMOS transistor is low, the gate potential becomes higher than the source potential by Vdd and a reverse bias is applied, so that a leak current can be suppressed.

Although the configuration including the main pump 1d, the pump drivers 3e and 4e, and the sub-pump 2d has been described as an example, the present invention is not limited to this configuration. The same effect can be obtained with a configuration including only 1d and the pump drivers 3e and 4e.

As described above, according to the third embodiment, the speed of the pump driver for driving the main pump 1d or the area thereof can be reduced. Therefore, the speed of the entire charge pump circuit can be increased. Further, a charge pump circuit having a small area can be realized in addition to the low voltage operation.

(Embodiment 4) FIG. 11 is a circuit diagram of a charge pump circuit according to Embodiment 4 of the present invention. FIG. 12 is a diagram showing operation waveforms of each part of the charge pump circuit of FIG. In the first to third embodiments, the sub-pump boosts the gate potential of the rectifier transistor and the precharge transistor of the main pump.

However, in order to boost the output of the sub-pump to around 2 Vdd, it is necessary to set the capacitance of the sub-capacitor of the sub-pump sufficiently larger than the values of the rectifying transistor and other parasitic capacitances. Since the load connected to the output of the charge pump circuit is heavy, when the current required to drive the main pump increases, the size of the sub-pump also increases. As a result, the power supply voltage Vdd
Under a low-voltage condition where is less than or equal to 1 V, the sub-pump may not operate at high speed.

In the fourth embodiment, in order to solve this problem, the first stage sub-pump drives the second stage sub-pump. Therefore, even if the driving capacity of the first-stage sub-pump is insufficient to drive the main pump, it is sufficient that the first-stage sub-pump can drive the second-stage sub-pump.

In this case, since the signals SN1d and SN2d output from the first-stage sub-pump 2d can generate voltages in the range of Vss to 2Vdd, as shown in FIG.
The second-stage sub-pump can be overdriven. Therefore, the sub-capacitor of the second-stage sub-pump can be set to be larger than that of the first-stage sub-pump.

As described above, according to the fourth embodiment, by connecting the sub-pumps in multiple stages, it is possible to boost the signals SN1d and SN2d to substantially 2 Vdd even when the load on the main pump is heavy. Therefore, even if the power supply voltage Vdd is a low voltage of 1 V or less, high-efficiency boosting can be performed.

The number of stages for connecting the sub-pumps is not limited to two, but may be three or more. The sub-pump at the last stage can drive the main pump without stress, and the signals φ1 and φ
As long as 2 can drive the first-stage sub-pump without stress, the number of connected sub-pumps is arbitrary.

The phase of the signal for driving the main pump by the sub-pump in the last stage with respect to the phase of signals φ1 and φ2 is shifted by an amount corresponding to the number of stages of the connected sub-pumps. Is the same as the frequency of the signals φ1 and φ2.

(Fifth Embodiment) FIG. 13 is a circuit diagram of a charge pump circuit according to a fifth embodiment of the present invention. FIG. 14 is a diagram showing operation waveforms of the charge pump circuit of FIG. The sub-pump according to the above-described second embodiment includes:
Vss to 2Vdd are generated. This is because the gate voltage can be sufficiently achieved by the amplitude of Vss to 2Vdd.

However, the power supply voltage Vdd is further lowered, and 2 Vdd (Vss to 2) is used to control the rectifying transistor and the precharge transistor of the main pump.
Vdd) or more may be required. Further, the larger the on / off potential difference applied to the gate of the transistor, the higher the driving capability of the transistor. Therefore, the output from the sub pump is
The larger the potential amplitude of the signal for controlling the main pump, the better.

As shown in FIG. 13, nodes N3j are connected to node N2j and node N4j is connected to node N1j as a pre-charge power supply for the sub-pump. Nodes N3j and N4j are precharged to voltage Vpp or higher. Therefore, the outputs SN1j, SN of the sub-pump
The potential amplitude of 2j can be expanded to the range of Vss to (Vdd + Vpp).

As described above, according to the fifth embodiment, the potential amplitudes of the gate potentials of the rectifier transistors Q1j and Q2j and the precharge transistors Q3j and Q4j of the main pump are smaller than those of the second to fourth embodiments. Further, it can be enlarged by (Vpp-Vdd). For this reason, it is possible to further improve the speed of transferring charges from the nodes N1j and N2j of the main pump to the output node Npp.

FIG. 15 is a circuit diagram of a modification of the fifth embodiment of the charge pump circuit according to the present invention. FIG.
FIG. 16 is a diagram showing operation waveforms of the charge pump circuit of FIG.

As shown in FIGS. 15 and 16, feedback capacitors BC1k and BC2k are connected between nodes N1k and N2d and between nodes N2k and N1d.
Are provided respectively. Node N1d or N2d
Rises to 2Vdd, the capacitor C1k or C2k of the main pump 1k is switched to the pump driver 3e or 4e.
Driven with a delay. At this timing, the feedback capacitors BC1k and BC2k are also driven.

For this reason, the feedback capacitor BC
Due to the capacitive coupling of 1k and BC2k, the potentials of nodes N1d and N2d further rise from 2Vdd. As a result, the potential amplitudes of the gate potentials of the rectifier transistors Q1k and Q2k of the main pump 1k and the precharge transistors Q3k and Q4k can be made larger than 2 Vdd.

(Embodiment 6) With the background of low power consumption of semiconductor circuits and miniaturization of process technology, semiconductor circuits tend to have low power supply voltage.

However, in a semiconductor circuit, there may be a portion where the logic is locally complicated and a signal is not transmitted within a predetermined time. In such a portion, the power supply voltage is locally increased and the signal is supplied to a predetermined portion. It needs to be transmitted in time. For this reason, there is a demand for a dual power supply system for the semiconductor circuit.

In the present invention, focusing on the power consumption of each part of the semiconductor circuit and the conversion loss at the time of voltage conversion for the dual power supply system, the voltage before the voltage conversion is supplied to the part where the power consumption is large, Is supplied to a portion having low power consumption.

Referring to FIG. 17A, the semiconductor circuit comprises the first
It includes a circuit X1, a second circuit X2, and a voltage conversion circuit X3. The power consumption of the first circuit X1 is larger than the power consumption of the second circuit X2. Voltage conversion circuit X3 converts power supply voltage Vdd to voltage Vpp. Voltage Vpp is a voltage higher than power supply voltage Vdd or a voltage lower than ground voltage Vss. At the time of voltage conversion in the voltage conversion circuit X3, conversion loss occurs. The voltage Vpp including the conversion loss has the first power consumption.
Supplied to a second circuit X2 that is smaller than the power consumption of the circuit,
The power supply voltage Vdd before conversion is supplied to the first circuit X1 whose power consumption is larger than that of the second circuit X2.

Since the power consumption of the second circuit X2 to which the voltage Vpp including the conversion loss is supplied is smaller than the power consumption of the first circuit X1, the conversion loss does not increase. Therefore, power loss due to conversion loss in the entire semiconductor circuit is reduced. As a result, power consumption is reduced.

The voltage conversion circuit X3 may be formed on a chip on which the first circuit X1 and the second circuit X2 are formed. Alternatively, it may be formed outside the chip on which the first circuit X1 and the second circuit X2 are formed.

The voltage conversion circuit X3 has a power supply voltage Vd
Any voltage conversion circuit can be used as long as it has a function of converting d to the voltage Vpp. For example, the voltage conversion circuit X3
It may be a conventional charge pump circuit, DC / DC converter, or the like.

Furthermore, the charge pump circuit of the present invention described in the first to fifth embodiments can be used as the voltage conversion circuit X3. In this case, the power supply voltage V
The advantage that the conversion loss from dd to the voltage Vpp is small and the advantage that the voltage conversion circuit operates even when the power supply voltage Vdd is a low voltage of 1 V or less are obtained.

The switching probability of the first circuit X1 may be greater than the switching probability of the second circuit X2. The load driven by the first circuit X1 is the second circuit X1.
It may be larger than the load driven by the circuit X2.

Hereinafter, the case where the load driven by the first circuit X1 is larger than the load driven by the second circuit X2 will be described as an example. Note that the present invention can be similarly applied to a case where the switching probability of the first circuit X1 is greater than the switching probability of the second circuit X2.

FIG. 17B is a diagram showing Embodiment 6 of the logic circuit of the present invention having a boosted power supply.

The logic circuit includes a logic circuit section S1, a driver section S2, a charge pump circuit S3, and a capacitor CL.
Logic circuit section S1 includes PMOS transistors Q1 and Q2. The driver section S2 includes a PMOS transistor Q3,
Includes NMOS transistor Q4.

The driver section S2 drives the capacitor CL which is a load larger than the load of the logic circuit section S1. The power consumption of the driver unit S2 is larger than the power consumption of the logic circuit unit S1. Therefore, the power supply voltage Vdd before voltage conversion is supplied to the driver unit S2.

The logic circuit S1 is a part that requires high-speed operation. The logic circuit unit S1 includes a boosted voltage Vp after voltage conversion.
p is supplied. The load of the logic circuit S1 is the driver unit S2
, The conversion loss is not increased even when the boosted voltage Vpp including the conversion loss due to the voltage conversion is supplied. Therefore, the power loss due to the conversion loss in the entire logic circuit is reduced.

As described above, by supplying the power supply voltage Vdd to the driver section S2 and supplying the boosted voltage Vpp to the logic circuit section S1, it is possible to reduce the power consumption of the entire logic circuit.

The logic circuit section S1 operates at high speed by receiving the boosted voltage Vpp. The driver unit S2 is
The operation is performed at high speed by using the PMOS transistor Q3 having a low threshold value. This is because, as described in Embodiment Mode 2, using a low-threshold transistor is effective for operating a semiconductor circuit at high speed. Thus, the logic circuit realizes high-speed operation of the whole logic circuit.

However, if the threshold value of the transistor is too low, the leakage current increases, and eventually the operating current increases. As a result, even though the voltage before the voltage conversion is used to reduce the power consumption of the semiconductor circuit, the power consumption may increase.

In the logic circuit according to the sixth embodiment, as described below, leakage current can be suppressed even when a PMOS transistor having a low threshold value is used.

The logic circuit section S1 outputs one of the boosted voltage Vpp and the ground potential Vss to the driver section S2. Boosted voltage Vpp or ground potential Vss is applied to PMOS transistors Q3 and N provided in driver section S2.
It is applied to the gate of MOS transistor Q4.

When the boosted voltage Vpp is output to the driver section S2, the PMOS transistor Q3 provided in the driver section S2 is turned off and the NMOS transistor Q4 is turned on. As a result, the driver unit S2 outputs the ground potential Vs
s is output.

When the ground potential Vss is output to the driver S2, the PMOS transistor Q3 provided in the driver S2 is turned on, and the NMOS transistor Q4 is turned off. As a result, the power supply voltage Vd
d is output.

The source of the PMOS transistor Q3 is supplied with the power supply voltage Vdd. When the boosted voltage Vpp is applied to the gate of the PMOS transistor Q3, PM
The OS transistor Q3 turns off. Therefore, PM
When the OS transistor Q3 is off, a reverse bias is applied to the PMOS transistor Q3.

Therefore, the power supply voltage Vdd is supplied to the source of the PMOS transistor Q3, and the PMOS transistor Q3 is turned off when the power supply voltage Vdd is applied to the gate of the PMOS transistor Q3. The threshold value of the transistor Q3 can be reduced.

As described above, according to the present invention, the leakage current is suppressed by turning the low threshold transistor into the reverse bias state when the transistor is off.

For example, consider the case where the power supply voltage Vdd = 0.5 V is supplied to the source of the PMOS transistor Q3, the boosted voltage Vpp = 0.75V is applied to the gate, and the PMOS transistor Q3 is turned off. Gate-source voltage Vgs when Q3 is off
Is 0.25V.

In general, for a PMOS transistor,
It is said that if the value of (Vgs-Vt) is 0.1 V or more, the leak current will never become an unacceptable value (Semicon Kansai 96 ULSI Technical Seminar Lecture Preliminary Collection 1)
−48 to 1-49, ISSCC96 / SESSION 10 / LOW-POWER & C
OMMUNICATION SIGNAL PROCESSING / PAPER FA 10.3).

The operation current is the sum of the charge / discharge current and the leak current. If the value of (Vgs-Vt) is 0.1 V or more, the ratio of the leakage current included in the operation current is small, and the leakage current does not greatly increase the operation current.

Therefore, as the value of the threshold value Vt of the PMOS transistor Q3, an extremely low threshold value of +0.15 V can be set.

Here, in the case of an NMOS transistor, a change in the threshold value from + to-means that the threshold value is lowered.
Unlike the case of the MOS transistor, the threshold value is changed from-to +
The change in the direction of is referred to as a lower threshold.

As in the conventional case, the PMOS transistor Q3
Is supplied with the power supply voltage Vdd = 0.5V to the source, the power supply voltage Vdd = 0.5V is applied to the gate, and the PMOS transistor Q3 is turned off, the gate-source voltage when the PMOS transistor Q3 is turned off Vgs is 0
V. When Vgs is 0 V, (Vgs-Vt)
Is required to be -0.1 V as the value of the threshold value Vt of the PMOS transistor.

As described above, conventionally, the PMOS transistor Q
The threshold Vt of 3 could only be reduced to -0.1V.
In the present embodiment, the threshold value Vt can be reduced to + 0.15V. That is, +0.15 V is the lowest threshold value Vt.

However, the threshold value Vt is not necessarily +0.15 V
There is no need to lower it. The threshold value Vt only needs to be a value lower than -0.1 V, and can take any value within a range from -0.1 V to +0.15 V. The threshold value Vt is -0.1
This is because if it is in the range from V to +0.15 V, it is lower than the conventional threshold value.

According to the sixth embodiment, it is possible to lower the threshold value by 0.25 V (the threshold value in the positive direction is lower in the case of PMOS) while maintaining the leak level, as compared with the related art.
As described above, since the PMOS transistor Q3 has a low threshold, the ground potential Vs is applied to the gate of the PMOS transistor Q3.
When s is input, the PMOS transistor Q3 operates at high speed from the off state to the on state.

Further, regarding the NMOS transistor Q4, since the gate voltage at the time of off is Vss and the source voltage is Vss, the gate-source voltage at the time of off is 0.
V. Generally, for NMOS transistors,
It is said that if the value of (Vgs-Vt) is -0.1 V or less, the leakage current does not significantly increase the operating current.

Therefore, although the threshold voltage cannot be lowered to 0.1 V or less, the gate voltage at the time of ON is 0.75 V,
The source voltage is the ground potential Vss (0 V),
Since the source-to-source voltage Vgs is 0.75 V, (Vgs-Vt) equal to or higher than the power supply voltage Vdd (0.5 V) is applied without forcibly lowering the threshold voltage. Thus, NM
The OS transistor Q4 operates at a high speed from an off state to an on state because the gate-source voltage Vgs at the time of on is large.

As described above, in the driver section S2, the PMO
ON / OFF of the S transistor Q3 and the NMOS transistor Q4 is switched at high speed. As a result, the driver section S2 operates at high speed.

The PMOS transistor Q of the logic circuit section S1
1, the threshold values of Q2 are set higher than the threshold value of the PMOS transistor Q3 of the driver section S2. Logic circuit section S1
Of the PMOS transistors Q1 and Q2 are small,
Since the off-states of the PMOS transistors Q1 and Q2 become insufficient and the leakage current increases, the intended effect of realizing high-speed operation and low power consumption by supplying the boosted voltage Vpp from the charge pump circuit S3 is achieved. Because you cannot get it.

It is to be noted that some of the PMOS transistors other than the PMOS transistors Q1 and Q2 of the logic circuit portion S1 include:
A low threshold transistor similar to the PMOS transistor Q3 may be used. This is because if the number of low threshold transistors is small, the increase in leakage current may be within an allowable range.

As described above, the PMOS transistor Q3 provided in the driver section S2 for driving a heavy load is
The transistors are set to a low threshold, and transistors other than the PMOS transistor Q3 are set to a standard threshold. Logic circuit section S
The gate delay of 1 is suppressed by applying the boosted power supply Vpp output from the charge pump circuit S3.

The power supply voltage Vdd is converted to a voltage Vpp higher than the power supply voltage Vdd, and the voltage Vpp is converted to the logic circuit section S.
1 has been described as the power supply voltage, the ground voltage Vss is set to a voltage Vs lower than the ground voltage Vss.
The same effect can be obtained even when the voltage is converted to s 'and the voltage Vss' is used as the ground voltage of the logic circuit unit S1. In this case, the NMOS transistor Q4 of the driver circuit S2 may be set to a low threshold.

It is also possible to convert power supply voltage Vdd to voltage Vpp higher than power supply voltage Vdd, convert ground voltage Vss to voltage Vss 'lower than ground voltage Vss, and use voltage Vpp and voltage Vss' together. It is. In this case, the PMOS transistor Q3 of the driver circuit S2,
Both of the NMOS transistors Q4 can have a low threshold.

[0164]

As described above, according to the present invention, it is possible to provide a charge pump circuit having a small loss in voltage conversion.

Further, it is possible to provide a charge pump circuit which can supply a boosted / decreased voltage with high efficiency at high speed even when a low power supply voltage of 1 V or less is used.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a charge pump circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms of the charge pump circuit of FIG.

FIG. 3 is a circuit diagram showing a modification of the charge pump circuit of FIG. 1;

4 is a diagram showing operation waveforms of the charge pump circuit of FIG.

FIG. 5 is a circuit diagram of a charge pump circuit according to the present invention for implementing a step-down operation.

6 is a diagram showing operation waveforms of the charge pump circuit of FIG.

FIG. 7A is a circuit diagram of a charge pump circuit according to a second embodiment of the present invention.

FIG. 7B is a diagram showing operation waveforms of the charge pump circuit of FIG. 7A.

FIG. 8A is a circuit diagram showing a variation of the sub-pump of the charge pump circuit according to the present invention.

FIG. 8B is a circuit diagram showing a variation of the sub-pump of the charge pump circuit according to the present invention.

FIG. 8C is a circuit diagram showing a variation of the sub-pump of the charge pump circuit according to the present invention.

FIG. 8D is a circuit diagram showing a variation of the sub-pump of the charge pump circuit according to the present invention.

FIG. 8E is a diagram showing operation waveforms of the sub-pump of FIG. 8D.

FIG. 9 is a circuit diagram of a charge pump circuit according to a third embodiment of the present invention.

FIG. 10 is a diagram showing operation waveforms of the charge pump circuit of FIG.

FIG. 11 is a circuit diagram of a charge pump circuit according to a fourth embodiment of the present invention.

12 is a diagram showing operation waveforms of the charge pump circuit of FIG.

FIG. 13 is a circuit diagram of a charge pump circuit according to a fifth embodiment of the present invention.

14 is a diagram showing operation waveforms of the charge pump circuit of FIG.

FIG. 15 is a circuit diagram of a modification of the fifth embodiment of the charge pump circuit according to the present invention.

16 is a diagram showing operation waveforms of the charge pump circuit of FIG.

FIG. 17A is a diagram showing the principle of Embodiment 6 of the logic circuit of the present invention.

FIG. 17B is a diagram showing Embodiment 6 of the logic circuit of the present invention including a boost power supply.

FIG. 18 is a circuit diagram of a conventional pump circuit.

19 is a diagram showing operation waveforms of the pump circuit of FIG.

[Explanation of symbols]

1a Main pump 2a Sub pump C1a, C2a, SC1a, SC2a Capacitor Q1a, Q2a, Q3a, Q4a, SQ1a, SQ2a
Transistor

Claims (9)

(57) [Claims] 1. A first pump comprising a first switching element having a first control terminal, a second switching element having a second control terminal, and a node connected to the first and second switching elements. A charge pump circuit, wherein the charge pump circuit converts an input voltage to an output voltage by causing the first and second switching elements to operate complementarily in response to first and second drive voltage signals. And outputting the output voltage via an output terminal, wherein the first control terminal and the second control terminal
And a charge pump circuit electrically isolated from both the output terminal and the output terminal . 2. The first switching element includes first and second rectification transistors, the first control terminal includes first and second rectification control terminals, and the second switching element includes a second rectification control terminal. A first and a second precharge transistor; the second control terminal includes a first and a second precharge control terminal; the node includes a first and a second node; Respectively the first and second
In a first state, the first rectifying transistor supplies the charge stored in the first capacitor to the output terminal, and the second precharge transistor supplies the input voltage to the input terminal. In the second state, the second rectifying transistor supplies the charge stored in the second capacitor to the output terminal, and the first precharge transistor supplies the input voltage to the first capacitor. The charge according to claim 1, wherein the charge is supplied to a capacitor, and the first node and the second precharge control terminal, and the second node and the first precharge control terminal are electrically isolated. Pump circuit. 3. The charge pump circuit further includes a second pump for driving the first and second control terminals, wherein the second pump includes first and second sub-transistors and first and second sub-transistors. A sub-capacitor, the first and second sub-transistors have first and second sub-control terminals, the first rectification control terminal, the second precharge control terminal, and the second A first control terminal group including two sub-control terminals is:
Receiving the first drive voltage signal via the first sub-capacitor, a second control terminal group including the second rectification control terminal, the first precharge control terminal, and the first sub-control terminal,
The charge pump circuit according to claim 2, wherein the second drive voltage signal is received through the second sub-capacitor. 4. The charge pump circuit according to claim 3, wherein said first control terminal group and said second control terminal group receive a voltage having an amplitude that is larger than an amplitude of said input voltage. 5. The second pump further comprises means for generating a first voltage sufficiently close to a predetermined voltage so as to ensure that the first and second switching elements are turned off. The control terminal group receives the second voltage higher than the input voltage in the first state, receives the first voltage in the second state, and the second control terminal group receives the first voltage in the first state. The charge pump circuit according to claim 3, wherein the charge pump circuit receives the second voltage in the second state. 6. The second pump further includes means for generating a first voltage sufficiently close to a predetermined voltage so as to ensure that the first and second switching elements are turned off. The control terminal group receives the second voltage lower than the ground potential in the first state, receives the first voltage in the second state, and the second control terminal group receives the first voltage in the first state. 4. The charge pump circuit according to claim 3, wherein the charge pump circuit receives the second voltage in the second state. 7. The first control terminal group receives a first voltage higher than the input voltage in the first state, and
The second control terminal group receives the second voltage in the first state, and receives the first voltage in the second state, wherein the second control terminal group receives the second voltage substantially equal to the input voltage in the state. 4. The charge pump circuit according to 3. 8. The first group of control terminals receives a first voltage lower than a ground potential in the first state, receives a second voltage substantially equal to the input voltage in the second state, and The charge pump circuit according to claim 3, wherein the control terminal group receives the second voltage in the first state, and receives the first voltage in the second state. 9. The first switching element includes a rectification transistor, the first control terminal includes a rectification control terminal, the second switching element includes a precharge transistor, and the second control terminal includes: A precharge control terminal, wherein the node is connected to a capacitor; in a first state, the rectifying transistor supplies a charge stored in the capacitor to the output terminal; The transistor is
The charge pump circuit according to claim 1, wherein the input voltage is supplied to the capacitor, and the node and the precharge control terminal are electrically isolated.