JP2878780B2 - Electronic interlocking device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic interlocking device used for controlling a signal switch in a railway station.

[Conventional technology]

FIG. 7 is a block diagram showing a configuration of a conventional electronic interlocking device. In this figure, a control input signal from an input circuit 1 passes through a data collating circuit 2 to two operation processing circuits 3,
Sent to 4.

The arithmetic processing circuits 3 and 4 perform the same arithmetic processing, and the arithmetic data signal is sent to the data matching circuit 2. The data collation circuit 2 collates these operation data signals, outputs a collation output signal (1-bit DC data output signal) 5 if they match, and does not output the collation output signal 5 if they do not match. .

When the collation output signal 5 is output, the amplification circuit 6 amplifies the signal and excites the relay 7. Thereby, the a contact 8 of the relay 7 is turned on, and the output of the control output signal of the output circuit 9 is permitted.

As described above, after the operation results of the two operation processing circuits 3 and 4 are collated, the output of the output circuit 9 is permitted because the electronic interlocking device has the property of a signal security device. This is because higher security is required.

[Problems to be solved by the invention]

By the way, since the electronic interlocking device has the character as a signal security device, a so-called fail-safe function that causes a failure on the safe side is required even if a failure occurs.

However, in the above configuration, even if the operation data signals of the operation processing circuits 3 and 4 do not coincide with each other, if the collation of the data collation circuit 2 is incorrect, the collation output signal 5 is erroneously output. As a result, a fail-out failure occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made in consideration of an operation data signal from a plurality of arithmetic processing circuits so that a data collation circuit does not make an erroneous collation, and an electronic device that has improved fail-safe certainty. It is intended to provide an interlocking device.

[Means for solving the problem]

According to the present invention, as a means for solving the above-mentioned problem, the first and second arithmetic processing circuits perform the same arithmetic processing on a control input signal from an input circuit, and then perform the first and second arithmetic processing.
The operation data signals are compared by a data comparison circuit, and the data comparison circuit outputs a comparison output signal only when these operation data signals match each other, and permits the output circuit to output a control output signal. In the electronic interlocking device described above, the data collating circuit includes an arithmetic data inverting unit that inverts a first arithmetic data signal from the first arithmetic processing circuit during a predetermined inversion period; All of the first operation data signal and the second operation data signal are input, and the first and second operation data signals do not coincide with each other during the inversion period, and during the non-inversion period, And a data coincidence determining means for outputting the collation output signal only when they coincide with each other.

(Operation)

In the above configuration, the first operation data signal from the first operation processing circuit during the inversion period is inverted by the operation data inversion means. Therefore, if the first operation data signal and the second operation data signal are actually coincident with each other, the data coincidence determination means must make sure that these signals do not coincide during the inversion period. During the non-inversion period, it should be determined that they match. Therefore, if the data coincidence discriminating means performs another discrimination during the inversion period and during the non-inversion period, the first and second operation data signals are likely to be inconsistent with each other. Does not output a collation output signal.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 6. FIG. 1 is a block diagram showing a main part of the present embodiment, and the illustration of the input circuit 1, the output circuit 9 and the like in FIG. 7 is omitted.

The data collating circuit 2A is configured to include an operation data inverting unit 10 and a data coincidence determining unit 11. And
The first operation data signal from the first operation processing circuit 3 is:
During the inversion period, the data is output to the data coincidence determination means 11 in a state inverted by the arithmetic data inversion means 10. On the other hand, the second operation data signal from the second operation processing circuit 4 is directly output to the data coincidence determination means 11 as it is.

Now, the control input signal from the input circuit 1 is applied to the arithmetic processing circuit.
It is assumed that the first and second operation data signals are sent to 3 and 4 and processed, and the first and second operation data signals are identical to each other. The waveforms of the first and second operation data signals at this time are shown in the upper part of FIG. As shown in the middle stage of FIG. 2, the operation data inverting means 10 inverts the first operation data signal during the inversion period, and outputs the first operation data signal without inversion during the non-inversion period. Therefore, the data match determination means 11 determines that the first and second calculation data signals do not match each other during the inversion period of the calculation data inversion means 10 and that they match each other during the non-inversion period. 2 outputs a collation output signal as shown in the lower part of FIG.

The inversion and non-inversion of the arithmetic data inversion means 10 are repeated a plurality of times, and the waveform of the collation output signal from the data coincidence determination means 11 is as shown in the middle part of FIG. If the data match determination unit 11 determines that the data does not match, the retry signal is output to the first and second arithmetic processing circuits.
3 and 4, and the first and second operation data signals are collated again. Such a retry operation is performed a predetermined number of times.

By the way, the collation output signal shown in the middle part of FIG. 3 is not suitable for driving the relay 7 because the ON period and the OFF period are not the same and the duty is not constant. Therefore, this collation output signal and the signal from the gate circuit 6 which takes the AND condition of the first and second operation data signals are output to the DT flip-flop circuit 13 and the third
The read signal shown in the lower part of the figure is obtained.

The AC amplifier circuit 6A is provided with a DT flip-flop circuit.
It amplifies the read signal from 13 and drives the relay 7. As shown in FIG. 4, this AC amplifier circuit 6A
It comprises a transformer 14, a transistor 15, a diode 16, a capacitor 17, a resistor 18, and the like.

The apparatus according to the present embodiment performs the above-described processing, and the outline of the processing flowchart and the timing of the processing are shown in FIGS. Here, the “input / output batch processing” means that the output of the previous cycle and the input of the current cycle are performed simultaneously. Accordingly, in FIG. 6, the flow of the process for the current cycle is as indicated by the arrow.

In the above embodiment, the case where the number of the first arithmetic processing circuit and the number of the second arithmetic processing circuit are respectively one, that is, the case where the number of the arithmetic processing circuits is two in total has been described. 2. The plurality of arithmetic processing circuits
The total arithmetic processing circuit can be three or more. In this case, the required number of operation data inversion means is provided, and the inversion period and the non-inversion period of three or more are appropriately shifted and adjusted.

〔The invention's effect〕

As described above, according to the present invention, the operation data inversion means inverts the operation data of the first operation processing circuit during the inversion period, and the operation data of the first and second operation processing circuits is inverted during the inversion period. The data matching circuit outputs the matching output signal only when the data matching does not match each other and matches each other during the non-inversion period. There is an effect that it is possible to improve the reliability of the fail safe without erroneous verification.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.
FIG. 3 and FIG. 3 are waveform diagrams for explaining the operation of FIG.
FIG. 4 is a circuit diagram of some components in FIG. 1, FIG. 5 is a flowchart showing an outline of the processing of the apparatus according to the present invention, FIG. 6 is a waveform chart showing the timing of the processing, FIG. 7
FIG. 1 is a block diagram showing a conventional example. 1 ... input circuit, 2A ... data collation circuit, 3 ... first operation processing circuit, 4 ... second operation processing circuit, 9 ... output circuit, 10 ... operation data inverting means, 11 ... Data match determination means.

Claims (1)

(57) [Claims] After performing the same arithmetic processing on a control input signal from an input circuit in first and second arithmetic processing circuits,
The first and second operation data signals are collated by a data collation circuit, and the data collation circuit outputs a collation output signal only when the operation data signals match each other, and outputs a collation output signal to the output circuit. In an electronic interlocking device configured to permit output, the data collation circuit is configured to invert a first operation data signal from the first operation processing circuit during a predetermined inversion period; A first operation data signal via the operation data inverting means and the second operation data signal are input to the first operation data signal.
And a data match determination unit that outputs the comparison output signal only when the second operation data signal does not match each other during the inversion period and matches each other during the non-inversion period. An electronic interlocking device characterized by comprising.