JP2878745B2 - Logic simulator - Google Patents

Description

Description: Object of the Invention (Industrial Application Field) The present invention relates to a technology for simulating a logic circuit, and in particular, a logic simulator for assisting debugging of a circuit defect realized by the simulation. About.

(Prior Art) In recent years, an event-driven logic simulator has been developed to simulate a large-scale logic circuit. The event-driven method is a method in which when a certain logic gate changes, only the input of a logic circuit connected to the logic gate changes, and the signal value is calculated only along the propagation path of the logic signal.

In the event-driven logic simulator, if a defect is found in a circuit as a result of the simulation, an event generated during the simulation is necessary to debug the defect. Therefore, in order to reliably debug the logic circuit, all events from the start to the end of the simulation must be held.

However, if all the events from the start of the simulation are to be held, if the simulation using a long test pattern or the simulation of a large-scale circuit is performed, the number of events to be held becomes extremely large. For this reason, there is a problem that an enormous amount of storage area for holding events is required.

As a result of the simulation, when a defect is found in the circuit and debugging is performed, information on all events is not necessary, and an old event is hardly useful. However, since it is not known where a problem occurs during the simulation, it is not possible to judge from which point the event should be held, so that all the events have to be held.

(Problems to be Solved by the Invention) As described above, conventionally, in the event-driven logic simulator, in order to debug a defect of a circuit found as a result of the simulation, it is necessary to hold all events from the start of the simulation. Yes, the storage area for storing event information is increased. Further, it is necessary to search for a point where a problem has occurred based on an enormous amount of events, and there has been a problem that debugging work is complicated and time is required.

The present invention has been made in view of the above circumstances. It is an object of the present invention to reliably debug a logic circuit found by simulation and to reduce an event information storage area. An object of the present invention is to provide a driven logic simulator.

[Structure of the Invention] (Means for Solving the Problem) The gist of the present invention is not to hold all events, but to hold information from the latest event to an event that has gone up by a predetermined number of event cells. Is to do.

That is, the present invention provides an event-driven logic simulator that simulates the operation of a logic circuit modeled by a hardware description language, an event cell pool that holds a plurality of event cells for storing event information, Event cell acquisition means for extracting an event cell from the head of the event cell pool when a new event occurs due to a change in pattern or execution of an event, and information of the newly generated event is stored in the event cell acquired by the means. There is provided an event registering means for registering, and an event cell collecting means for adding an event cell unnecessary by execution of the event registered by the means to the end of the event cell pool.

(Operation) In the present invention, first, the event cells are initialized before executing the simulation, the information of the parent event cells of all the event cells is cleared, and all the event cells are stored in the event cell pool.

In the simulation execution, the following is performed.
First, for test patterns input from outside,
An event cell is acquired from the event cell pool, and an event is created and registered while the information of the parent event cell is cleared. When a new event occurs by executing a registered event, an event cell is acquired from the event cell pool, and an event having the event cell number of the currently executing event is created as a parent event cell. sign up. When the execution of the event is completed, the event cell of the currently executed event becomes unnecessary, and is returned to the event cell pool. At this time, the event information is stored as it is.

When using event cells in this way, use the event cells from the top of the event cell pool, and return unnecessary event cells after the execution of the event to the end of the event cell pool while preserving the event information. The event cell pool can be regarded as log information of an event recorded on an endless tape. The event cell pool always stores the information of the event that has gone up from the latest event by the number of event cells. By increasing the number of event cells to some extent, all the events are stored. Even if it is not necessary, it is possible to trace back to a large event, which is effective for circuit debugging.

As described above, according to the present invention, since information from the latest event to an event that has gone up by a predetermined number of event cells is held without holding all events from the start of the simulation, the present invention is effective for debugging a logic circuit. Backtrace of various events becomes possible.

(Examples) Hereinafter, details of the present invention will be described with reference to the illustrated examples.

FIG. 1 is a schematic configuration diagram showing a logic simulator according to one embodiment of the present invention. The simulator 10 includes an event cell pool 11, which holds event cells in a list,
An event cell acquisition unit 12 that extracts event cells from the beginning of the event cell pool 11, an event cell collection unit 13 that adds unnecessary event cells to the end of the event cell pool 11, and an event cell registration that registers event information in the event cells Unit 14, event execution unit 15 that executes events
Backtrace section that performs backtrace of events and events
It is composed of 16 mag.

As shown in FIG. 2, the event cell stores event information such as the next event cell number, time, element number, event value, and parent event cell number. Prior to the execution of the simulation, all the event cells are initialized to a parent event cell number of −1 and held in the event cell pool 11. In the event cell pool 11, the event cells form a chain by the number of the next event cell. FIG. 3 is a schematic diagram showing an example of the event cell pool 11, in which the event cells 20 are arranged in numerical order (# 1, # 2,.
n).

FIG. 4 shows an example of the circuit to be simulated, which comprises OR gates G1, G2, AND gate G3, and NOT gate G4. Now, it is assumed that the input terminals A and B of the gate G1 are both "0", and the input terminals C and D of the gate G2 are both "1". "1" to the input terminal A and is inputted as a test pattern at time T _1.

In this case, in the simulator 10 shown in FIG.
, An event cell with the number #k is fetched, an event is created, and the event is registered in the event registration unit 14. Event execution unit 15
When the event of #k is executed, the output of the gate G1 becomes "1"
, A new event occurs. Therefore,
An event cell # (k + 1) is fetched from the event cell pool 11 to create and register an event. Here, # (k +
The number of the parent event cell of the event 1) is #k.
When the execution of the event is completed, the event cell #k becomes unnecessary, and is returned to the last stage of the event cell pool 11 by the event cell collection unit 13.

Next, when the event of the event cell # (k + 1) is executed, the output of the gate G3 becomes "1", so that the event cell # (k + 2) is fetched in the same manner as described above, and the event is created and registered. Then, the event cell # (k + 1) is collected in the event cell pool 11. Further, when the event cell # (k + 2) is executed, the output of the gate G4 becomes "0".
(K + 2) is returned to the event cell pool 11. FIG. 5 is a diagram showing a state of the event cell pool 11 at this time.

Here, when the back trace is applied from the event standing at the gate G4, the back trace of the event is performed based on the number of the parent event cell of the past event stored in the event cell pool 11 as shown in FIG. It is possible to do.

FIG. 7 is a diagram showing an apparatus for performing from simulation to debugging using the simulator shown in FIG. The test pattern 30 is input to the simulator 10,
The simulation result is output from the simulator 10 according to the test pattern. The output result 40 is compared with a preset expected value 50 by the comparing means 60. If they do not match, the circuit is debugged by the debugging means 70. In this debugging, as described above, the back tracing unit 16 in the simulator 10 back traces the event cells in the event cell pool 11 and performs the debugging.

FIG. 8 is a diagram showing the relationship between test patterns and output results. Here, in the conventional method, in order to debug a circuit, it is necessary to hold events for all test patterns as indicated by broken arrows in the figure. That is, it is necessary to hold all events from the start of the simulation, and the storage capacity becomes enormous. On the other hand, in the present embodiment, not all the test patterns as shown by solid arrows in the figure, but events corresponding to test patterns in a certain area (which change with time) may be held. Less is needed.

As a check method, all test patterns are simulated, then simulated again, and the simulation is stopped near an event having a bug. At this time, since the event cell pool 11 holds an event that is up by a certain number from the latest event, the event in which a bug has occurred is also held. Therefore, by back tracing the events held in the event cell pool 11, debugging can be easily performed.

Also, instead of resimulating after simulating all the test patterns, the simulation can be completed only once by dividing the region to be simulated. That is, a checkpoint CP may be provided for each certain range, and when a bug occurs at each checkpoint, back-trace may be performed to perform debugging.

Thus, according to the present embodiment, it is possible to always hold an event that has gone up by a certain number from the latest event, and it is possible to backtrace the event without holding information on all events. . Therefore, it is possible to effectively debug the circuit. Further, since only a predetermined number of events are stored without storing all events, there is an advantage that the storage area does not increase even when a long simulation is performed.

 Next, another embodiment of the present invention will be described.

2. Description of the Related Art Conventionally, in the design of a large-scale logical system, a technique of dividing the entire system into several parts and designing hierarchically has been adopted. Correspondingly, a hardware description language can be described hierarchically, and modeling can be performed for each submodule. When this is simulated by a conventional logic simulator, the description of each submodule is compiled first, and then linked to combine the entire logic system into one load data. By loading this into the simulator, all the data of the logical system is read at once and the simulation is executed.

In such a conventional logic simulator, the size of the load data increases in proportion to the size of the target logic system. For this reason, there is a problem that the size of the logic system that can be simulated is limited by the size of the main storage area of the simulator, or that it takes time to read the load data. Also, during the execution of the simulation, not all the data of the modeled logical system is needed, but rather data of the local part is sufficient. This is also a problem.

Therefore, in this embodiment, instead of loading all the data of the logical system to be simulated, the data of the sub-module of the logical system to be simulated is loaded onto the main storage area when needed, When the main storage area becomes insufficient, the main storage area to which the data of the unnecessary submodule is loaded is released, and the data of another submodule is loaded to execute the simulation. This makes it possible to execute a simulation without loading all the data of the entire logical system at once, thereby solving the above problem.

FIG. 9 is a schematic configuration diagram showing a logic simulator according to this embodiment. The simulator 80 includes a simulator core unit 81 which is a basic element of the simulator, a main storage area 82 for storing data of sub-modules of a logical system,
A sub-module management table 83 for managing the sub-modules loaded on the main memory, a module check unit 84 for checking whether the specified sub-module is loaded on the main memory, and estimating the data amount of the sub-module data A data amount estimating unit 85, a main storage area obtaining unit 86 for obtaining a main storage area according to the estimated data amount,
Main storage area release unit 87 that releases the main storage area, data load unit that reads submodule data into the main storage area
It comprises a control unit 88 for controlling each unit and the like.
Data 90 of each sub-module constituting the logical system to be simulated is input from outside the simulator 80.

FIG. 10 shows an example of the simulated logic system, which is composed of a module MD1 and a submodule SMD2 of the highest hierarchy. At the beginning of the simulation,
First, the data amount estimating unit 85 estimates the data amount of the module MD1 in the highest hierarchy. A main storage area is secured by the main storage area acquisition unit 86 according to the estimated data amount, and data is loaded into the main storage area 82 by the data load unit 88.
At this time, the main storage area acquisition unit 86 registers the contents of the main storage area of the MD1 in the submodule management table 83. FIG. 11 is a diagram showing an example of the module management table 83.

Now, suppose that a test pattern is given to the input terminal A1 of MD1 and a simulation is performed, and an event occurs at the input terminal B2 of the submodule SMD2. In this case, the module check unit 84 checks whether the data of the sub-module SMD2 has been loaded on the main storage area. If it is not loaded, the data amount estimation unit 85
To estimate the data amount of the SMD2, and the main storage area acquisition unit 86 secures the main storage area. When the main storage area required for the SMD 2 cannot be secured, the main storage area releasing unit 87 releases the main storage area of the submodule not required for the simulation at that time, and secures the main storage area again.

Then, the data of the submodule SMD2 is loaded into the secured main storage area by the data load unit 88, and the simulation is continued. Similarly, if an event occurs at the input terminal of the sub-module during the execution of the simulation, it is checked at the same time whether or not the data of the sub-module is in the main storage area. And then load the data.

As described above, in the present embodiment, in the simulation of the hierarchical logical system, instead of loading all the data of the logical system to be simulated, when the data is needed for each sub-module, the data is It can be loaded and simulated. Further, by releasing the data of the unnecessary sub-module, the data of another sub-module can be loaded into the area. Therefore, the size of the target logical system is not limited by the size of the main storage area of the simulator, and a large-scale logical system can be simulated.

Thus, according to the present embodiment, the data of the submodule of the logical system to be simulated is loaded onto the main storage area when it becomes necessary, and becomes unnecessary when the main storage area becomes insufficient. The simulation can be performed by releasing the main storage area where the data of the submodule is loaded and loading the data of another submodule. Therefore, a simulation can be executed without loading all the data of the entire logical system at once. Therefore, the simulation of the large-scale logic system can be executed without being limited by the size of the main storage area of the simulation. In addition, since all data is not loaded at one time, there is an advantage that it does not take much time to read data.

The present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the spirit of the invention. For example, the event information registered in the event cell is not limited to the one shown in FIG. 2, but can be changed as appropriate according to the specifications. However, for back tracing, it is desirable to include the parent event cell number. Further, the size of the event cell pool may be appropriately determined according to conditions such as the complexity of the circuit to be simulated and the number of test patterns.

[Effects of the Invention] As described above in detail, according to the present invention, instead of holding all events, information of an event that has gone up by a predetermined number of event cells from the latest event is held. Therefore, the circuit can be debugged without holding all the events, and the event information storage area can be reduced, and the circuit can be effectively debugged.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a logic simulator according to one embodiment of the present invention, FIG. 2 is a schematic diagram showing the contents of an event cell, FIG. 3 is a schematic diagram showing a state of an event cell pool before simulation, FIG. 4 is a circuit configuration diagram showing an example of a circuit to be simulated, FIG. 5 is a schematic diagram showing a state of an event cell pool after simulation, FIG. 6 is a schematic diagram showing a state of a back trace, and FIG. FIG. 8 is a diagram for explaining a method, FIG. 8 is a diagram showing a relationship between a test pattern and an output result, FIG. 9 is a schematic configuration diagram showing another embodiment of the present invention, and FIG. FIG. 11 is a diagram showing an example, and FIG. 11 is a schematic diagram showing an example of a module management table. 10… Logic simulator, 11… Event cell pool, 12…
Event cell acquisition unit, 13: Event cell collection unit, 14: Event registration unit, 15: Event execution unit, 16: Back trace unit, 20: Event information, 30: Test pattern, 40: Output result, 50: Expected value, 60: comparison means, 70: debugging means.

Claims (3)

(57) [Claims] 1. An event-driven logic simulator simulating the operation of a logic circuit modeled by a hardware description language, comprising: an event cell pool for holding a plurality of event cells for storing event information; Event cell acquisition means for extracting an event cell from the head of the event cell pool when a new event occurs due to a change in pattern or execution of an event, and information of the newly generated event is stored in the event cell acquired by the means. A logic register comprising: an event registering means for registering; and an event cell collecting means for adding an event cell which becomes unnecessary by execution of the event registered by the means to the end of the event cell pool. . 2. The event information registered in an event cell by the event registration means is added with an event cell number of a parent event that caused the event to occur. Logic simulator. 3. The logic simulator according to claim 2, further comprising means for back-tracing the event information based on the parent event cell number added to the event information.