JP2878695B2 - Image processing apparatus and multi-value image estimation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention estimates the density value of each pixel of image information represented by pseudo gradation and converts input image information into a multi-valued image. The present invention relates to an image processing apparatus for performing conversion and a multi-value image estimation method.

(Prior Art) Conventionally, in order to enable communication between facsimile machines having different scanning line densities or text image processing devices, various line density conversion processes have been performed on a target image. As such a line density conversion process, an SPC method, a disjunction method (Information Processing Society of Japan Transactions PP920-925, 1985-9, a projection method (Image Electronics Society of Japan 11-2, PP72-83 1982), etc.) are known. I have.

On the other hand, in recent years, pseudo gradation expression methods such as a dither method and an error diffusion method have been frequently used mainly in document image processing devices, and the above-described line density conversion processing is also performed on image information expressed in pseudo gradation. The need has arisen.

However, the images targeted by the above-described line density conversion processing are a simple binarized image and a multi-valued image. When the line density conversion processing is performed on a pseudo gradation image such as a dither image, However, there is a problem that the gradation information and the sense of definition are lost, and furthermore, moire occurs depending on the magnification of the linear density conversion, and the image quality is largely deteriorated.

Therefore, a method has been proposed in which a halftone image is restored by a predetermined process on an image subjected to dither processing, and then a line density conversion process is performed on the halftone image (Japanese Patent Laid-Open No. 62-114377). ). However, in this process, if the size of the area to be referred to when restoring the halftone image is small, the halftone image from which the periodic component of the dither image has been completely removed cannot be restored, and the occurrence of moire is prevented. I couldn't do that. In addition, when the size of the area to be referred to is large, there is a problem that the definition, which is a feature of the dither image, is lost.

(Problems to be Solved by the Invention) As described above, in the conventional image processing method, for example, when linear density conversion is performed on image information represented by a pseudo gradation such as a dither image, gradation and sharpness are reduced. There have been problems such as impaired feeling and moire.

Accordingly, an object of the present invention is to provide an image processing apparatus and a multi-value image estimation method for estimating a multi-value image from a pseudo-tone image while maintaining the gradation and sharpness of the pseudo-tone image.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, an image processing apparatus according to the present invention is configured by inputting image information expressed in pseudo gradation and using a table using a ROM. By the identified image identification means,
An identification signal indicating a type of an image including the target pixel corresponding to a plurality of dot patterns having different variances of image points in a pixel region including a plurality of pixels centered on each target pixel of the input image information. Is output, and the opening size for the target pixel is determined by the smoothing processing means to be larger as the variance is larger based on the identification signal, and the input image information is smoothed by the opening size to obtain the target pixel. The multi-valued image data is output by calculating the density value of.

In the present invention, the image processing apparatus may further include a line density conversion processing unit for performing a line density conversion on the multi-valued image data output from the smoothing processing unit.

Furthermore, the present invention provides a method for converting image information represented by pseudo gradation into
In a multi-valued image estimating method for obtaining a density value of each pixel of interest of the image information and estimating a multi-valued image corresponding to the image information, a multi-valued image estimation method includes: From the variance of the image points, the aperture size for the pixel of interest is determined to have a larger value as the variance is larger, the image information is smoothed with the aperture size to obtain the density value of the pixel of interest, and the multivalued image is obtained. It is characterized by being estimated.

(Operation) In the present invention, the type of an image including a target pixel is determined in correspondence with a plurality of dot patterns having different variances of image points in a pixel region including a plurality of pixels centered on each target pixel of image information. An identification signal is output, and based on this, the aperture size for the pixel of interest is determined to be larger as the variance is larger. That is, when the variance is large, corresponding to a plurality of dot patterns having different variances of the image points,
Since the density change is gradual, it is determined to be, for example, a periodic component of the dither image, and if the variance is small, it is determined to be a character / line figure or edge portion where the density change is steep.

In the former case, by increasing the aperture size based on such a result of identification, the periodic component of the dither image is removed to prevent the occurrence of moire and to express the gradation well. In the latter case, by reducing the opening size, the density value can be correctly estimated without impairing the fineness (sharpness).

Further, for the multi-valued image estimated as described above,
By performing the linear density conversion, it is possible to obtain a scaled image that retains the gradation and definition of the input image information represented by the pseudo gradation.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to one embodiment of the present invention. The image processing apparatus 10 includes an image input interface 1, an N-line memory 2, an image identification circuit 3, a smoothing processing circuit 4, and a line density conversion processing circuit 5.
And a dithering processing device 6. The image input interface 1 sends to the N-line memory 2 binary image data represented by pseudo gradation input from outside via the transmission path 7. An N-line memory 2 stores N lines of binary image data S input via the input interface 1 and stores several pixels necessary for multi-value image estimation centering on a target pixel in an image identification processing circuit 3 and a smoothing processing circuit. 4 is output in parallel. The image identification circuit 3 is configured by a table using a ROM, and based on the binary image data received from the N-line memory 2, what kind of image each pixel of interest in the image is included in, that is, a dither image It is determined in several steps whether the data is close to a character or a character, and an image identification signal SW as a result of the determination is output to the smoothing processing circuit 4. The smoothing circuit 4 smoothes the image data of the reference area sent from the N-line memory 2 with an aperture size based on the image identification signal SW sent from the image identification circuit 3 and is a result of estimating the density value of the pixel of interest. Output multi-valued image data SG. The linear density conversion processing circuit 5 performs a linear density conversion on the multi-valued image data SG output from the smoothing processing circuit 4. The dithering processing circuit 6 creates a dither image based on the multivalued image data after the line density conversion input from the line density conversion processing circuit 5.

In the image processing apparatus 10 configured as described above, when the binary image data S is input to the image interface 1 via the transmission path 7, the binary image data S
The data is sequentially stored in the N-line memory 2. N line memory 2
As shown in FIG. 2, for example, a data bus 21 is connected to a bidirectional driver register 22, an image memory 23, and a serial / parallel conversion circuit 24.
In this embodiment, the image memory 23 has a capacity for storing image data for eight lines. When the storage area corresponding to each of these lines and L ₀ ~L _7, first, the image memory 23 the binary image data S to be input serially from the data image input interface 1 via the data bus 21
To store one line in the L _0. When the image data of one screen point on the next line is stored in the image memory 23, prior to it, the image data before one stroke point the line of already written to the L ₀ of the image memory 23 is Read and stored in bidirectional driver register 22. This bidirectional driver register 22
The stored image data is written in one stroke th point of the storage area L ₁ of the next line of the image memory 23 via the data bus 21 to. At the same time, one of the newly input next lines
Data having the image-th point is stored in one stroke th point of L _0. When the image memory 23 by repeating such an operation is full, then every time the image data of a new line is one dot input, stored in the L ₀ ~L ₆ arranged in the dot in the sub-scanning direction 7-bit image data are read out onto the data bus 21, so that the 8-bit data obtained by adding 1 bit to be newly entered is stored in the corresponding main scanning direction position of the L ₀ ~L _7.

On the other hand, the serial / parallel conversion circuit 24
Each time 1-bit image data is written to 23, 8-bit image data on data bus 21 is shifted in in synchronization with writing to image memory 23. When the 8-bit image data is input, the serial-parallel conversion circuit 24 outputs parallel data of 8 bits for each bit, that is, 8 lines × 8 bits = 64 bits.

FIG. 3 is a diagram two-dimensionally showing 8-line × 8-bit parallel image data output from the serial / parallel conversion circuit 24 of the N-line memory 2. Assuming that the pixel of (X ₀ , Y ₀ ) indicated by oblique lines is the pixel of interest, the image data of the peripheral pixel area M of 3 lines × 4 dots centered on the pixel of interest is input to the image identification circuit 3.

The image identification circuit 3 comprises, for example, a ROM 9 as shown in FIG. The contents of the ROM 9 are determined based on, for example, statistical data as shown in FIG. In this graph, a plurality of halftone dot images and character images each composed of binary image data are prepared as sample images, and the cumulative occurrence frequency of the pattern observed when these sample images are scanned through a 3 × 4 aperture. It is a graph in which values are arranged in descending order or in increasing order. From such statistical data, it can be estimated whether a certain pattern is a part of a halftone image or a part of a character image. Therefore, all of the 3 × 4 dot patterns are classified into 10 classes, and the degree of dispersion is high (it is highly likely that they are halftone dots).
Low degree of dispersion from the class (likely a character image) in correspondence signals SW ₀ to SW ₉ to class are tabulated. ROM9 inputs the dot pattern of the peripheral image region M as an address, and outputs the image identification signal SW ₀ to SW ₉ as data.

Further, the image data of 8 × 8 pixels of the N-line memory 2 shown in FIG.
As shown in FIG. 6, the smoothing processing circuit 4 includes bit counting circuits 40a to 40f, adders 41a and 41b, and dividers 42a to 42d.
And a switch 43. Input data I1 ~
I7 is data obtained by combining outputs of 8 × 8 pixels from the N-line memory 2 as follows. Regarding I2 to I7, the corresponding pixels in FIGS. 7A to 7F are indicated by “*”.

I1: (Y, X) = (0,0) I2: (Y, X) = (0,0), (0,1), (1,0), (1,1) I3: (Y, X ) = (1, -2), (1,3), (2, -2), (2,
3) I4: (Y, X) = (-1, -1), (-1,0), (-1,1,),
(−1,2), (0, −1), (0,0), (0,1), (0,2),
(1, -1), (1,0), (1,1), (1,2), (2, −
1), (2,0), (2,1), (2,2) I5: (Y, X) = (− 3, −2), (− 3, −1), (− 3,
0), (−3,1), (−3,2), (−3,3), (−2−
2), (−2, -1), (−2,0), (−2,1), (−2,
2), (−2,3), (−1-2) (− 1,3), (0, −
2), (0,3) I6: (Y, X) = (4, -3), (4, -2), (4, -1),
(4,0), (4,1), (4,2), (4,3), (4,4), (-
3, -3), (-3,4), (-2, -3), (-2,4), (-
1,3), (-1,4), (0, -3), (0,4) I7: (Y, X) = (1, -3), (1, -2), (1, 3), (1,
4), (2-3), (2-2), (2,3), (2,4),
(3, -3), (3-2), (3, -1), (3,0), (3,
1), (3,2), (3,3), (3,4) The smoothing processing circuit 5 performs 1 × 1 pixel (I1) and 2 × 2 pixel (I2) based on the input data I1 to I7. ), 4 × 4 pixels (I
4), 6 × 6 pixels (I3 + I4 + I5), 8 × 8 pixels (I4 + I5 + I6
+ I7) The smoothing process is performed simultaneously with the five types of opening sizes. Therefore, each of the bit counting circuits 40a to 40f counts the number of white or black pixels included in each of the input data I2 to I7. The adder 41a adds the bit count outputs of I3, I4, and I5, and
The result of counting the bits in the aperture size of the pixel is calculated.
The adder 41b adds the bit count outputs of I4, I5, I6, and I7,
The bit count result for the aperture size of 8 × 8 pixels is calculated. The dividers 42a to 42d are circuits for dividing the number of white or black pixels by the number of aperture pixels in order to obtain an estimated density at each size aperture. Switcher 43, estimated concentration I1 for each aperture size determined simultaneously in this way, selected by the image discrimination signal SW ₀ to SW ₉ output by the image identification circuit 3 one of Ta to Td. For example, an image dot dispersion size of the image identification signal SW _0, SW
Assuming that ₉ is a large pixel concentration, the SW ₀ side selects an estimated density based on 6 × 6 or 8 × 8 pixels with a large aperture size, and the SW ₉ side estimates with a 1 × 1 or 2 × 2 pixel with a small aperture size. select the density, the intermediate of SW ₃ to SW _5, select the estimated concentration with the opening size of 4 × 4. As a result, the aperture can be increased in the dither image portion and the aperture can be reduced in the character image portion, and the multi-valued image estimation that reproduces the fine portion without the dither period component of the dither image of the input image is performed. Is possible.

The multi-valued image SG estimated in this manner is enlarged or reduced by the linear density conversion processing circuit 5, further multi-valued by the dithering processing circuit 6, and output as a binary image.

FIG. 8 is a diagram showing an image processing apparatus according to a second embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. In the previous embodiment, the image processing was performed online and in real time using the N-line memory 2. In this embodiment, the batch processing is performed using the binary image page memory 51 instead of the N-line memory 2. The case is shown.

The binary image page memory 51 stores the binary image data input from the transmission path 7 via the input interface 1 in page units. The image discriminating circuit 3 and the smoothing processing circuit 4 estimate a multivalued image with an appropriate aperture size from the binary image data stored in the binary image page memory 51 by the above-described processing. The N-line multi-valued memory 52 sequentially stores the multi-valued images estimated by the smoothing processing circuit 4 for N lines. The number of lines of the image stored in the N-line multi-valued memory 52 is determined by the magnification at which the line density conversion circuit 5 enlarges or reduces. For example, when the scaling ratio of the line density conversion circuit 5 is 0.5, two lines are converted to one line, so that it is necessary to store a multi-valued image of at least two lines. The multi-valued image that has been scaled by the linear density conversion processing circuit 5 is dithered by the dithering processing circuit 6 and is converted into a binary image page memory.
Stored in 51. Then, after all the scaling processes are completed, the dither image generated on the binary image page memory 51 is sent to the outside via the output interface 53.

FIG. 9 and FIG. 10 are views showing an image processing apparatus according to a third embodiment of the present invention. This embodiment uses the ROM of the image identification circuit 3 used in the first and second embodiments described above.
Is not changed, and the type of the image including the target pixel is accurately determined with reference to a wider range of peripheral pixel regions. The ROM 9 performs the same operation as the ROM shown in FIG. The image identification signal SW from the ROM 9 is N
For example, nine lines are stored in the line memory 61. M
The bit register 62 reads a matrix of the image identification signals SW corresponding to the nine peripheral pixel areas A to I shown in FIG. The determination circuit 63 determines the identification signal obtained from the area A including the target pixel indicated by hatching in FIG. 10 and the eight areas B to I around the area A.
Is compared with the image identification signal SW obtained from. When the image identification signal of the area A matches the image identification signal SW of the areas B to I, the image identification signal SW of the area A is output as it is, and the image identification signal of the area A and the image identification signal of the areas B to I are output. signal
If the SW is different, it is determined that the binary image in the area A may contain noise, and the eight areas B around the area A are determined.
The image identification signal of the pixel of interest is determined in consideration of the image identification signals of .about.I.

According to this embodiment, the aperture for determining the type of image can be widened without changing the capacity of the ROM 9 at all, and there is an effect that erroneous determination due to the influence of noise included in the input image can be prevented.

FIG. 11 and FIG. 12 are views showing an image processing apparatus according to a fourth embodiment of the present invention. This embodiment is an example in which a multi-valued image is estimated by software. Here, as shown in FIG. 11, the system used connects the input interface 1, the image memory 51, the CPU 71, the determination table 72, and the work memory 73 to each other via a bus 74. It is configured.

The image memory 51 stores the binary image data S input from the outside.
Is stored via the input interface 1. CPU71
Estimates a multi-valued image from the binary image data stored in the image memory 51 by the following processing. Hereinafter, the operation of the CPU 51 will be described with reference to the flowchart of FIG.

The Y address and the X address of the pixel of interest in the binary image are determined (St. 1 and 2). Then, the coordinates of the pixels in the peripheral pixel area for determining the type of the image to which the pixel of interest belongs are determined (St. 3), and the pixel information of the coordinates is read from the binary image. The information is rearranged one-dimensionally, input as the array address of the determination table 72, and (S
t.4) Find the type of image to which the noted pixel belongs. The output of the determination table 52 corresponds to the opening size of the reference area including the target pixel. Therefore, based on this opening size, the coordinates of each image point to be taken out within the reference area are obtained (St.
Five). The pixel information of the coordinates is read from the binary image, and the pixel information in the reference area read by the above processing is added.
The density of the target pixel is estimated by dividing the addition result by the number of pixels within the aperture size (St. 6). This estimation result is stored in memory 73
(St. 7), and the processing of one pixel stored in the image memory 51 ends. This processing is performed for all the pixels of the binary image stored in the image memory 51 (St. 8,
9).

After the CPU 71 completes the process of estimating the multi-valued image from the binary image, the CPU 71 may perform the linear density conversion process as needed.

The present invention is not limited to the embodiments described above. For example, in the above-described embodiment, the ROM table of the image identification circuit is statistically created using the binarized character image and the halftone image, but the image itself obtained by dithering the character image or the grayscale image is used. May be used to create an image identification table.

Further, the opening size of the reference area can be set to a size other than the size shown in the embodiment.

Further, by inputting a color image as a single-color image such as R, G, B, and performing the above-described processing on the input image, image processing corresponding to the color image can be performed.

Furthermore, the present invention is applicable not only to binary dithering but also to multi-valued image estimation of multi-valued dither, and is also applicable to images represented by other pseudo gradations such as an error diffusion method. is there.

[Effects of the Invention] As described above, according to the present invention, the opening size of the reference area is set according to the type of the target image point, and the density of the target image point is estimated from the image information in the reference area. Therefore, it is possible to provide an image processing apparatus capable of accurately estimating a multi-valued image while maintaining the gradation and sharpness of the pseudo gradation image.

[Brief description of the drawings]

1 to 7 are diagrams showing a first embodiment of the present invention. FIG. 1 is a block diagram showing a configuration of an image processing apparatus. FIG. 2 is a block diagram showing a configuration of an N-line memory. FIG. 3 is a view showing a peripheral pixel area, and FIG. 4 is a view showing RO constituting an image identification circuit.
M is a block diagram, FIG. 5 is a diagram showing statistical data for determining the contents of the ROM, FIG. 6 is a block diagram showing a configuration of a smoothing processing circuit, and FIGS. 7 (a) to (f) are smoothing processes. FIG. 8 is a diagram showing image data input to a circuit, FIG. 8 is a block diagram showing a configuration of an image processing apparatus according to a second embodiment, and FIG.
FIG. 10 is a block diagram showing a configuration of a main part of the image processing apparatus according to the fourth embodiment, FIG. 10 is a diagram showing a peripheral pixel area referred to by the same apparatus, and FIG. FIG. 12 is a block diagram showing the configuration, and FIG. 12 is a flowchart showing the processing operation of the apparatus. 1 ... Image input interface, 2,61 ... N line memory, 3 ... Image identification circuit, 4 ... Smoothing processing circuit, 5 ...
... Line density conversion processing circuit, 6 ... Dithering processing circuit, 7 ...
… Transmission line, 9… ROM, 10,50,60,70 …… Image processing device,
21, 74 data bus, 22 bidirectional driver register, 23 image memory, 24 serial-parallel conversion circuit, 40a-40f bit counter circuit, 41a, 41b adder, 42a- 42d: Divider, 43 switcher, 51: Binary image page memory, 52: N-line multi-valued memory, 53: Output interface, 62: M-bit shift register, 63 ...
... Judgment circuit, 71 ... CPU, 72 ... Judgment table, 73 ...
memory.

Claims (3)

(57) [Claims] An input means for inputting image information represented by pseudo gradation and a table using a ROM, wherein a plurality of pixels centered on each pixel of interest of the image information input by the input means are provided. Corresponding to a plurality of dot patterns having different variances of image points in a pixel area, an image identification unit that outputs an identification signal indicating a type of an image including the target pixel, and the target pixel based on the identification signal. Is determined such that the larger the variance, the larger the variance becomes, and the image information input by the input means is smoothed with the aperture size to obtain the density value of the pixel of interest, thereby obtaining multi-valued image data. An image processing apparatus comprising: a smoothing processing unit for outputting. 2. The image processing apparatus according to claim 1, further comprising a line density conversion processing unit for performing a linear density conversion on the multi-valued image data output from the smoothing processing unit. 3. A multi-valued image estimating method for obtaining a density value of each pixel of interest of the image information from the image information represented by the pseudo gradation and estimating a multi-valued image corresponding to the image information. From the variance of image points in a pixel area composed of a plurality of pixels centered on each pixel of interest, the aperture size for the pixel of interest is determined to be larger as the variance is larger, and the image information is A multi-valued image estimating method, wherein the multi-valued image is estimated by obtaining a density value of the pixel of interest by performing a smoothing process on a size.