JP2875938B2 - Threshold voltage setting circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to signal processing in a magnetic disk drive, and more particularly to a threshold voltage setting circuit of a maximum likelihood detector used for recording and reproduction using a partial response.

2. Description of the Related Art As the speed and capacity of a magnetic disk device increase, the frequency of a signal handled by a demodulation circuit increases, and the recording density on a recording medium also increases, so that the signal quality is significantly deteriorated. When demodulating such a degraded signal, it is becoming difficult to perform highly reliable demodulation by conventional peak detection.

[0003]

2. Description of the Related Art A partial response system for sampling a reproduced signal to which controlled waveform interference has been added at a bit rate and demodulating the signal as an effective method instead of peak detection has been known for a long time. For example, the following document discloses a partial response method.

(1) E. R. Kretzmer, "Ge
neralization of Technik
e for Binary Data Comuni
site ", IEEE Trans. Comm.
Tech COM-14, pp. 67-68, (19
66).

(2) H. Kobayashi and
D. T. Tang, "Application of
Partial Response Channel
Coding to Magnetic Record
Ding Systems ", IBM J. Res.
Developer. , 14, No. 4, pp. 36
8-375, (1970).

[0006] In a class 4 equalization method which is one of the equalization methods of the partial response method, an attempt to incorporate a maximum likelihood detection method is being studied. This attempt has been proposed, for example, in the following document:

(3) M. J. Ferguson, "O
ptimal Reception for Binar
y Partial Response Channel
ls ", The Bell System Techn
ical journal Vol 51, No. 5; 2,
pp. 493-505, (1972).

(4) Roger W. Wood and
David A. Petersen, "Viter
bi Detection of Class IV
Partial Response on a Mag
netic Recording Channel ”,
IEEE Trans. Comm. COM-3
4, pp. 454-461, (1986).

In these methods, a data string having the highest likelihood is derived from the read sample value string, and this is output as a detection result. Input sample value sequence is input to the state detector, before the previous state dependent to varying the threshold voltage V _th ^+, V _th ^- is compared with the state of the input sample values must be determined.

FIG. 7 is a block diagram of a reproducing system of a general magnetic disk drive. In the figure, the reproducing system has a magnetic head 10, an amplifier 20, an equalizer 30, a state detector 40, and a decoder 50. The magnetic head 10 reads information stored in the disk and sends a small signal to the amplifier 2.
Output to 0. The amplifier 20 amplifies this small signal and outputs it to the equalizer 30. The equalizer 30 equalizes the output signal from the amplifier 20 so that the amplitude of the high-frequency component increases. The state detector 40 compares the equalized signal with two threshold voltages described later, and detects the state of this signal at predetermined intervals. Therefore, the output signal of the state detector 40 becomes a sample value sequence. This sample value is a state of the input signal temporarily determined. Therefore, the decoder 50
Derives a data sequence with the highest likelihood from a sample value sequence indicating the state of the input signal temporarily determined, and outputs this as a decoded signal. For the processing of the decoder 50, for example, a Viterbi demodulation method using a known partial response method is used.

The sample value sequence output from the state detector 40 is used for controlling the two threshold voltages.

FIG. 8 is a block diagram showing the internal configuration of the state detector 40. As shown in FIG. As shown, the state detector 40 includes a comparator 42 and a threshold voltage setting circuit 44. The comparator 42 converts the input signal from the equalizer 30 shown in FIG.
Two threshold voltage V _th ⁺ and V _th ^- compared to determine the state of the input signal. For example, when the amplitude of the input signal is larger than the threshold voltage V _th ⁺ , the state of the input signal is A
It is determined to be the threshold voltage V _th ^- when small than, the state of the input signal is determined to be C. Further, the amplitude of the input signal is two threshold voltages V _th ⁺ and V _th ^- when it is between the state of the input signal is determined to be B.

The threshold voltage setting circuit 44 includes the equalizer 30
, And an output signal of the comparator 42 (a signal indicating the determined state), and the threshold voltages V _th ⁺ and V _th
th ^- to change the value of. This change depends on the state of the previous input signal.

[0014] Figure 9 is the threshold voltage V _th ⁺ and V _th ^- is a diagram showing changes of. In Figure 9, the sample values of X1-X10 are input signals, AL is the threshold voltage V _th ⁺ and V _th ^- the difference between, k is number that indicates the timing of the sampling, X _k
Is the sample value of the k-th input signal. A,
B and C represent the states of the input signal determined as described above. Further, the voltage difference AL is an amplitude corresponding to a theoretical value “1” in the partial response system.

The comparator 42 calculates the k-th sample value X _k
Is determined as follows.

[0016] (1) When ^{_{X k> V th + (k}} ), the state ^{_{A (2) V th + (}} k) ≧ X k> V th - when _(k), the state B (3) V _th ^- _(k) when ≧ X _k, also state C, the threshold voltage V _th ⁺ _(k) and V _th of the time ^- _(k)
Is dependent on the (k-1) th state, and the threshold voltage setting circuit 44 controls as follows.

[0017] (1) when the k-1 th state is ^{_{"A", V th + (}} k) = X k-1 V th - (k) = X k-1 -AL (2) The k when -1st state is ^{_{"B", V th + (}} k) = V th + (k-1) V th - (k) = V th - (k-1) (3) (k-1) -th When the third state is “C”, V _th ⁺ _(k) = X _k−1 + AL V _th ⁻ _(k) = X _k−1 where 0 ≦ | X _k | ≦ AL The threshold voltage setting circuit 44 sequentially determines the threshold voltage V according to the state of the (k-1) th input signal for the maximum likelihood detection for removing the influence of noise and interference between waveforms.
_th ⁺ and V _th ^- changing the comparator 42 the threshold voltage V _th ⁺ and V _th ^- outputting the state of the provisional judgment result becomes an input signal using a.

FIG. 10 is a block diagram showing a configuration of threshold voltage setting circuit 44 shown in FIG. As illustrated, the threshold voltage setting circuit 44 includes a selection circuit 44A, an adder 44B, a selection circuit 44C, and a controller 44D. The selection circuit 44A includes a switch S1, selects one of the voltages + AL and -AL generated by a voltage generator (not shown), and outputs the selected voltage to one input terminal of the adder 44B. The input signal (X in FIG. 10) from the equalizer 30 is provided to the other input terminal of the adder 44B.
The adder 44B adds the input signal X and the voltage selected by the selection circuit 44A and outputs the result to the selection circuit 44C.

The selection circuit 44C has two switches S2 and S
3 is provided. The switch S2 is connected to the input signal X and the adder
44B output signal is selected, and the threshold voltage is selected.
Pressure V _th ⁺Output as Similarly, switch S3 is an input
Select either signal X or output signal of adder 44B
And the threshold voltage V_th ^-Output as

The controller 44D controls the selection circuits 44A and 44C according to the above (1)-(3) based on the (k-1) -th state output from the comparator 42 shown in FIG.

[0021]

However, the above-mentioned prior art has the following problems. As shown in FIG.
The threshold voltage V _th ⁺ and V _th ^- for the generation, the threshold voltage setting circuit 44 uses the adder 44B. The adder 44B is a circuit including a plurality of transistors. Therefore, it takes time from when the input signal X is supplied to when the output signal is determined. At this time, if the data rate is increased and the sampling interval is shortened, the operation becomes difficult in terms of threshold voltage follow-up characteristics and calculation errors. Therefore, it is difficult to determine the state of the input signal at high speed, and it is extremely difficult to reproduce the signal at high speed.

Accordingly, it is an object of the present invention to solve the above-mentioned conventional problems and to provide a high-speed operation threshold voltage setting circuit capable of speeding up the state determination of an input signal.

[0023]

FIG. 1 is a block diagram showing the principle of the present invention. According to the present invention, in the information reproducing system using the partial response system, the first voltage of the node (t2) in the floating state is driven by the read signal read from the magnetic recording medium, and the logic "1" of the partial response system is used. Amplitude equivalent to "
A second voltage higher than the first voltage and the amplitude AL
Voltage generating circuit 100 for generating a third voltage which is only lower
The first voltage and the second voltage based on a predetermined control signal.
Threshold and a selection circuit 200 for outputting a ^- voltage and third respectively select two from the voltage of the first threshold voltage V _th ⁺ and the second threshold voltage V _th of This is a voltage setting circuit.

[0024]

Assuming now that the amplitude of the read signal is X, the first voltage is X, the second voltage is X + AL, and the third voltage is X-AL. The voltage generation circuit 100 always outputs the second voltage X + AL and the third voltage X-AL following the read signal. The second voltage X + AL and the third voltage
Is generated based on a voltage X obtained by driving a node in a floating state with a read signal,
The second voltage X + A always follows the amplitude X of the read signal.
L and the third voltage X-AL can be generated with high accuracy. Therefore, it is possible to solve the problems of the threshold voltage follow-up characteristic and the calculation error caused by using the adder as in the related art.

The selection circuit 200 includes a first voltage X and a second voltage X.
Are selected in accordance with a predetermined control signal from a voltage X + AL and a third voltage X-AL, and a first threshold voltage V
_th ⁺ a second threshold voltage V _th ^- outputting a. The predetermined control signal indicates, for example, a past state determination result.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a block diagram of a threshold voltage setting circuit according to one embodiment of the present invention. The illustrated threshold voltage setting circuit is provided in the state detector 40 shown in FIG. 7, and more specifically, is used in place of the conventional threshold voltage setting circuit 44 shown in FIGS. 8 and 10. is there.

The voltage generating circuit 100 includes voltage sources 110 and 3
And two buffers 120, 130 and 140. Voltage source 110 has output terminals t1, t2 and t3. The output terminal t2 corresponds to the middle point in the floating state described above. The terminal t1 outputs a voltage X + AL higher than the midpoint voltage X by AL in a high impedance state, and the terminal t3 outputs a voltage X-AL lower than the midpoint voltage X by AL in a high impedance state.

The buffer 120 receives an input signal X from the equalizer 30 shown in FIG. This buffer 120 outputs an input signal X received at a high impedance in a low impedance state. The input / output characteristics of the buffer 120 are linear. The output terminal of the buffer 120 is connected to the midpoint terminal t2 of the voltage source 110. Therefore, the midpoint terminal t2 of the voltage source 110 is driven by the input signal X. The input signal X output from the buffer 120 is output from the voltage generation circuit as a voltage V2. Terminal t of voltage source 110
Voltage X + AL output from 1 is output as voltage V1 via buffer 130, and voltage X-AL output from terminal t3 is output as voltage V3 via buffer 140. The buffers 130 and 140 are buffers having linear characteristics for outputting a voltage received at a high impedance at a low impedance.

The selection circuit 200 has two switches S4 and S
5 Switch S4 has contacts c1, c2, c3, and switch S5 has contacts c3, c4, c5. The contacts c1, c2 and c3 are respectively connected to the voltage generation circuit 100
Are supplied. The switch S4 selects one of the voltages V1 and V2 and outputs it as a threshold voltage _Vth ⁺ via a contact c4. Switch S
5 selects one of voltages V2 and V3, the threshold voltage V _th through the contact c5 ^- output as. Switch S4
And S5 are controlled based on a control signal output from the controller 300. This control signal is generated based on the output signal of the comparator 42 shown in FIG. For example, as mentioned above,
The threshold voltage V _th ⁺ and V _th on the basis of the evaluation result of the k-1-th input signal wherein X ^- voltage value is determined for. Here, the algorithm of this determination is shown again.

[0031] (1) when the k-1 th state is ^{_{"A", V th + (}} k) = X k-1 V th - (k) = X k-1 -AL (2) The k when -1st state is ^{_{"B", V th + (}} k) = V th + (k-1) V th - (k) = V th - (k-1) (3) (k-1) -th When the third state is “C”, V _th ⁺ _(k) = X _k−1 + AL V _th ⁻ _(k) = X _k−1 where 0 ≦ | X _k | ≦ AL threshold voltage V _th ⁺ and V _th ^-
Is output to the comparator 42 shown in FIG.

FIG. 3 is a block diagram showing a configuration of voltage source 110 shown in FIG. The illustrated voltage source 110 includes a reference voltage source 111, a current source 112, a first current mirror circuit (# 1) 113, and a second current mirror circuit (# 2).
114, and two resistors R. The input terminal of the first current mirror circuit 113 is connected to the current source, and the first output terminal is connected to the input terminal of the second current mirror circuit 114. Also, the first current mirror circuit 1
The 13 second output terminal is connected to the output terminal of the second current mirror circuit 114 via two resistors R connected in series. A connection node between the two resistors R corresponds to the terminal t2 of the voltage source 110, and the other end corresponds to terminals t1 and t3.

The reference voltage source 111 generates a predetermined reference voltage, and the current source 112 generates a current Iref corresponding to the reference voltage.
Generate This current Iref flows into the input terminal of the first current mirror circuit 113. The first current mirror circuit 113 outputs currents I1 and I2 having the same magnitude as the input current Iref via the second and second output terminals, respectively. The current I1 output from the first current mirror circuit 113 is
4 flows into the input terminal of the second current mirror circuit 1
Reference numeral 14 outputs a current I3 via an output terminal. As described above, the first current mirror circuit 113 is a discharge-type current source, and the second current mirror circuit 114 is a suction-type current source.

The current I2 is generated by two resistors R connected in series.
Through the second current mirror circuit 11 as a current I3.
Flow into 4. When the output current of the first current mirror circuit 113 flows through the resistor R, I2 ·
An R voltage drop occurs. This voltage drop I2 · R is equal to the voltage AL. The second current mirror circuit 11
When the output current I3 flows through the resistor R, a voltage drop of I3 · R occurs at both ends. This voltage drop is I
Equal to 2 · R, and thus to AL.

The voltage source 110 shown in FIG. 3 generates a voltage using a voltage drop generated in a resistor connected between the two current mirror circuits 113 and 114. here,
The resistance values of the two resistors R are equal to the first current mirror circuit 1
It is assumed that the equalization resistance value of each of the thirteenth and second current mirror circuits 114 is sufficiently smaller. By doing so, a voltage source maintained at a high impedance can be obtained from the power supply and the ground, and the midpoint t2 is set to a floating state. This midpoint t2 is set to the input signal X (= V
By driving in 2), the voltages V1 and V3 offset vertically by the potential difference AL can be obtained.

FIG. 4 is a circuit diagram of the voltage source 110. FIG.
The reference voltage VTH generated by the reference voltage source 111 shown in FIG. This current source 112 has bipolar transistors Q1-Q14, Q30, Q31, resistors R1-R3, R8-R19, R27-R29, and a capacitor C1. Current source 1 consisting of these components
Reference numeral 12 denotes a differential input operational amplifier (operational amplifier). The base of the transistor Q2 functions as one input terminal of the operational amplifier, and the base of the transistor Q7 functions as the other input terminal. Transistors Q2 and Q7
Are always compared and controlled so that these base potentials are always equal. More specifically,
Reference voltage VTH applied to the base of transistor Q2
And the voltage drop generated by the resistor R19 are constantly compared,
The current flowing through the resistor R19 is controlled so that this voltage drop becomes equal to the reference voltage VTH. The current flowing through the resistor R19 is the current Iref shown in FIG. This current Iref acts as an input current of the first current mirror circuit 113.

The first current mirror circuit 113 includes bipolar transistors Q15, Q17, Q19-Q25
And resistors R4 to R7. The current Iref flowing through the resistor R19 becomes the collector current of the transistor Q15. Due to the current mirror effect of the transistors Q15, Q19 and Q24, the current I1 flowing from the transistors Q19 to Q20 and the current I2 flowing from the transistors Q24 to Q25 are the same as the collector current of the transistor Q15. This current I1 is supplied to the second current mirror circuit 11
4, and the current I2 is output to the resistor R24.
This resistor R24 corresponds to the resistor R connected between the terminals t1 and t2 in FIG.

The second current mirror circuit 114 includes bipolar transistors Q18, Q21, Q26-Q29,
And resistors R20-R26. Transistor Q2
The collector current I1 of 0 becomes the collector current of the transistor Q21. Due to the current mirror effect of the transistors Q21 and Q29, the current I3 flowing through the transistors Q28 and Q29 is equal to the current I1. The current I
3 is a current flowing through the resistor R25 and is equal to the current I2 flowing through the resistor R24. Note that the resistor R25 corresponds to the resistor R connected between the terminals t2 and t3 in FIG.

As described above, the resistors R24 and R25 are connected between the high impedance first current mirror circuit 113 and the second current mirror circuit 114, and V1 and V3 are set by the voltage drop flowing therebetween. Is generated.

FIG. 5 is a circuit diagram of the buffer 120 shown in FIG. The other buffers 130 and 140 also have the same circuit configuration as the buffer 120. Buffer 120
Is a bipolar transistor Q32-Q43 and a resistor R3
2-R38. As described above, the buffer 12
0, 130 and 140 output the input signal as it is and convert the high input impedance to a low output impedance.
As shown, the buffer 120 is constituted by a differential input operational amplifier. That is, the base potential of the transistor Q33 is controlled so as to be the same as the potential of the base of the transistor Q32 acting as the input terminal IN of the buffer 120. The output terminal OUT of the buffer 120 is connected to the emitter of the transistor Q35. That is, the output of the buffer 120 has a low output impedance emitter follower configuration. Reference voltage Vref is applied to the base of transistor Q38, and determines the amount of current flowing through transistors Q39-Q43 acting as a current source. That is, the emitter voltage of transistor Q42 changes according to reference voltage Vref. Note that the transistor Q34 functions as a load of the differential stage including the transistors Q32 and Q33.

FIG. 6 is a circuit diagram showing a configuration of switch S4 of selection circuit 200 shown in FIG. In FIG. 2, the voltages V1, V2, and V3 are shown as voltages of a single signal line for convenience, however, it is actually preferable to adopt a differential voltage configuration as shown in FIG. That is, the voltages V1, V2, and V3 are each a difference voltage between the two voltages.

The switch S4 has constant current sources 210, 212,
214 and bipolar transistors Q44-Q49. Transistors Q44 and Q45 form a differential amplifier, and transistors Q46 and Q47 also form a differential amplifier. The bases of transistors Q44 and Q45 are connected to a contact corresponding to contact c1 in FIG. Similarly, the bases of transistors Q46 and Q47 are connected to a contact corresponding to contact c2 in FIG. The collectors of the transistors Q44 and Q45 are connected to a contact corresponding to the contact c4 shown in FIG. Similarly, the collectors of transistors Q46 and Q47 are connected to contacts corresponding to the contacts shown in FIG. Note that the collectors of the transistors Q44 and Q46 are connected to the constant current source 210, and the collectors of the transistors Q45 and Q47 are connected to the constant current source 212.

Transistors Q48 and Q49 form a differential amplifier. The collector of transistor Q48 is connected to the emitters of transistors Q44 and Q45, and the collector of transistor Q49 is connected to the emitters of transistors Q46 and Q47. Transistors Q48 and Q49
Is connected to the constant current source 214. Transistor Q4
The bases of 8 and Q49 receive the control signal. When a high-level control signal is applied to the base of transistor Q48 and a low-level control signal is applied to the base of transistor Q49, transistors Q44 and Q45 are turned on, and the above-described voltage V1 applied to contact c1 is applied to contact c4. Is transmitted. When a high-level control signal is applied to the base of transistor Q49 and a low-level control signal is applied to the base of transistor Q48, transistor Q4
6 and Q47 are turned on, and the aforementioned voltage V2 applied to the contact c2 is transmitted to the contact c4.

The switch S5 of the selection circuit 200 shown in FIG. 2 has the same configuration as the configuration shown in FIG.

The embodiment of the present invention has been described. Although bipolar transistors are used in the above embodiments, other types of transistors may be used. Further, instead of the first current mirror circuit 113 and the second current mirror circuit 114, another high impedance current source may be used.

[0046]

As described above, according to the present invention,
In the information reproducing system using the partial response method, the first voltage of the node in the floating state is driven by the read signal read from the magnetic recording medium, and only the amplitude AL corresponding to the logic "1" of the partial response method is used. A second voltage higher than the first voltage;
A third voltage lower by the amplitude AL is generated, and the first voltage, the second voltage, and the third voltage are generated based on a predetermined control signal.
And the second threshold voltage is selected to output the first threshold voltage and the second threshold voltage, respectively, so that the second threshold voltage which follows the amplitude of the read signal and becomes the threshold voltage is selected. The voltage and the third voltage can be generated with high accuracy. Therefore, problems in terms of threshold voltage follow-up characteristics and calculation errors due to the use of an adder as in the prior art can be solved, and the speed of input signal state determination can be increased. A threshold voltage setting circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a block diagram of one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a voltage source shown in FIG.

FIG. 4 is a circuit diagram of the voltage source shown in FIG.

FIG. 5 is a circuit diagram of the buffer shown in FIG. 2;

FIG. 6 is a circuit diagram of a switch in the selection circuit shown in FIG. 2;

FIG. 7 is a block diagram of a system for reproducing information from a magnetic disk according to a partial response system to which the present invention is applied.

FIG. 8 is a block diagram showing a configuration of the state detector shown in FIG.

9 is a waveform chart showing setting of a threshold voltage used in the state detector shown in FIG.

FIG. 10 is a block diagram of a threshold voltage generation circuit shown in FIG. 8;

[Explanation of symbols]

 Reference Signs List 10 magnetic head 20 amplifier 30 equalizer 40 state detector 50 decoder 100 voltage generating circuit 111 reference voltage source 112 current source 113 first current mirror circuit 114 second current mirror circuit 200 selection circuit 300 controller

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takenori Oshima 1015 Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-2-226981 (JP, A) (58) Fields investigated (Int.Cl. ⁶ , DB name) G11B 20/10

Claims (6)

(57) [Claims] 1. Information using a partial response method
The first voltage of the node (t2) in the floating state
Is driven by a read signal read from the magnetic recording medium
With the partial response logic “1”.
A second voltage higher than the first voltage by a corresponding amplitude AL
And a third voltage lower by the amplitude AL.
A raw circuit (100), the first voltage and the second voltage based on a predetermined control signal.
Pressure and a third voltage to select the first and second voltages respectively.
Threshold voltage V_th ⁺And the second threshold voltage V_th ^-Output
And a selection circuit (200) for selecting
Threshold voltage setting circuit. 2. The voltage generating circuit according to claim 1, wherein said first voltage, said second voltage,
2. The threshold voltage setting circuit according to claim 1, further comprising a voltage source for generating said third voltage. 3. The voltage generating circuit (100) further comprises: a first current source (113) maintained at a sufficiently high impedance with respect to a power supply voltage or a ground; A second current source (114) kept at a high impedance, the first current source (113) and the second current source (11);
4) a resistor network (R; R24, R25) provided between the first current source and the first current source via the resistor network. 2. The power supply according to claim 1, wherein the voltage is generated by a voltage drop due to a current flowing through the current source.
The described threshold voltage generation circuit. 4. The voltage generating circuit (100) has a current source (112) that outputs a constant current corresponding to a reference voltage, and the first and the second current sources that receive the constant current output from the current source. A first current mirror circuit for outputting a second output current; a second current mirror circuit for receiving the first output current of the first current mirror circuit as an input and outputting a third output current (114) a series circuit (R; R24, R25) that receives the second output current of the first current mirror circuit and outputs the second output current as the third output current of the second current mirror circuit
The series circuit has first and second resistors connected in series, outputs the first voltage from a midpoint between the first and second resistors, and the other end of each of the first and second resistors. 2. The threshold voltage generating circuit according to claim 1, wherein said second and third voltages are output from said first and second terminals. 5. The threshold voltage generating circuit according to claim 4, wherein said second current is equal to said third current. 6. The device according to claim 4, wherein resistance values of said first and second resistors are smaller than equalization resistance values of said first current mirror circuit and said second current mirror circuit. Threshold voltage generation circuit.