JP2874441B2 - Testing method for low power supply voltage data retention characteristics of semiconductor static RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor static R
The present invention relates to a method for testing low power supply voltage data retention characteristics of an AM, and more particularly to a method for testing low power supply voltage data retention characteristics of a semiconductor static RAM that can accurately test data retention characteristics in a short time.

[0002]

2. Description of the Related Art As a conventional test method of a low power supply voltage data retention characteristic of a semiconductor static RAM, for example, a method as shown in FIGS. 2 and 3 is used. FIG.
FIG. 1 is a circuit diagram showing an example of a memory cell of a conventional general semiconductor static RAM. FIG. 3 is a graph showing the transition of the cell node potential during the data retention characteristic test of the memory cell shown in FIG. 2, and the dashed line in the figure shows the transition of the power supply voltage.

A MOS static memory cell 1 which is a memory cell of a semiconductor static RAM shown in FIG.
A flip-flop 2 for storing data, switching transistors 5 and 6, digit lines D, -D (D signal
It is constituted by No.) and the word line WL. The book
In the specification, an inverted signal of D is indicated by adding-before D.
Express. However, in the drawing, the inverted signal is a normal notation
According to the law, a bar is added to the code. The flip-flop 2 includes MOS transistors 3 and 4 and high resistance loads R1 and R2. The gate of MOS transistor 3 is set to cell node N. High resistance load R1,
A power supply VCC is applied to R2. The flip-flop 2 is connected to digit lines D and -D via switching transistors 5 and 6, and the gates of the switching transistors 5 and 6 are commonly connected to a word line WL. The switching transistors 5 and 6 are transfer gates that are turned on when the MOS static memory cell 1 is selected, and are turned off when not selected.

An example of a test for guaranteeing the data holding power supply voltage VCCDR of 2.0 V in the conventional MOS static memory cell 1 configured as described above will be described. First, “0” is written to all the memory cells at the recommended operation power supply voltage of 5 V (± 10%). That is, "H" is written to the cell node N by applying a low level voltage to the digit line D and a high level voltage to the digit line -D to increase the potential of the word line WL.

[0005] Thereafter, the measurement sample is set to a non-selected state, and the potentials of all the word lines fall. At this time, the potential of the cell node N has risen to the potential V shown in FIG. 3 via the high resistance load R1. In order to confirm the low power supply voltage data retention characteristic, when the power supply voltage is lowered from the potential V to the data retention power supply voltage VCCDR or lower, that is, about 1.9 V in a non-selected state, as shown in FIG. At the hold time t = Ta, a measurement capable of guaranteeing the data holding power supply voltage VCCDR of 2.0 V can be performed. Here, C is the cell node N
, R is the resistance value of the high resistance loads R1 and R2, and Ta is the predetermined data holding time shown in FIG.
After a lapse of a hold time (Ta or more shown in FIG. 3) sufficient for the potential of the cell node N to fall to 2.0 V or less,
The power supply voltage is raised to the potential V again, and it is read and confirmed whether or not the write data “0” is held.

The above test is also performed for the case of write data “1”, so that the data holding power supply voltage V
CCDR 2.0V can be guaranteed.

[0007]

However, in the above-described conventional method for testing the low power supply voltage data retention characteristic of a semiconductor static RAM, the test must be performed with a sufficient hold time as described above. Further, the resistance value R of the high resistance load changes significantly depending on the temperature. For these reasons, semiconductor static RAM, especially at low temperatures
When testing low power supply voltage data retention characteristics, the time constant becomes excessive and the hold time is required more than 10 seconds. Therefore, when testing a large number of products, a huge amount of time is required as a real problem. There is a problem that becomes.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a method for testing a low power supply voltage data retention characteristic of a semiconductor static RAM capable of performing an accurate data retention characteristic in a short time. The purpose is to:

[0009]

According to the method for testing the low power supply voltage data holding characteristic of a semiconductor static RAM according to the present invention, data is written to a semiconductor static RAM at a normal recommended operating voltage to be in a data holding state. rear,
Once, low permanent de than the power supply voltage data retention guarantee voltage
Power supply voltage drops to the first holding power supply voltage that can hold data
After the elapse of a predetermined retention time,
The power supply voltage is raised to the holding power supply voltage
The to Rukoto characterized the read operation for the certification.

[0010]

[0011]

In the method for testing the low power supply voltage data retention characteristics of a semiconductor static RAM according to the present invention, permanent data can be retained in a semiconductor static RAM after writing data at a normal recommended operating voltage to bring the data into a data retention state. The power supply voltage is reduced to a first holding power supply voltage (1 V or less) to rapidly lower the cell node potential. Next, after a predetermined retention time has elapsed, the second
The power supply voltage is raised to the holding power supply voltage (about 1.9 V), and the cell node potential is slowly lowered. Thereafter, a read operation for data confirmation is performed. By these,
The test method of the low power supply voltage data retention characteristic of the semiconductor static RAM according to the present invention can eliminate the risk of lowering the cell node potential more than necessary, and can accurately measure the data retention voltage of the semiconductor static RAM in a short time. be able to.

[0012]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a graph showing a transition of a cell node potential during a data retention characteristic test of a memory cell for explaining a test method of a low power supply voltage data retention characteristic of a semiconductor static RAM according to an embodiment of the present invention. is there. The dashed line in FIG. 1 indicates the transition of the power supply voltage. In this embodiment, the conventional semiconductor static RAM shown in FIG.
What is different from the test method of low power supply voltage data retention characteristics of
The point is that the power supply voltage Vcc is changed during the data retention characteristic test.

Next, a procedure of a test method of a low power supply voltage data retention characteristic of the semiconductor static RAM according to the present embodiment will be described in detail. An example in which the method for testing the low power supply voltage data retention characteristic of the semiconductor static RAM according to the embodiment of the present invention is applied to the memory cell of the conventional semiconductor static RAM shown in FIG. 2 will be described below.

After data writing, first, the first holding power supply voltage Vb shown in FIG. 1 capable of holding normal permanent data whose power supply voltage is lower than the data holding power supply voltage VCCDR (2.0 V).
(1.0 V or less), the potential of the cell node N shown in FIG. 2 changes according to the time constant determined by the parasitic capacitance C of the cell node N and the resistance R of the high resistance loads R1 and R2. It descends as indicated by a solid line or a broken line shown in FIG.
When the time constant is large, the potential of the cell node N does not immediately drop to the first holding power supply voltage Vb, and the data of the memory cell is held for a certain period of time. The manufacturing variation of the time constant CR in all the memory cells constituting the semiconductor static RAM is (CR) MAX / (CR) MIN ≦ 2
it is conceivable that. The solid line waveform in FIG.
At (CR) MIN, the potential of the cell node N at t = TMIN is equal to the data holding power supply voltage VCCDR.
(2.0 V). After t = TMIN, the cell node N
Power supply voltage to prevent the potential of
From the holding power supply voltage Vb to about 1.9 V of the second holding power supply voltage.

The dashed waveform shown in FIG. 1 represents a case where the time constant of the cell node N is (CR) MAX, and the potential of the cell node N rapidly drops until t = TMIN. Thereafter, the power supply voltage rises from the first holding power supply voltage Vb to about the second holding power supply voltage 1.9 V, so that the cell node N
At the time t = TMAX, becomes the data holding power supply voltage VCCDR (2.0 V).

According to the method described above, the potentials of the high-level cell nodes N in all the memory cells are changed to the data holding power supply voltage VCCDR during the hold time TMAX.
(2.0 V) or less, and there is no danger that the potential of the cell node N drops unnecessarily due to variations in the time constant CR and the like. After the hold, the power supply voltage is raised to the recommended operating voltage as in the conventional example, and reading is confirmed.

According to the test method of the low power supply voltage data retention characteristic of the semiconductor static RAM according to the present embodiment described above, the low power supply voltage data retention of the conventional semiconductor static RAM is lower than that of the conventional example at a low temperature. With the characteristic test method, a test that takes 10 seconds or more can be reduced to several seconds.

[0019]

As described above, according to the test method of the low power supply voltage data retention characteristic of the semiconductor static RAM according to the present invention, the data retention characteristic is temporarily measured during the data retention characteristic test.
By lowering the power supply voltage to a potential lower than the data retention guarantee voltage and capable of retaining permanent data, the data retention voltage of the semiconductor static RAM can be accurately measured in a short time.

[Brief description of the drawings]

FIG. 1 shows a semiconductor static RA according to an embodiment of the present invention.
6 is a graph illustrating transition of a cell node potential during a data retention characteristic test of a memory cell, for describing a test method of a low power supply voltage data retention characteristic of M.

FIG. 2 is a circuit diagram showing an example of a memory cell of a conventional semiconductor static RAM.

FIG. 3 is a graph showing transition of cell node potential during a data retention characteristic test of the memory cell shown in FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1; MOS static memory cell 2; Flip-flop 3, 4; Transistor 5, 6; Switching transistor D, -D ; Digit line WL;

Claims (1)

(57) [Claims] In a semiconductor static RAM, data is written at a normal recommended operating voltage, a data holding state is set, and then a power supply voltage is temporarily held lower than a data holding assurance voltage, and first data holding is possible. Power supply up to power supply voltage
Reduce the voltage, and after the specified retention time has elapsed, save the permanent data.
Raising the power supply voltage to a second holding power supply voltage
Te method of testing low power supply voltage data retention characteristic of the semiconductor static RAM and said to Rukoto a read operation for data confirmation.